Design of a high performance CMOS charge pump for phase-locked loop synthesizers

A new high performance charge pump circuit is designed and realized in 0.18μm CMOS process. A wide input ranged rail-to-rail operational amplifier and self-biasing cascode current mirror are used to enable the charge pump current to be well matched in a wide output voltage range.Furthermore,a method of adding a precharging current source is proposed to increase the initial charge current,which will speed up the settling time of CPPLLs.Test results show that the current mismatching can be less than 0.4%in the output voltage range of 0.4 to 1.7 V,with a charge pump current of 100μA and a precharging current of 70μA.The average power consumption of the charge pump in the locked condition is around 0.9 mW under a 1.8 V supply voltage.     

Low power high gain gain-controlled LNA and mixer for GNSS receivers Wei Binbin(魏斌斌)1, Jiang Jinguang(江金光)1,2,3*

A low power high gain gain-controlled LNA ＋ mixer for GNSS receivers is reported. The high gain LNA is realized with a current source load. Its gain-controlled ability is achieved using a programmable bias circuit. Taking advantage of the high gain LNA, a high noise figure passive mixer is adopted. With the passive mixer, low power consumption and high voltage gain of the LNA ＋ mixer are achieved. To fully investigate the performance of this circuit, comparisons between a conventional LNA ＋ mixer, a previous low power LNA ＋ mixer, and the proposed LNA ＋ mixer are presented. The circuit is implemented in 0.18 #m mixed-signal CMOS technology. A 3.8 dB noise figure, an overall 45 dB converge gain and a 10 dB controlled gain range of the two stages are measured. The chip occupies 0.24 mm2 and consumes 2 mA current under 1.8 V supply.     

A low power high gain gain-controlled LNAC＋mixer for GNSS receivers

A low power high gain gain-controlled LNAC+mixer for GNSS receivers is reported. The high gain LNA is realized with a current source load.Its gain-controlled ability is achieved using a programmable bias circuit. Taking advantage of the high gain LNA, a high noise figure passive mixer is adopted. With the passive mixer, low power consumption and high voltage gain of the LNACmixer are achieved. To fully investigate the performance of this circuit, comparisons between a conventional LNAC+mixer, a previous low power LNAC+mixer, and the proposed LNAC+mixer are presented. The circuit is implemented in 0.18 m mixed-signal CMOS technology. A 3.8 dB noise figure, an overall 45 dB converge gain and a 10 dB controlled gain range of the two stages are measured. The chip occupies 0.24 mm2and consumes 2 mA current under 1.8 V supply.     

采用PMOS底部电流源的低功耗电流自调整压控振荡器

This paper presents the design and implementation of a current self-adjusted VCO with low power consumption. In the proposed VCO, a bottom PMOS current source instead of a top one is adopted to decrease the tail noise. A current self-adjusted technique without additional external control signals is taken to ensure the VCO starts up in the whole band while keeping the power consumption relatively low. Meanwhile, the phase noise of the VCO at the low frequency （high Cvar） can be reduced by the technique. The circuit is implemented in 0.18 μm CMOS technology. The proposed VCO exhibits low power consumption of 〈1.6 mW at a 1.5 V supply voltage and a tuning range from 11.79 to 12.53 GHz. The measured phase noise at 1 MHz offset from the frequency 11.79 GHz is-104.7 dBc/Hz, and the corresponding FOM is -184.2 dBc/Hz.     

基于带隙的具有高稳定性欠压锁存方法

Highly reliable bandgap-based under-voltage-lockout(UVLO) methods are presented in this paper.The proposed under-voltage state to signal conversion methods take full advantages of the high temperature stability characteristics and the enhancement low-voltage protection methods which protect the core circuit from error operation; moreover,a common-source stage amplifier method is introduced to expand the output voltage range.All of these methods are verified in a UVLO circuit fabricated with a 0.5 μm standard BCD process technology.The experimental result shows that the proposed bandgap method exhibits a good temperature coefficient of 20 ppm/℃,which ensures that the UVLO keeps a stable output until the under-voltage state changes.Moreover,at room temperature,the high threshold voltage VTH+ generated by the UVLO is 12.3 V with maximum drift voltage of 80 mV,and the low threshold voltage VTH- is 9.5 V with maximum drift voltage of ±70 mV.Also,the low voltage protection method used in the circuit brings a high reliability when the supply voltage is very low.     

一种用于半桥功率IC的新型高压电平位移电路

In order to reduce the chip area and improve the reliability of HVICs,a new high-voltage level-shifting circuit with an integrated low-voltage power supply,two PMOS active resistors and a current mirror is proposed.The integrated low-voltage power supply not only provides energy for the level-shifting circuit and the logic circuit,but also provides voltage signals for the gates and sources of the PMOS active resistors to ensure that they are normally-on.The normally-on PMOS transistors do not,therefore,need to be fabricated in the depletion process.The current mirror ensures that the level-shifting circuit has a constant current,which can reduce the process error of the high-voltage devices of the circuit.Moreover,an improved RS trigger is also proposed to improve the reliability of the circuit.The proposed level-shifting circuit is analyzed and confirmed by simulation with MEDICI,and the simulation results show that the function is achieved well.     

An Ultra Low Steady-State Current Power-on-Reset Circuit in 65nm CMOS Technology

A novel Power-on-reset （POR） circuit is proposed with ultra-low steady-state current consumption. A band=gap voltage eomparator is used to generate a stable pull-up voltage. To eliminate the large current consumptions of the analog part, a power switch is adopted to cut the supply of band-gap voltage comparator, which gained ultra-low current consumption in steady-state after the POR rest process completed. The state of POR circuit is maintained through a state latch circuit. The whole cir- cuit was designed and implemented in 65rim C1V[OS tech- nology with an active area of 120ttm＊160~m. Experimental results show that it has a steady pull=up voltage of 0.69V and a brown-out voltage of 0.49V under a 1.2V supply voltage rising from 0V, plus its steady-state current is only 9hA. The proposed circuit is suitable to be integrated in system on chip to provide a reliable POR signal.     

Load adaptive start-up scheme for synchronous boost DC-DC converter

This paper presents a load adaptive soft-start scheme through which the inductor current of the synchronous boost DC-DC converter can trace the load current at the start-up stage. This scheme effectively eliminates the inrush-current and over-shoot voltage and improves the load capability of the converter. According to the output voltage, the start-up process is divided into three phases and at each phase the inductor current is limited to match the load. In the pre-charge phase, a step-increasing constant current gives a smooth rise of the output voltage which avoids inrush current and ensures the converter successfully starts up at different load situations. An additional ring oscillator operation phase enables the converter to start up as low as 1.4 V. When the converter enters into the system loop soft-start phase, an output voltage and inductor current detection methods make the transition of the phases smooth and the inductor current and output voltage rise steadily. Effective protection circuits such as short-circuit protection, current limit circuit and over-temperature protection circuit are designed to guarantee the safety and reliability of the chip during the start-up process. The proposed start-up circuit is implemented in a synchronous boost DC-DC converter based on TSMC 0.35μm CMOS process with an input voltage range 1.4-4.2 V, and a steady output voltage 5 V, and the switching frequency is 1 MHz. Simulation results show that inrush current and overshoot voltage are suppressed with a load range from 0-2.1 A, and inductor current is as low as 259 mA when the output shorts to the ground.     

一种带热滞回保护的高精度高电源抑制比带隙基准源

To meet the accuracy requirement for the bandgap voltage reference by the increasing data conversion precision of integrated circuits, a high-order curvature-compensated bandgap voltage reference is presented employing the characteristic of bipolar transistor current gain exponentially changing with temperature variations. In addition, an over-temperature protection circuit with a thermal hysteresis function to prevent thermal oscillation is proposed. Based on the CSMC 0.5 μ m 20 V BCD process, the designed circuit is implemented; the active die area is 0.17 × 0.20 mm². Simulation and testing results show that the temperature coefficient is 13.7 ppm/K with temperature ranging from –40 to 150 ℃, the power supply rejection ratio is –98.2 dB, the line regulation is 0.3 mV/V, and the power consumption is only 0.38 mW. The proposed bandgap voltage reference has good characteristics such as small area, low power consumption, good temperature stability, high power supply rejection ratio, as well as low line regulation. This circuit can effectively prevent thermal oscillation and is suitable for on-chip voltage reference in high precision analog, digital and mixed systems.     

一种应用于能量攫取系统的低功耗的工作于亚阈值区域的基准电压源的设计

We propose a bandgap reference, which works in sub-threshold regions to the reduce power consumption in applications such as those in energy harvesting systems that stimulate the development of power management for low power consumption applications.Measurements shows that the supply current of the proposed bandgap reference is only 6.87 μA, including a voltage buffer consuming 3.6 μA of supply current, when the supply voltage is 5 V.The supply voltage can vary from 3 to 11 V and the line regulation of the proposed bandgap reference output voltage is 0.875 mV/V at room temperature.The temperature coefficiency is 88.9 ppm from 10 to 100° C when the supply voltage is 5 V.     

Interfacial reaction and shear strength of SnAgCu-xNi/Ni solder joints during aging at 150 °C

The interfacial microstructure and shear strength of Sn3.8Ag0.7Cu-xNi (SAC-xNi, x = 0.5, 1, and 2) composite solders on Ni/Au finished Cu pads were investigated in detail after aging at 150 °C for up to 1000 h. The interfacial characteristics of composite solder joints were affected significantly by the weight percentages of added Ni micro-particles and aging time. After aging for 200 h, the solder joints of SAC, SAC-0.5Ni and -1Ni presented duplex intermetallic compound (IMC) layers regardless of the initial interfacial structure on as-reflowed joints, whose upper and lower IMC layers were comprised of (CuNi)₆Sn₅ and (NiCu)₃Sn₄, respectively. Only a single (NiCu)₃Sn₄ IMC layer was ever observed at the SAC-2Ni/Ni interface on whole aging process. Based on the compositional analysis, the amount of Ni within the IMC regions increased as the proportion of Ni addition increased. The IMC (NiCu)₃Sn₄ layer thickness on the interface of SAC and SAC-0.5Ni grew more slowly when compared to that of SAC-1Ni and -2Ni, while for the (CuNi)₆Sn₅ layer the reverse is true. Except the IMCs sizes are increased with increased aging time, the interfacial IMCs tended to transfer their morphologies to polyhedra. In all composite joints testing, the shear strengths were approximately equal to non-composite joints. The fracturing observed during shear testing of composite joints occurred in the bulk solder, indicating that the SAC-xNi/Ni solder joints had a desirable joint reliability.     

有机发光二极管中ADN掺杂ErQ的1.54μm电致发光

自行设计了基于8-羟基喹啉铒(ErQ)为发射层(EMLs)和二硝酰胺铵(ADN)为蓝光主体材料的近红外有机发光二级管.器件的基本结构为(p-Si/NPB/EML/Bphen/Bphen:Cs2CO3/Sm/Au),设计并比较了三套不同发射层结构(ErQ/ADN为双层结构器件,(ErQ/ADN)×3为多层结构器件,ErQ:ADN为掺杂结构器件)的器件.三组器件在一定的偏压下,均可发出1.54μm的光,对应三价铒离子4I13/2→4I15/2的跃迁.其中,ADN:ErQ(1∶1)掺杂结构的近红外电致发光强度是ADN/ErQ双层结构中的三倍.此外,不同掺杂浓度的ADN:ErQ复合膜做了以下表征:吸收谱、光致发光谱和荧光寿命谱.实验结果证实了在近红外电致发光过程中存在从ADN主体分子到ErQ发射分子的高效率的能量转移.     

BNBST无铅压电陶瓷的制备工艺研究

设计了（Bi0.55Na0.5）1-X（BaaSrb）xTiO3（BNBST[100x-100a／100b]）无铅压电陶瓷新体系。该体系压电陶瓷具有工艺特性及压电响应好，压电常数高的特点，且有实际应用前景的新型压电陶瓷材料体系。采用传统的陶瓷工艺制备了（Bi0.55Na0.5）1-X（BaaSrb）xTiO3无铅压电陶瓷，研究了制备工艺参数对其物化结构性能的影响。生料的热重-差热（TGA-DTA）分析表明，粉料合成过程中，先是SrTiO3、BaTiO3的形成，然后是（Bi0．5Na0．5）Tio，的形成，同时三者形成固溶体；密度测试表明，陶瓷的体积密度随烧结温度的升高而增大，可较易获得理论密度94％的陶瓷；X-射线能谱分析（EDAX）研究表明，陶瓷的Bi、Na的挥发随着烧结温度的升高而加剧。研究结果表明，要制备性能优良的无铅压电陶瓷，需要精确控制制备工艺。     

Emerging interconnects: a state-of-the-art review and emerging solutions

Aluminium was a primary material for interconnection in integrated circuits (ICs) since their inception. Later, copper was introduced as interconnect material which has better metallic conductivity and resistance to electromigration. As the aggressive technology scaling continues, the copper resistivity increased because of size effects, which causes increase in delay, power dissipation and electromigration. The need to reduce the resistor-capacitor??????? delay, dynamic power utilisation and the crosstalk commotion is as of now the fundamental main impetus behind the presentation of new materials. The purpose of this paper is to do a survey of interconnect material used in IC from introduction of ICs to till date. This paper studies and reviews new materials available for interconnect application which are optical interconnects, carbon nanotube (CNT), graphene nanoribbons (GNRs) and silicon nanowires which are alternatives to copper. While doing a survey of interconnect material, it is found that multiwalled CNTs, multilayer GNR and mixed CNT bundles are promising candidates and are ultimate choice that can strongly address the problems faced by copper but on integration basis copper would last for coming years.     

钠离子对poly(dT).poly(dA).poly(dT)三螺旋DNA分子呼吸模式的影响

利用分子结构的螺旋对称性,建立了一个包括钠离子的三链DNA分子poly(dT)*poly(dA)*poly(dT)的晶格动力学模型,计算了poly(dT)*poly(dA)*poly(dT)的氢键呼吸模式.结果发现钠离子的加入明显地淬灭了位于较低频率的几个最为强烈的Hoogensteen氢键呼吸模式,而对Watson-Crick氢键呼吸模式影响不明显,这说明钠离子能提高poly(dT)*poly(dA)*poly(dT)三螺旋结构的稳定性.该计算结果很好地解释了poly(dT)*poly(dA)*poly(dT)的热融化实验.     

聚对苯撑苯并双(口恶)唑发光及其器件制备

采用光谱技术,研究了聚对苯撑苯并双(口恶)唑(PBO)溶液的光敏发光特性,并用相对法估算出溶液发光效率在50%范围.结合光谱技术、半导体电学和电化学等研究手段,具体研究了以PBO为发光层的单层电致发光器件,研究结果显示,电致发光与薄膜的光致发光有具有相同的发光中心,峰值位于510 nm左右.同时发现,由于存制备过程中不同处理条件使得不同厚度薄膜残留的掺杂物质浓度不同,从而引起薄膜的导电性的不同.使得器件的阈值场强随PBO厚度的减小而逐渐增加.     

人小肠粘膜免疫酶的定位研究—光镜和电镜免疫组织化学染色法

本文对免疫酶组织化学的样品制备程序和染色方法做了详细的阐述。用直接法、间接法和ABC法,对人小肠免疫酶的定位,进行了光镜和电镜的观察,染色阳性反应显著,获得了满意的效果。并对染色技巧做了分析和探讨。     

Arsenic deposition as a precursor layer on silicon (211) and (311) surfaces

We investigate the properties of arsenic (As) covered Si(211) and Si(311) surfaces by analyzing data from x-ray photoelectron spectroscopy (XPS) and low-energy electron diffraction (LEED) images. We then create a model using total surface energy calculations. It was found that both Si(211) and Si(311) had 0.68±0.08 surface As coverage. Si(211) had 0.28±0.04 Te coverage and Si(311) had 0.24±0.04 Te coverage. The Si(211) surface replaces the terrace and trench Si atoms with As for a lower surface energy, while the Si edge atoms form dimers. The Si(311) surface replaces all terrace atoms and adsorbs an As dimer every other edge site. These configurations imply an improvement in the mean migration path from the bare silicon surface by allowing the impinging atoms for the next epitaxial layer, tellurium (Te), to bind at every other pair of edge atoms, and not the step terrace sites. This would ensure a nonpolar, B-face growth.     

盲多用户检测技术中的恒模算法分析

恒模算法（CMA）是一种广泛应用于阵列处理、均衡和多用户检测中的盲算法。现对恒模算法及其在盲多用户检测技术中的应用进行了分析,并指出其研究方向。     

Joint estimation of TOA and DOA in IR-UWB system using a successive propagator method

Impulse radio ultra-wideband (IR-UWB) ranging and positioning require accurate estimation of time-of-arrival (TOA) and direction-of-arrival (DOA). With receiver of two antennas, both of the TOA and DOA parameters can be estimated via two-dimensional (2D) propagator method (PM), in which the 2D spectral peak searching, however, renders much higher computational complexity. This paper proposes a successive PM algorithm for joint TOA and DOA estimation in IR-UWB system to avoid 2D spectral peak searching. The proposed algorithm firstly gets the initial TOA estimates in the two antennas from the propagation matrix, then utilises successively one-dimensional (1D) local searches to achieve the estimation of TOAs in the two antennas, and finally obtains the DOA estimates via the difference in the TOAs between the two antennas. The proposed algorithm, which only requires 1D local searches, can avoid the high computational cost in 2D-PM algorithm. Furthermore, the proposed algorithm can obtain automatically paired parameters and has better joint TOA and DOA estimation performance than conventional PM algorithm, estimation of signal parameters via rotational invariance techniques algorithm and matrix pencil algorithm. Meanwhile, it has very close parameter estimation to that of 2D-PM algorithm. We have also derived the mean square error of TOA and DOA estimation of the proposed algorithm and the Cramer-Rao bound of TOA and DOA estimation in this paper. The simulation results verify the usefulness of the proposed algorithm.