A digital input class-D audio amplifier with sixth-order PWM

A digital input class-D audio amplifier with a sixth-order pulse-width modulation(PWM)modulator is presented.This modulator moves the PWM generator into the closed sigma–delta modulator loop.The noise and distortions generated at the PWM generator module are suppressed by the high gain of the forward loop of the sigma–delta modulator.Therefore,at the output of the modulator,a very clean PWM signal is acquired for driving the power stage of the class-D amplifier.A sixth-order modulator is designed to balance the performance and the system clock speed.Fabricated in standard 0.18 m CMOS technology,this class-D amplifier achieves 110 dB dynamic range,100 dB signal-to-noise rate,and 0.0056%total harmonic distortion plus noise.     

A 1.2-V, 84-dB Σ△ ADM in 0.18-μm digital CMOS technology

A low power and low voltage∑△analog-to-digital modulator is realized with digital CMOS technology, which is due to full compensated depletion mode capacitors.Compared with mixed signal technology,this type of modulator is more compatible for pure digital applications.A pseudo-two-stage class-AB OTA is used in switchedcapacitor integrators for low voltage and low power.The modulator is realized in standard SMIC 0.18μm 1P6M digital CMOS technology.Measured results show that with 1.2 V supply voltage and a 6 MHz sample clock,the dynamic range of the modulator is 84 dB and the total power dissipation is 2460μW.     

A 1.1 mW 87 dB dynamic range △∑ modulator for audio applications

This paper presents a 1.1 mW 87 dB dynamic range third orderΔΣmodulator implemented in 0.18μm CMOS technology for audio applications.By adopting a feed-forward multi-bit topology,the signal swing at the output of the first integrator can be suppressed.A simple current mirror single stage OTA with 34 dB DC gain working under 1 V power supply is used in the first integrator.The prototype modulator achieves 87 dB DR and 83.8 dB peak SNDR across the bandwidth from 100 Hz to 24 kHz with 3 kHz input signal.     

A sub-sampling 4-bit 1.056-GS/s flash ADC with a novel track and hold amplifier for an IR-UWB receiver

A sub-sampling 4-bit 1.056-GS/s flash ADC with a novel track and hold amplifier(THA) in 0.13μm CMOS for an impulse radio ultra-wideband(IR-UWB) receiver is presented.The challenge is in implementing a sub-sampling ADC with ultra-high input signal that further exceeds the Nyquist frequency.This paper presents,to our knowledge for the second time,a sub-sampling ADC with input signals above 4 GHz operating at a sampling rate of 1.056 GHz.In this design,a novel THA is proposed to solve the degradation in amplitude and improve the linearity of signal with frequency increasing to giga Hz.A resistive averaging technique is carefully analyzed to relieve noise aliasing.A low-offset latch using a zero-static power dynamic offset cancellation technique is further optimized to realize the requirements of speed,power consumption and noise aliasing.The measurement results reveal that the spurious free dynamic range of the ADC is 30.1 dB even if the input signal is 4.2 GHz sampled at 1.056 GS/s.The core power of the ADC is 30 mW,excluding all of the buffers,and the active area is 0.6 mm~2.The ADC achieves a figure of merit of 3.75 pJ/conversion-step.     

A 455 nW 220 fJ/conversion-step 12 bits 2 kS/s SAR ADC for portable biopotential acquisition systems

An ultra-low power 12 bits 2 kS/s successive approximation register analog-to-digital converter(ADC) is presented.For power optimization,the voltage supply of the digital part is lowered,and the offset voltage of the latch is self-calibrated.Targeted for better linearity and lower noise,an improved digital-to-analog converter capacitor array layout strategy is presented,and a low kick-back noise latch is proposed.The chip was fabricated by using 0.18μm 1P6M CMOS technology.The ADC achieves 61.8 dB SNDR and dissipates 455 nW only,resulting in a figure of merit of 220 fJ/conversion-step.The ADC core occupies an active area of only 674×639μm~2.     

应用于K波段的宽锁定范围低功耗注入锁定三倍频器

This paper presents a wide locking range and low DC power injection-locked frequency tripler for Kband frequency synthesizers application. The proposed ILFT employs a variable current source to decouple the injection signal path and the bias current so that the third harmonic of the injection signal can be maximized to enlarge the locking range. Meanwhile, a 2-bit digital control capacity array is used to further increase the output frequency locking range. It is implemented in a 130-nm CMOS process and occupies a chip area of 0.7 0.8 mm2 without pads. The measured results show that the proposed ILFT can achieve a whole locking range from 18 to21 GHz under the input signal of 4 d Bm and the core circuit dissipates only 4 m W of DC power from a 0.8 V supply voltage. The measured phase noise degradation from that of the injection signal is only 10 d B at 1 MHz offset.     

A 14-bit 40-MHz analog front end for CCD application

A 14-bit, 40-MHz analog front end (AFE) for CCD scanners is analyzed and designed. The proposed system incorporates a digitally controlled wideband variable gain amplifier (VGA) with nearly 42 dB gain range, a correlated double sampler (CDS) with programmable gain functionality, a 14-bit analog-to-digital converter and a programmable timing core. To achieve the maximum dynamic range, the VGA proposed here can linearly amplify the input signal in a gain range from -1.08 to 41.06 dB in 6.02 dB step with a constant bandwidth. A novel CDS takes image information out of noise, and further amplifies the signal accurately in a gain range from 0 to 18 dB in 0.035 dB step. A 14-bit ADC is adopted to quantify the analog signal with optimization in power and linearity. An internal timing core can provide flexible timing for CCD arrays, CDS and ADC. The proposed AFE was fabricated in SMIC 0.18 μm CMOS process. The whole circuit occupied an active area of 2.8×4.8 mm² and consumed 360 mW. When the frequency of input signal is 6.069 MHz, and the sampling frequency is 40 MHz, the signal to noise and distortion (SNDR) is 70.3 dB, the effective number of bits is 11.39 bit.     

一个单通道10位160兆每秒的逐次逼近式模数转换器

This paper demonstrates a single-channel 10-bit 160 MS/s successive-approximation-register （SAR） analog-to-digital converter （ADC） in 65 nm CMOS process with a 1.2 V supply voltage. To achieve high speed, a new window-opening logic based on the asynchronous SAR algorithm is proposed to minimize the logic delay, and a partial set-and-down DAC with binary redundancy bits is presented to reduce the dynamic comparator offset and accelerate the DAC settling. Besides, a new bootstrapped switch with a pre-charge phase is adopted in the track and hold circuits to increase speed and reduce area. The presented ADC achieves 52.9 dB signal-to-noise distortion ratio and 65 dB spurious-free dynamic range measured with a 30 MHz input signal at 160 MHz clock. The power consumption is 9.5 mW and a core die area of 250 ×200 μm^2 is occupied.     

一种基于开关型运放和双向循环移位DWA的0.9V Delta-Sigma模数转换器

This paper presents a low-power high-precision switched-opamp(SO)-based delta-sigma(△Σ) analog-to -digital converter(ADC).The proposed SO design allows circuit operation at sub-1 V supply voltage,only needs to work in half of a clock cycle,and thus is suitable for low power applications.In addition,an opamp-sharing technique is applied to save on hardware overheads.Due to the use of a dual cycle shift data weighted averaging (DCS-DWA) technique,mismatch errors caused in the feedback DAC have been eliminated without introducing signal-dependent tones.The proposed ADC has been implemented in a standard 0.18μm process and measured to have a 92.2 dB peak SNDR and 94.1 dB dynamic range with 25 kHz signal bandwidth.The power consumption is 58μW for the modulator at 0.9 V supply voltage and 96μW for the decimation filter,which translate to the figure-of-merit(FOM) of 35.4 fJ/step for the solo modulator,and 94 fJ/step for the whole system.     

An A/D interface based on ΣΔ modulator for thermal vacuum sensor ASICs

A new Σ Δ modulator architecture for thermal vacuum sensor ASICs is proposed. The micro-hotplate thermal vacuum sensor fabricated by surface-micromachining technology can detect the gas pressure from 1 to 10⁵ Pa. The amplified differential output voltage signal of the sensor feeds to the Σ Δ modulator to be converted into digital domain. The presented Σ Δ modulator makes use of a feed-forward path to suppress the harmonic distortions and attain high linearity. Compared with other feed-forward architectures presented before, the circuit complexity, chip area and power dissipation of the proposed architecture are significantly decreased. The correlated double sampling technique is introduced in the 1st integrator to reduce the flicker noise. The measurement results demonstrate that the modulator achieves an SNDR of 79.7 dB and a DR of 80 dB over a bandwidth of 7.8 kHz at a sampling rate of 4 MHz. The circuit has been fabricated in a 0.5 μ m 2P3M standard CMOS technology. It occupies an area of 5 mm² and dissipates 9 mW from a single 3 V power supply. The performance of the modulator meets the requirements of the considered application.     

A taxonomy of ADC architectures for ICT engineering curricula

This paper presents the various Analog to Digital Converter (ADC) architectures within a structured frame in order to outline the basic design choices and to point out some additional degrees of freedom beyond the classic ADC circuits. The parameters for a detailed analysis of performance, speed, precision, costs are identified and discussed. Within this frame, the paper identifies variations to the classic ADC structures, which provide additional speed/cost tradeoffs. The aim is to provide students an understanding of various ADC techniques, allowing a motivated choice of the most suitable structure for each specific application at the systems design level. This approach has been used in teaching ADCs for several years, and the paper includes a discussion of results and student feedback.     

几种A／D转换技术及性能特点的分析

通过对四种最为常用的模数转换技术及其特点加以分析比较，阐述其工作原理、性能特点及其优缺点．以助于读者更好地选择适合自己设计的模数转换器。     

模数转换技术的分析与应用

从市场角度入手分析了ADC在电子技术发展中的重要性及其特殊性;然后分析ADC不同的算法组合,如并行比较型、逐次逼近型、积分型、∑-Δ型、流水线型ADC,详细比较各种算法的优缺点及主要用途;最后结合工艺的发展,展望了ADC的发展趋势和存在困难。并指出在选用ADC时,不仅要考虑应用的精度、速度等主要指标,还要考虑输入信号的形式、输入信号范围、输入通道类型和数量、工作电源等多种具体功能上的差异。     

高分辨率∑-△ADC的原理及应用

MAX1402是一种高分辨率、高精度ADC.文中主要介绍它的应用和设计中的注意事项.     

可编程模拟器件在接收机动态可重构结构中的应用设计

为进一步提高接收机的动态可重构性能，对基于可编程模拟器件的接收机前端结构进行了优化设计，并给出了具体的设计方案，证明了接收机前端动态可重构的可行性。     

一种基于人眼视觉特性图像传感器的研究

基于韦伯-费希纳法则这一人眼视觉特性重要定律,提出对传统图像传感器线性量化进行改进,引入了对数量化,并设计了一种结构精简的多分辨率ADC,对图像传感器的线性输出信号进行对数量化.使用FPGA验证表明,量化时间缩短为256个时钟周期,且综合资源大幅降低.     

低功耗高速全差动放大器驱动ADC实现高精度

在高分辨率和高精度应用中,怎样才能使ADC在严格的功率限制内实现宽泛的范围？以往有二种解决方案,一种是单端解决方案,这种方案设计和电路都比较复杂、需多个放大器,匹配问题也不好解决。另一种方案是采用差动放大器,但是噪声和功耗都比较大,对驱动ADC来讲也不是十分理想。     

提高检测仪器测量精度的几种措施

文中介绍微型传感器中机械和电子元件的热噪声（热波动）对测量精度的影响，并分析其原因。最后提出几种提高精度的有效措施。     

高速模数转换器动态参数的定义和测试

随着集成工艺的发展,高速模数转换器的性价比不断提高,其应用范围也越来越广,特别是在通信领域,高速ADC的发展为软件无线电技术奠定了基础,本文主要讨论高速ADC测试方法,以MAXIM新一代3V、10位高速模数转换器的测试为基础,详细讨论硬件的配置、软件工具和用于数据采样和分析的仪器。