A realization of a below-1-V operational and 30-MS/s sample-and-hold IC with a 56-dB signal-to-noise ratio by applying the current-based circuit approach

This paper demonstrates the low-voltage and low-power operation of a MOS sample-and-hold circuit while preserving speed and accuracy, aiming at the realization of a pipelined low-voltage and low-power analog-to-digital converter on a system large-scale integrated circuit. It was fabricated by utilizing 0.35-/spl mu/m CMOS technology. The main feature of this circuit is that all the input, signals, and output are in the current form. The circuit consists of simple current mirrors. In order to eliminate the signal-dependent current transfer ratio error, voltages at the drain terminals of mirror transistors are fixed as constant. A source degeneration resistor, which is a transistor in the triode operational region, is connected to a mirror transistor in order to alleviate the influence of the threshold and transconductance parameter variations. Control signals are boosted in voltage and applied to the gate of switch NMOS transistors in the signal path in order to reduce the on-resistance of analog switches. A differential configuration is adopted throughout the entire circuit and effectively cancels switch feedthrough errors. As a result, a 30-MS/s operation with a signal-to-noise ratio (SNR) of 56 dB from a 1-V supply has been achieved, when the input current is /spl plusmn/200 /spl mu/A. The chip even operated down to 0.85 V with a 20-MHz clock. The SNR was measured as 50 dB with an input current of /spl plusmn/100 /spl mu/A.     

A 1.5-V 50-MHz pseudodifferential CMOS sample-and-hold circuit with low hold pedestal

This paper describes the design strategy and implementation of a low-voltage pseudodifferential double-sampled timing-skew-insensitive sample-and-hold (S/H) circuit with low hold pedestal based on the Miller-effect scheme. The S/H circuit employs bootstrapped switches in order to facilitate low voltage operation. The design considerations for each building block are described in detail. The S/H circuit has been designed using a 0.35-/spl mu/m 2P4M CMOS technology and experimental results are presented. The 1.5-V S/H circuit operates up to a sampling frequency of 50 MHz with less than -54.6 dB of total harmonic distortion for an input sinusoidal amplitude of 0.8 V/sub pp/. In these conditions, a differential hold pedestal of less than 0.8 mV, 1.6 ns acquisition time at 0.8-V step input, and 0.8 V/sub pp/ full-scale differential input range are achieved.     

A 100-Mb/s 2.8-V CMOS current-mode analog Viterbi decoder

This paper describes a 4-state rate-1/2 analog convolutional decoder fabricated in 0.8-μm CMOS technology. Although analog implementations have been described in the literature, this decoder is the first to be reported realizing the add-compare-select section entirely with current-mode analog circuits. It operates at data rates up to 115 Mb/s (channel rate 230 Mb/s) and consumes 39 mW at that rate from a single 2.8-V power supply. At a rate of 100 Mb/s, the power consumption per trellis state is about 1/3 that of a comparable digital system. In addition, at 50 Mb/s (the only rate at which comparative data were available), the power consumption per trellis state is similarly about 1/3 that of the best competing analog realization (i.e., excluding, for example, PR4 detectors which use a simplified form of the Viterbi algorithm). The chip contains 3.7 K transistors of which less than 1 K are used in the analog part of the decoder. The die has a core area of 1 mm², of which about 1/3 contains the analog section. The measured performance is close to that of an ideal Viterbi decoder with infinite quantization. In addition, a technique is described which extends the application of the circuits to decoders with a larger number of states. A typical example is a 64-state decoder for use in high-speed satellite communications     

A 3-V 340-mW 14-b 75-Msample/s CMOS ADC with 85-dB SFDR at Nyquistinput

This paper describes the design of a 14-b 75-Msample/s pipeline analog-to-digital converter (ADC) implemented in a 0.35-μm double-poly triple-metal CMOS process. The ADC uses a 4-b first stage to relax capacitor-matching requirements, buffered bootstrapping to reduce signal-dependent charge injection, and a flip-around track-and-hold amplifier with wide common-mode compliance to reduce noise and power consumption. It achieves 14-b accuracy without calibration or dithering. Typical differential nonlinearity is 0.6 LSB, and integral nonlinearity is 2 LSB. The ADC also achieves 73-dB signal-to-noise ratio, and 85-dB spurious-free dynamic range over the first Nyquist band. The 7.8-mm² ADC operates with a 2.7- to 3.6-V supply, and dissipates 340 mW at 3 V     

A 1.5-V, 10-bit, 14.3-MS/s CMOS pipeline analog-to-digitalconverter

A 1.5-V, 10-bit, 14.3-MS/s pipeline analog-to-digital converter was implemented in a 0.6 μm CMOS technology. Emphasis was placed on observing device reliability constraints at low voltage. MOS switches were implemented without low-threshold devices by using a bootstrapping technique that does not subject the devices to large terminal voltages. The converter achieved a peak signal-to-noise-and-distortion ratio of 58.5 dB, maximum differential nonlinearity of 11.5 least significant bit (LSB), maximum integral nonlinearity of 0.7 LSB, and a power consumption of 36 mW     

A 1.5-V 45-mW direct-conversion WCDMA receiver IC in 0.13-/spl mu/m CMOS

A 2-GHz direct-conversion receiver for wide-band code division multiple access (WCDMA) is presented. It includes two low-noise amplifiers (LNAs), an I/Q demodulator, and two sixth-order baseband channel select filters with programmable gain. Quadrature local oscillator (LO) signals are generated on chip in a frequency divider flip-flop. An external interstage filter between the LNAs rejects transmitter leakage to relax demodulator linearity requirements. A low-voltage demodulator topology improves linearity as well as demodulator output pole accuracy. The active-RC baseband filter uses a programmable servo loop for offset compensation and provides an adjacent channel rejection of 39 dB. Programmable gain over 71-dB range in 1-dB steps is merged with the filter to maximize dynamic range. An automatic on-chip frequency calibration scheme provides better than 1.5% corner frequency accuracy. The receiver is integrated in a 0.13-/spl mu/m CMOS process with metal-insulator-metal (MIM) capacitors. Measured receiver performance includes a 6.5-dB noise figure, IIP2 of +27 dBm, and IIP3 of -8.6 dBm. Power consumption is 45 mW.     

14位20 MS/s CMOS流水线A/D转换器

介绍了一种14位20 MS/s CMOS流水线结构A/D转换器的设计.采用以内建晶体管失配设置阈值电压的差分动态比较器,省去了1.5位流水线结构所需的±0.25 VR两个参考电平;采用折叠增益自举运算放大器,获得了98 dB的增益和900 MHz的单位增益带宽,基本消除了运放有限增益误差的影响;采用冗余编码和数字校正技术,降低了对比较器失调的敏感性,避免了余差电压超限引起的误差.电路采用0.18 μm CMOS工艺,3.3 V电源电压.仿真中,对频率1 MHz、峰值1 V的正弦输入信号的转换结果为:SNDR 85.6 dB,ENOB 13.92位,SFDR 96.3 dB.     

A 15-Gb/s 2.4-V Optical Receiver Using a Ge-on-SOI Photodiode and a CMOS IC

We report the fastest (15 Gb/s) and lowest voltage (2.4V) all-silicon-based optical receiver to date. The receiver consists of a lateral, interdigitated, germanium-on-silicon-on-insulator (Ge-on-SOI) photodiode wire-bonded to a 0.13-$mu$m complementary metal–oxide–semiconductor (CMOS) receiver integrated circuit (IC). The photodiode has an external quantum efficiency of 52% at$lambda=850$nm and a dark current of 10 nA at$-$2 V. The small-signal transimpedance of the receiver is 91-dB$Omega$and the bandwidth is 6.6 GHz. At a bit-error rate of$10^-12$and$lambda=850$nm; the receiver exhibits sensitivities of$-$11.0,$-$9.6, and$-$7.4 dBm at 12.5, 14, and 15 Gb/s, respectively. The receiver operates error-free at rates up to 10 Gb/s with an IC supply voltage as low as 1.5 V and with a photodiode bias as low as 0.5 V. The power consumption is 3 to 7 mW/Gb/s. The Ge-on-SOI photodiode is well suited for integration with CMOS processing, raising the possibility of producing high-performance, low-voltage, monolithically integrated receivers based on this technology in the future.     

A 3.3-V 12-b 50-MS/s A/D converter in 0.6-μm CMOS with over80-dB SFDR

A 12-b analog-to-digital converter (ADC) is optimized for spurious-free dynamic range (SFDR) performance at low supply voltage and suitable for use in modern wireless base stations. The 6-7-b two-stage pipeline ADC uses a bootstrap circuit to linearize the sampling switch of an on-chip sample-and-hold (S/H) and achieves over 80-dB SFDR for signal frequencies up to 75 MHz at 50 MSample/s (MSPS) without trimming, calibration, or dithering. INL is 1.3 LSB, differential nonlinearity (DNL) is 0.8 LSB. The 6-b and 7-b flash sub-ADCs are implemented efficiently using offset averaging and analog folding. In 0.6-μm CMOS, the 16-mm² ADC dissipates 850 mW     

A 3.3-V single-poly CMOS audio ADC delta-sigma modulator with 98-dB peak SINAD and 105-dB peak SFDR

This paper presents a second-order ΔΣ modulator for audio-band analog-to-digital conversion implemented in a 3.3-V, 0.5-μm, single-poly CMOS process using metal-metal capacitors that achieves 98-dB peak signal-to-noise-and-distortion ratio and 105-dB peak spurious-free dynamic range. The design uses a low-complexity, first-order mismatch shaping 33-level digital-to-analog converter and a 33-level flash analog-to-digital converter with digital common-mode rejection and dynamic element matching of comparator offsets. These signal-processing innovations, combined with established circuit techniques, enable state-of-the art performance in CMOS technology optimized for digital circuits     

A 10 bit 20 MS/s 3 V supply CMOS A/D converter

A 10 bit CMOS A/D converter with 3 V power supply has been developed for being integrated into system VLSI's. In this A/D converter, redundant binary encoders named “twin encoders” enhance tolerance to substrate noise, together with employing differential amplifiers in comparators. The bias circuit using a replica of the amplifier is developed for biasing differential comparators with 3 V power supply. Subranging architecture along with a multilevel tree decoding structure improves dynamic performance of the ADC at 3 V power supply. The A/D converter is fabricated in double-polysilicon, double-metal, 0.8 μm CMOS technology. The experimental results show that the ADC operates at 20 MS/s and the twin encoders suppress the influence of substrate noise effectively. This ADC has a single power supply of 3 V, and dissipates 135 mW at 20 MS/s operation     

A 1.2-V 19.2-mW 10-bit 30-MS/s pipelined ADC in 0.13-icm CMOS

A 10-bit 30-MS/s pipelined analog-to-digital converter (ADC) is presented.For the sake of lower power and area,the pipelined stages are scaled in current and area,and op amps are shared between the successive stages.The ADC is realized in the 0.13-tt,m 1-poly 8-copper mixed signal CMOS process operating at 1.2-V supply voltage.Design approaches are discussed to overcome the challenges associated with this choice of process and supply voltage,such as limited dynamic range,poor analog characteristic devices,the limited linearity of analog switches and the embedded sub-1-V bandgap voltage reference.Measured results show that the ADC achieves 55.1-dB signal-to-noise and distortion ratio,67.5-dB spurious free dynamic range and 19.2-mW power under conditions of 30 MSPS and 10.7-MHz input signal.The FoM is 0.33 pJ/step.The peak integral and differential nonlinearities are 1.13 LSB and 0.77 LSB,respectively.The ADC core area is 0.94 mm2.     

A 1.5-V 75-dB dynamic range third-order G/sub m/-C filter integrated in a 0.18-/spl mu/m standard digital CMOS process

A design methodology of a CMOS linear transconductor for low-voltage and low-power filters is proposed in this paper. It is applied to the analog baseband filter used in a transceiver designed for wireless sensor networks. The transconductor linearization scheme is based on regulating the drain voltage of triode-biased input transistors through an active-cascode loop. A third-order Butterworth low-pass filter implemented with this transconductor is integrated in a 0.18-/spl mu/m standard digital CMOS process. The filter can operate down to 1.2-V supply voltage with a cutoff frequency ranging from 15 to 85 kHz. The 1% total harmonic distortion dynamic range measured at 1.5 V for 20-kHz input signal and 50-kHz cutoff frequency is 75 dB, while dissipating 240 /spl mu/W.     

A 1.8-V 22-mW 10-bit 30-MS/s Pipelined CMOS ADC for Low-Power Subsampling Applications

This paper describes a 10-bit 30-MS/s subsampling pipelined analog-to-digital converter (ADC) that is implemented in a 0.18 mum CMOS process. The ADC adopts a power efficient amplifier sharing architecture in which additional switches are introduced to reduce the crosstalk between the two opamp-sharing successive stages. A new configuration is used in the first stage of the ADC to avoid using a dedicated sample-and-hold amplifier (SHA) circuit at the input and to avoid the matching requirement between the first multiplying digital-to-analog converter (MDAC) and flash input signal paths. A symmetrical gate-bootstrapping switch is used as the bottom-sampling switch in the first stage to enhance the sampling linearity. The measured differential and integral nonlinearities of the prototype are less than 0.57 least significant bit (LSB) and 0.8 LSB, respectively, at full sampling rate. The ADC exhibits higher than 9.1 effective number of bits (ENOB) for input frequencies up to 30 MHz, which is the twofold Nyquist rate (fs/2), at 30 MS/s. The ADC consumes 21.6 mW from a 1.8-V power supply and occupies 0.7 mm², which also includes the bandgap and buffer amplifiers. The figure-of-merit (FOM) of this ADC is 0.26 pJ/step.     

A 14-b 12-MS/s CMOS pipeline ADC with over 100-dB SFDR

A 1.8-V 14-b 12-MS/s pseudo-differential pipeline analog-to-digital converter (ADC) using a passive capacitor error-averaging technique and a nested CMOS gain-boosting technique is described. The converter is optimized for low-voltage low-power applications by applying an optimum stage-scaling algorithm at the architectural level and an opamp and comparator sharing technique at the circuit level. Prototyped in a 0.18-/spl mu/m 6M-1P CMOS process, this converter achieves a peak signal-to-noise plus distortion ratio (SNDR) of 75.5 dB and a 103-dB spurious-free dynamic range (SFDR) without trimming, calibration, or dithering. With a 1-MHz analog input, the maximum differential nonlinearity is 0.47 LSB and the maximum integral nonlinearity is 0.54 LSB. The large analog bandwidth of the front-end sample-and-hold circuit is achieved using bootstrapped thin-oxide transistors as switches, resulting in an SFDR of 97 dB when a 40-MHz full-scale input is digitized. The ADC occupies an active area of 10 mm/sup 2/ and dissipates 98 mW.     

20 mW 1.25 Gbit/s CMOS transimpedance amplifier with 30 dB dynamic range

A 1.25 Gbit/s transimpedance amplifier using a novel photodiode capacitance cancellation technique has been demonstrated in 0.35 mum CMOS technology. The transimpedance amplifier achieved a transimpedance gain of 17.1 kOmega as well as a wide dynamic range from +1 to -29 dBm while consuming only 20 mW from a 3 V supply     

A 1.5-V direct digital synthesizer with tunable delta-sigma modulator in 0.13-/spl mu/m CMOS

In direct digital synthesizer (DDS) applications, the drawback of the conventional delta sigma (/spl Delta//spl Sigma/) modulator structure is that its signal band is fixed. In the new architecture presented in this paper, the signal band of the /spl Delta//spl Sigma/ modulator is tuned according to the DDS output frequency. We use a hardware-efficient phase-to-sine amplitude converter in the DDS that approximates the first quadrant of the sine function with 16 equal-length piecewise second-degree polynomial segments. The DDS is capable of frequency, phase, and quadrature amplitude modulation. The die area of the chip is 2.02 mm/sup 2/ (0.13 /spl mu/m CMOS technology). The total power consumption is 138 mW at 1.5 V with an output frequency of 63.33 MHz at a clock frequency of 200 MHz (D/A converter full-scale output current: 11.5 mA).     

A 2.5-V 12-b 54-Msample/s 0.25-μm CMOS ADC in 1-mm2with mixed-signal chopping and calibration

This paper describes a two-step analog-to-digital converter (ADC) with a mixed-signal chopping and calibration algorithm. The ADC consists primarily of analog blocks, which do not suffer from the matching limitations of active devices. The offset on two residue amplifiers limits the accuracy of the ADC. Background digital offset extraction and analog compensation is implemented to continuously remove the offset of these critical analog components. The calibrated two-step ADC achieves -70 dB THD in the Nyquist band, with a 2.5-V supply. The ADC is realized in standard single-poly 5-metal 0.25-μm CMOS, measures 1.0 mm² , and dissipates 295 mW     

A 2.5-V 57-MHz 15-tap SC bandpass interpolating filter with 320-MS/s output for DDFS system in 0.35-/spl mu/ hboxm CMOS

A switched-capacitor (SC) bandpass interpolating filter is proposed with the capability of achieving, simultaneously, channel selection and frequency up-translation, together with sampling rate increase, in a multirate configuration at high frequency. This filter has been designed for efficient use in a direct-digital frequency synthesis (DDFS) system with considerable rewards in terms of speed reduction of the digital core plus the digital-to-analog converter (DAC), as well as in the relaxation of the continuous-time (CT) smoothing filter order. It exhibits a 15-tap finite impulse response (FIR), with a bandpass frequency response centered at 57 MHz and a stop-band rejection higher than 45 dB. At the same time, it translates 22-24 MHz input signals at 80 MS/s, to the frequency range of 56-58 MHz in the output at 320 MS/s, allowing also a perfect operation at 400 MS/s, in 0.35-/spl mu/m CMOS technology. To implement a specific multi-notch FIR function, the filter architecture will comprise an effective low-speed polyphase-based interpolation structure with autozeroing capability, high-speed SC circuitry with fast opamps, and also ultra-low timing-skew multiple phase generation in order to achieve high-performance operation at high frequency. The prototype ICs present a signal-to-noise-and-distortion ratio (SNDR) of 61 dB, with a dynamic range of 69 dB, for 1% THD, and 61 dB, for 1% IM3. It consumes 2 mm/sup 2/ of active silicon area, 120 mW (analog) and 16 mW (digital) power, with a single 2.5-V supply, which corresponds to 8.6 mW of analog power per zero.     

A CMOS IC for Gb/s Viterbi decoding: system design and VLSIimplementation

At present, the Viterbi algorithm (VA) is widely used in communication systems for decoding and equalization. The achievable speed of conventional Viterbi decoders (VD's) is limited by the inherent nonlinear add-compare-select (ACS) recursion. The aim of this paper is to describe system design and VLSI implementation of a complex system of fabricated ASIC's for high speed Viterbi decoding using the “minimized method” (MM) parallelized VA. We particularly emphasize the interaction between system design, architecture and VLSI implementation as well as system partitioning issues and the resulting requirements for the system design flow. Our design objectives were 1) to achieve the same decoding performance as a conventional VD using the parallelized algorithm, 2) to achieve a speed of more than 1 Gb/s, and 3) to realize a system for this task using a single cascadable ASIC. With a minimum system configuration of four identical ASIC's produced by using 1.0 μ CMOS technology, the design objective of a decoding speed of 1.2 Gb/s is achieved. This means, compared to previous implementations of Viterbi decoders, the speed is increased by an order of magnitude