高温正向大电流下TiAl,TiptAu栅GaAsMESFET的栅退化机理 …

针对ＧａＡｓＭＥＳＦＥＴ在微波频率的应用中的射频过驱动导致高栅电流密度现象,设计了ＴｉＡｌ栅和ＴｉＰｔＡｕ栅ＧａＡｓ ＭＥＳＦＥＴ的高温正向大电流试验,通过对试验数据和试验样品的扫描电镜静态电压衬度像以及试验中的失效样品进行分析,确定了栅寄生并联电阻的经是导致器件的跨导ｇｍ、栅反向漏电流Ｉｓ、夹断电压Ｖｐ等特性退化,甚至导致器件烧毁失效的主要原因。     

GaAs双栅MESFET的PSPICE直流模型

提出了一种ＧａＡｓ双栅ＭＥＳＦＥＴ的ＰＳＰＩＣＥ直流模型．分析了ＧａＡｓ双栅ＭＥＳＦＥＴ漏极电流与两个控制栅偏置电压之间的关系,给出了漏极电流表达式．通过提取适当的模型参数,其直流输出特性的模拟曲线与实测曲线基本吻合,说明文中提出的ＧａＡｓ双栅ＭＥＳＦＥＴ的ＰＳＰＩＣＥ直流模型是有效的．     

半绝缘非掺GaAs材料制备的MESFETs背栅效应

设计了一套适用于二种工艺（离子注入隔离工艺和半绝缘衬底自隔离工艺）的背栅效应测试版图,用选择离子注入形成有源层和欧姆接触区,在非掺杂的半绝缘ＧａＡｓ衬底上制备ＧａＡｓＭＥＳＦＥＴｓ器件．研究了这二种不同工艺制备的ＭＥＳＦＥＴｓ器件的背栅效应以及不同距离背栅电极的背栅效应大小．结果表明,采用离子注入隔离工艺制备的ＭＥＳＦＥＴｓ器件的背栅效应要比采用半绝缘衬底自隔离工艺制备ＭＥＳＦＥＴｓ器件的背栅效应小,背栅效应的大小与距离近似成反比,采用隔离注入的背栅阈值电压随距离变化的趋势比采用衬底自隔离的更大．     

Al／n—GaAs肖特基接触正向脉冲退化对GaAsIC的影响

本文描述了Ａｌ／ｎ－ＧａＡｓ肖特基接触的正向脉冲退化效应，探讨了当肖特基二极管承受正向电流冲击时，势垒高度ΦＢ升高，直接影响Ａｌ栅ＭＥＳＦＥＴｓ的特性，导致Ａｌ／ｎ－ＧａＡｓ ＩＣ失效的机理。     

微波功率GaAs MESFET的可靠性

本文介绍了功率ＧａＡｓ ＭＥＳＦＥＴ的必要失效模式和失效机理，主要失效模式有突然烧毁致命失效，缓慢退化失效，击穿低漏电大失效，内外引线和热集中失效，器件性能的不稳定和可逆漂移，主要失效机理有结构设计不合理，材料和工艺缺陷，栅结，欧姆接触和材料退化。静电损伤等，提出了改进功率ＧａＡｓ ＭＥＳＦＥＴＳ可靠性的主要措施：全面质量管理，运用可靠性增长管理技术，合理的设计方案，先进的设备和工艺，优质的材料和     

GaAs MESFET栅极漏电流退化机理分析

高温存储试验后某种ＧａＡｓ　ＭＥＳＦＥＴ的栅－漏极正向和反向漏电流增大。为分析失效机理,测定了试验前后栅－漏极低压正向电流随温度的变化,定性估计了试验前后复合－产生中心浓度的变化,确定肖特基势垒接触有源层的复合－产生中心浓度增加是两种漏电流增大的原因,为高温下ＧａＡｓ　ＭＥＳＦＥＴ的肖特基势垒接触存在栅金属下沉和扩散提供了证据。     

背栅效应对GaAsMESFETV_(th)均匀性的影响

研究了背栅效应对全平面选择离子注入自隔离ＧａＡｓＭＥＳＦＥＴ的阈值电压及其均匀性的影响．结果表明,背栅效应使ＧａＡｓＭＥＳＦＥＴ的阈值电压绝对值变小,均匀性变差．     

砷化镓SJFET四端器件

本文提出一种由Ｍ－ＳＳｃｈｏｔｔｋｙ结和ｐｎ结组成的ＧａＡｓＳＪＰＥＴ四端器件，对该器件原理进行了分析与讨论，并在实验室研制出了ＧａＡｓＳＪＦＥＴ四端器件．实验结果表明，该器件可通过上、下两个栅分别调控，实现器件阈值电压连续可调．该器件极易获得稳定、重复的Ｅ－和Ｄ－ＭＥＳＦＥＴ，可望在ＧａＡｓ集成电路中得到应用．     

GaAs苛MESFET栅极漏电流退化机理分析

高温存储试验后某种ＧａＡｓ ＭＥＳＦＥＴ的栅－漏极正向和反向漏电流增大。为分析失效机理,测定了试验前后栅－漏极低电压正向电流随温度的变化,定性估计了试验前后复合－产生中心浓度的变化,确定肖待基势垒触有源层的复合－产生中心浓度的增加是两种漏电流增大的原因,为高温下ＧａＡｓ ＭＥＳＦＥＴ的肖特基势垒接触存在栅金属下沉和扩散提供了证据．     

GaAs器件及MMIC的可靠性研究进展

介绍了国外ＧａＡｓ微波器件及ＭＭＩＣ的可靠性研究进展情况，给出ＧａＡｓＭＥＳＦＥＴ、ＨＥＭＴ和ＭＭＩＣ的主要失效模式和失效机理以及在典型沟道温度下的平均寿命代表值。     

Analytical model of GaAs MESFET's

A simple analytical model of GaAs MESFET's is proposed. The model is based on the assumption that the current saturation in GaAs MESFET's is related to the stationary Gunn domain formation at the drain side of the gate rather than to a pinchoff of the conducting channel under the gate. The saturation current, channel conductance, transconductance, charge under the gate, gate-to-source and drain-togate capacitances, cutoff frequency, characteristic switching time, power-delay product, and breakdown voltage are calculated in the frame of this model. The results are verified by two-dimensional computer calculations. They agree well with the results of the computer analysis and experimental data for a 1-µm gate GaAs MESFET. It is shown that a stray gate-to-drain and gate-to-source capacitance sets up a limitation of a gate length which must be larger than or about 0.1 µm for a GaAs MESFET.     

Negative differential conductivity and isothermal drain breakdownof the GaAs MESFET

Electrical breakdown in GaAs MESFET's is simulated by two-dimensional (2-D) quasi hydrodynamic isothermal model with two types of carriers and “mixed” boundary conditions on the contacts-fixed drain current and fixed gate bias. It was demonstrated, that when some maximum drain voltage is reached the MESFET's differential conductivity becomes negative at every gate bias. The negative differential conductivity (NDC) is caused by the electric field reconstruction in the buffer by the injected carrier space charge. It is shown that the suggested breakdown model corresponds to the experimentally observed properties of the drain breakdown of the GaAs MESFET. The instantaneous burnout of the GaAs MESFET at the drain breakdown is explained by the uncontrollable drain current increase due to the NDC formation     

Co-integration of GaAs MESFET and Si CMOS circuits

Co-integration of GaAs MESFET and Si CMOS circuits is demonstrated using GaAs-on-Si epitaxial growth on prefabricated Si wafers. This is thought to be the first report of circuit-level integration of the two types of devices in a coplanar structure. A 2-μm gate Si CMOS ring oscillator has shown a minimum delay of 570 ps/gate, whereas on the same wafer a 1-μm gate GaAs MESFET buffered-FET-logic (BFL) ring oscillator has a minimum delay of only 70 ps/gate. A composite ring oscillator consisting of Si CMOS invertors and GaAs MESFET invertors connected in a ring has been successfully fabricated     

New method to measure the source and drain resistance of the GaAs MESFET

The method to measure the source resistance of the GaAs MESFET proposed here is able to determine its value directly without correcting for the channel resistance of the GaAs MESFET. A low gate current measurement condition is employed which leads to accurate determination of Rsand Rdover a relatively wide range of drain currents.     

TOM3 capacitance model: linking large- and small-signal MESFETmodels in SPICE

Improved accuracy in the modeled gate capacitance of GaAs metal-semiconductor field-effect transistors (MESFET's) is obtained in SPICE using conservation of charge in an implanted layer. The gate junction creates a natural partition between mobile and fixed channel charges. Relating the gate charge to the channel current creates gate capacitances dependent upon the channel current derivatives linking the small-signal model to the large-signal equations. Results are illustrated using a depletion-mode MESFET     

High-performance In0.08Ga0.92As MESFETs onGaAs(100) substrates

In_0.08Ga_0.92As MESFETs were grown in GaAs (100) substrates by molecular beam epitaxy (MBE). The structure comprised an undoped compositionally graded In_xGa_1-x As buffer layer, an In_0.08Ga_0.92As active layer, and an n⁺-In_0.08Ga_0.92As cap layer. FETs with 50-μm width and 0.4-μm gate length were fabricated using the standard processing technique. The best device showed a maximum current density of 700 mA/mm and a transconductance of 400 mS/mm. The transconductance is extremely high for the doping level used and is comparable to that of a 0.25-μm gate GaAs MESFET with an active layer doped to 10¹⁸ cm^-3. The current-gain cutoff frequency was 36 GHz and the power-gain cutoff frequency was 65 GHz. The current gain cutoff frequency is comparable to that of a 0.25-μm gate GaAs MESFET     

A low-gate-leakage-current GaAs MESFET with a thin epitaxialsilicon layer

An n-channel depletion-mode GaAs MESFET with an Al gate and a 6-A epitaxial Si layer between the metal and the GaAs, grown in situ by molecular beam epitaxy, is described. Its DC electrical characteristics are compared with a similar control structure grown without the Si layer. The gate leakage current in the Al/Si/GaAs MESFETs was three to four orders of magnitude lower than in the control structure, due to all increased barrier height in the Al/Si/n-GaAs Schottky gate of 1.04 eV, versus 0.78 eV for the Al/n-GaAs structure. The differences in threshold voltages, I-V characteristics, and transconductances between the two devices are consistent with an enhanced effective barrier height for the Al/Si/GaAs MESFET     

Inverted gate GaAs MESFET by epitaxial liftoff

A GaAs film deposited on metal by epitaxial liftoff can form a Schottky barrier. This film is used to make a 1 mu m gate length inverted gate GaAs metal-semiconductor field-effect transistor (MESFET) that can be pinched off by the inverted gate.<>     

High-density GaAs integrated circuit manufacturing

The essential items in the development of a high-density high-yield volume manufacturing process for GaAs integrated circuits are presented. The critical issues and decisions for creating the high-density GaAs (HGaAs) enhancement and depletion mode Schottky gate MESFET process are reviewed. The authors describe the process steps, fabrication equipment, and materials used to fabricate self-aligned, refractory gate, enhancement/depletion (E/D) MESFET multilevel metal GaAs integrated circuits. Representative device and circuit results are included.     

Reliability Study of GaAs MESFET's

Failure modes have been studied phenomenologically on a small-signal GaAs MESFET with a 1mu m aluminum gate. Three major failure modes have been revealed, i.e., gradual degradation due to source and drain contact degradation, catastrophic damage due to surge pulse, and instability or reversible drift of electrical characteristics during operation. To confirm the product quality and to assure the device reliability, a quality assurance program has been designed and incorporated in a production line. A cost-effective lifetime prediction method is presented that utilizes correlations between RF parameters and dc parameters calculated using an equivalent circuit model. Mean time to failure (MTTF) value of over 10/sup 8/ h has been obtained for the GaAs MESFET for an operating channel temperature of 100/spl deg/C.