A 130-nm 6-GHz 256 × 32 bit leakage-tolerant register file

Describes a 256-word × 32-bit 4-read, 4-write ported register file for 6-GHz operation in 1.2-V 130-nm technology. The local bitline uses a pseudostatic technique for aggressive bitline active leakage reduction/tolerance to enable 16 bitcells/bitline, low-V_t usage, and 50% keeper downsizing. Gate-source underdrive of -V _cc on read-select transistors is established without additional supply/bias voltages or gate-oxide overstress. 8% faster read performance and 36% higher dc noise robustness is achieved compared to dual-V_t bitline scheme optimized for high performance. Device-level measurements in the 130-nm technology show 703× bitline active leakage reduction, enabling continued V_t scaling and robust bitline scalability beyond 130-nm generation. Sustained performance and robustness benefit of the pseudostatic technique against conventional dynamic bitline with keeper-upsizing is also presented     

A 640-ps, 0.25-μm CMOS, 16×64-b three-port register file

We describe a 640-ps read access, 16-word by 64-b, three-port register file fabricated in 0.25-μm effective channel length CMOS technology. It features the capability to perform a write followed by a read in the same cycle at frequencies above 500 MHz. High speed is achieved by using a novel cell and array structure. Static circuit design is used exclusively throughout the entire register file and is optimized for high-speed operation. Measured results of the same-cycle read-after-write demonstrate register file operations at 625 MHz. Additionally internal probe measurements of the read access path components are presented and compared with circuit simulations     

A 1.3-ns 32-word×32-bit three-port BiCMOS register file

This paper describes a CMOS multiport static memory cell with which it is possible to use current-switching bipolar peripheral circuits to maintain small voltage swings throughout the read access path while retaining the high density of CMOS memory arrays. An experimental 32-word×32 bit three-port register file has been designed and implemented using this cell. The register file was fabricated in a 0.6-μm BiCMOS technology and operates from a single -3.3-V power supply with ECL-compatible I/O circuits. Under nominal operating conditions at 20°C, the measured pin-to-pin access time is 1.3 ns. The minimum write enable pulse width required is less than 1 ns, and the power dissipation, excluding the output buffers, is 650 mW at a clock rate of 100 MHz     

A 15-ns 32×32-b CMOS multiplier with an improved parallelstructure

A high-speed 32×32-b parallel multiplier with an improved parallel structure using 0.8-μm CMOS triple-level-metal technology is discussed. A unit adder, a 4-2 compressor, enhances the parallelism of the multiplier array. A 25% reduction in the propagation delay time is achieved by using the compressor. The multiplier contains 27704 transistors with a 2.68-×2.71-mm² die area. The multiplication time is 15 ns at 5 V with a power dissipation of 277 mW at 10-MHz operation. The triple-level-metal interconnection technology reduces the multiplier layout area. Compared with double-level-metal technology, a 27% chip size reduction is achieved     

A 32-bit NMOS microprocessor with a large register file

Two scaled versions of a 32-bit NMOS reduced-instruction-set computer CPU, called RISC II, have been implemented on two different processing lines using the simple layout rules of C.A. Mead and L.A. Conway (1980). The lambda values are 2 and 1.5 /spl mu/m, corresponding to drawn gate lengths of 4 and 3 /spl mu/m, respectively. The design utilizes a small set of simple instructions in conjunction with a large register file in order to provide high performance. This approach has resulted in two surprisingly powerful single-chip processors.     

Four-phase power clock generator for adiabatic logic circuits

A circuit for a four-phase trapezoidal power clock generator for adiabatic logic circuits realised with a double-well 0.25 μm CMOS technology and external inductors is proposed. The circuit, at a frequency of 7 MHz which is within the optimum frequency range for adiabatic circuits realised with 0.25 μm CMOS technology, has a conversion efficiency higher than 80%, and is robust with respect to parameter variations     

A 14-port 3.8-ns 116-word 64-b read-renaming register file

A 116-word by 64-b register file for a 154 MHz four-issue superscalar processor renames read addresses and reads data in a single operation. A 10-port, 116-word tag comparison unit and a rename logic unit use static-bit-line techniques in the comparison logic. Pulsed-power sense amplifiers achieve a 3.8-ns read delay while dissipating 31% less power than a nonpulsed circuit     

A 32-word by 32-bit three-port bipolar register file implementedusing a SiGe HBT BiCMOS technology

Describes a novel system level design for a 32-word by 32-bit bipolar register file with two read ports and one write port. The register file is implemented using a SiGe HBT BiCMOS technology and emitter-coupled logic (ECL)-style circuits. It has dimensions of 1.0 mm by 1.8 mm. The read access time for the register Me is between 340 and 350 ps using read port A, while the read access time using read port B is between 360 and 380 ps. Read access times as low as 290 ps were measured for some columns, however. The write access time for the register file is between 250 and 340 ps, using a write enable pulse with a width between 130 and 170 ps. The estimated register file power dissipation is 4.7 W using a 4.5-V supply     

0.5-μm 3.3-V BiCMOS standard cells with 32-kilobyte cache andten-port register file

BiCMOS standard cell macros, including a 0.5-W 3-ns register file, a 0.6-W 5-ns 32-kbyte cache, a 0.2-W 3-ns table look-aside buffer (TLB), and a 0.1-W 3-ns adder, are designed with a 0.5-μm BiCMOS technology. A supply voltage of 3.3 V is used to achieve low power consumption. Several BiCMOS/CMOS circuits, such as a self-aligned threshold inverter (SATI) sense amplifier and an ECL HIT logic are used to realize high-speed operation at the low supply voltage. The performance of the BiCMOS macros is verified using a fabricated test chip     

A wide supply voltage range and low-power all-digital clock generator

This study presents a low-power all-digital clock generator (ADCG) for a wide supply voltage range system. The proposed ADCG limits the maximum supply current to 100 μA at a supply voltage ranging from 1.6 to 3.6 V. The ADCG also uses a digitally controlled oscillator (DCO) to extend its operational frequency range. The proposed DCO controls the supply current and divider circuits for a wide supply voltage range. The output duty cycle of ADCG falls within 50 ± 1.9 % using a duty cycle corrector. The maximum peak-to-peak jitter is less than 2.7 % at 8.38 MHz for a digital water meter application (DWM). The operational frequencies of 1.45 and 8.38 MHz at 1.8 V are 3.1 and 36.7 μA, respectively. The core area of ADCG is 0.14 mm² for a 0.35 μm CMOS process. The operational frequency of ADCG ranges from 4.5 to 9.2 MHz at a supply voltage ranging from 1.6 to 3.6 V. This clock generator can also be applied to microcontroller applications.     

A 32×32-bit multiplier using multiple-valued MOS current-modecircuits

A 32×32-bit multiplier using multiple-valued current-mode circuits has been fabricated in 2-μm CMOS technology. For the multiplier based on the radix-4 signed-digit number system, 32×32-bit two's complement multiplication can be performed with only three-stage signed-digit full adders using a binary-tree addition scheme. The chip contains about 23600 transistors and the effective multiplier size is about 3.2×5.2 mm², which is half that of the corresponding binary CMOS multiplier. The multiply time is less than 59 ns. The performance is considered comparable to that of the fastest binary multiplier reported     

Prototype 32×32 optical switch matrix

A 32×32 optical switch matrix with a banyan network architecture is demonstrated using a Ti:LiNbO₃ waveguide. The switching voltage was 24 V and extinction ratio averaged -18 dB. The prototype device showed path dependent insertion loss deviation of 10 dB. The device can be used as a building block for many functional optical switch matrices     

A 54×54-b regularly structured tree multiplier

A 54-b×54-b parallel multiplier was implemented in 0.88-μm CMOS using the new, regularly structured tree (RST) design approach. The circuit is basically a Wallace tree, but the tree and the set of partial-product-bit generators are combined into a recurring block which generates seven partial-product bits and compresses them to a pair of bits for the sum and carry signals. This block is used repeatedly to construct an RST block in which even wiring among blocks included in wire shifters is designed as recurring units. By using recurring wire shifters, the authors can expand the level of repeated blocks to cover the entire adder tree, which simplifies the complicated Wallace tree wiring scheme. In addition, to design time savings, layout density is increased by 70% to 6400 transistors/mm², and the multiplication time is decreased by 30% to 13 ns     

A spread-spectrum clock generator with triangular modulation

In this paper, a spread-spectrum clock generator (SSCG) with triangular modulation is presented. Only a divider and a programmable charge pump are added into a conventional clock generator to accomplish the spread-spectrum function. The proposed circuit has been fabricated in a 0.35-/spl mu/m CMOS single-poly quadruple-metal process. The proposed SSCG can generate clocks of 66, 133, and 266 MHz with center spread ratios of 0.5%, 1%, 1.5%, 2%, and 2.5%. Experimental results confirm the theoretical analyses.     

A novel spread-spectrum clock generator for suppressing conducted EMI in switching power supply

In this paper, a novel spread spectrum clock generator (SSCG) which spreads spectrum with variable current is presented. The proposed SSCG circuit not only occupies a small area but also minimizes effect caused by leakage current. The proposed SSCG circuit has been fabricated in a 0.5 μm BCD process and applied to a fly-back converter. The effectiveness of the proposed SSCG circuit in terms of peak EMI reduction is demonstrated theoretically and confirmed with experimental results.     

A low-power 16×16-b parallel multiplier utilizingpass-transistor logic

This paper describes a low-power 16×16-b parallel very large scale integration multiplier, designed and fabricated using a 0.8 μm double-metal double-poly BiCMOS process. In order to achieve low-power operation, the multiplier was designed utilizing mainly pass-transistor (PT) logic circuits. The inherent nonfull-swing nature of PT logic circuits were taken full advantage of, without significantly compromising the speed performance of the overall circuit implementation. New circuit implementations for the partial product generator and the partial-product addition circuitry have been proposed, simulated, and fabricated. Experimental results showed that the worst case multiplication time of the test chip is 10.4 ns at a supply voltage of 3.3 V, and the average power dissipation is 38 mW at a frequency of 10 MHz     

A 4.4 ns CMOS 54×54-b multiplier using pass-transistormultiplexer

A 54×54-b multiplier using pass-transistor multiplexers has been fabricated by 0.25 μm CMOS technology. To enhance the speed performance, a new 4-2 compressor and a carry lookahead adder (CLA), both featuring pass-transistor multiplexers, have been developed. The new circuits have a speed advantage over conventional CMOS circuits because the number of critical-path gate stages is minimized due to the high logic functionality of pass-transistor multiplexers. The active size of the 54×54-b multiplier is 3.77×3.41 mm. The multiplication time is 4.4 ns at a 3.5-V power supply     

A 6.5-ns GaAs 20×20-b parallel multiplier with 67-ps gatedelay

The performance and yield of LSI circuits have been characterized over a wide variation in processing parameters and power supply voltage, and over the military temperature range using 4×4-, 8×8-, 12×12-, 16×16-, and 20×20-b multipliers. These parallel array multipliers with carry-save adder architecture have been implemented in low-power GaAs enhancement/depletion (E/D) direct-coupled FET logic (DCFL). The circuits were fabricated with a multifunction self-aligned gate process, which features a buried p-layer for high yield and manufacturability. Worst-case multiplication times ranging from 870 ps (51 ps/gate) for the 4×4-b, to 6.48 ns (67 ps/ gate) for the 20×20-b multiplier were obtained, with the fastest extracted gate delays yet reported for LSI circuits. The 20×20-b multiplier, with 18573 active devices (4902 logic gates), shows a wafer-probe yield as high as 61% on the best-yielding wafers. It is concluded that the E/D DCFL family is capable of providing LSI circuits operating over a wide variation in power-supply voltage and over the full military temperature range     

A new register file structure for the high-speed microprocessor

The pipeline operations of the register file in a microprocessor are analyzed in detail. Conventional register files, two-port static RAMs, have two problems in successive write-to-read operations. (1) A read-time error takes place when the transition of the W/R mode and the transition of register address occur simultaneously. (2) A write-time error takes place when the supply voltage is slow. A new register file structure is proposed, which has three address word lines and four data bit lines for each memory cell. This structure enables the independent write and read operations to each other, and can solve the two problems. By using this register file structure, a new 16 bit microprocessor with 250 ns machine cycle time is successfully developed. Several other features of this processor are also explained and discussed.     

一种占空比可调的两相非重叠时钟发生器

本文通过调谐压控振荡器输出信号的占空比,直接产生了两相非重叠时钟信号。这一设计集振荡信号发生与非重叠时钟产生于一身,突破了传统标准电路的设计思路。本项工作获得了20%~80%的信号占空比可调范围,同时还实现了两相信号之间不重叠时间间隔的可调谐。利用SMIC 0.18μm 1P6M CMOS工艺,所需电源电压为1.8V,整个电路仅需30个晶体管。