A Low Power 16‐Bit RISC Microprocessor Using ECRL Circuits

This paper presents a low power 16‐bit adiabatic reduced instruction set computer (RISC) microprocessor with efficient charge recovery logic (ECRL) registers. The processor consists of registers, a control block, a register file, a program counter, and an arithmetic and logical unit (ALU). Adiabatic circuits based on ECRL are designed using a 0.35 µm CMOS technology. An adiabatic latch based on ECRL is proposed for signal interfaces for the first time, and an efficient four‐phase supply clock generator is designed to provide power for the adiabatic processor. A static CMOS processor with the same architecture is designed to compare the energy consumption of adiabatic and non‐adiabatic microprocessors. Simulation results show that the power consumption of the adiabatic microprocessor is about 1/3 compared to that of the static CMOS microprocessor.     

A 32-word by 32-bit three-port bipolar register file implementedusing a SiGe HBT BiCMOS technology

Describes a novel system level design for a 32-word by 32-bit bipolar register file with two read ports and one write port. The register file is implemented using a SiGe HBT BiCMOS technology and emitter-coupled logic (ECL)-style circuits. It has dimensions of 1.0 mm by 1.8 mm. The read access time for the register Me is between 340 and 350 ps using read port A, while the read access time using read port B is between 360 and 380 ps. Read access times as low as 290 ps were measured for some columns, however. The write access time for the register file is between 250 and 340 ps, using a write enable pulse with a width between 130 and 170 ps. The estimated register file power dissipation is 4.7 W using a 4.5-V supply     

A 500-MHz, 32-word×64-bit, eight-port self-resetting CMOSregister file

A two-write-port, six-read-port, 32×64-bit register file has been designed for 2.5-V 0.5-μm CMOS technology, using primary self-resetting CMOS (SRCMOS) circuit techniques. The register cell are completely level-sensitive scan design test compatible. The fabricated register file occupies an area of 1.84×1.55 mm², and the cell size is 21.6×30 μm². The high-performance register file is implemented in a multiblock structure consisting of subarrays and associated multiplexing circuits. For a given read port, the outputs of all multiplexer circuits are dotted together to form a single global output. A quasi-global approach is used for reset pulse generation and timing control circuits to reduce area overhead. The output pulse width is controlled by a chopper circuit. The write-port operation is achieved by the combination of static data input and dynamic control circuits. The write-path circuits employ the advantages of the input isolation technique. Individual write-enable pulses applied to respective input ports of a multiport register-file cell are effective to establish a priority among those input ports. The present design provides an effective input isolation/decoupling circuit technique that allows the input pulse widths to vary over a wide range. This allows the write operation to be insensitive to control pulse widths, resulting in an effective input isolation scheme. Testing has shown all eight ports to be functional. The measured read access time was 1.1 ns, and read operation has been obtained at cycle times as short as 1.9 ns. The register file has been shown to be tolerant to a very wide range of input pulse widths yet delivers tightly controlled outputs     

基于耦合边界的紧凑型光子晶体定向耦合器的优化设计

本文采用平面波展开法分析了双线型缺陷并列平行光子晶体波导的带隙结构、缺陷模式及耦合长度,提出了一种具有耦合边界的光子晶体定向耦合器,并探讨了光波在其中的传输性能.同时基于平面波展开法及时域有限差分法,深入分析和讨论了光波在光子晶体并列波导、光子晶体直角转弯模块中的工作模式和传输特性.利用该光子晶体定向耦合器结合光子晶体转角器件可以将两根平行标准单模光纤传输模式组合成交叉态、直通态和功分态等状态.仿真结果表明在交叉态和直通态时,使用该光子晶体定向耦合器的传输峰值可以在较大频率带宽内达到90%以上.     

采用三相交流电源的低功耗绝热时序电路

研究采用三相交流电源的绝热时序电路.首先介绍了采用三相交流电源的双传输门绝热电路并分析其工作原理，在此基础上提出了性能良好的低功耗绝热D、T与JK触发器.使用绝热触发器设计时序系统的实例被演示.SPICE程序模拟表明，设计的电路具有正确的逻辑功能及低功耗的优点。     

An efficient charge recovery logic circuit

Efficient charge recovery logic (ECRL) is proposed as a candidate for low-energy adiabatic logic circuit. Power comparison with other logic circuits is performed on an inverter chain and a carry lookahead adder (CLA). ECRL CLA is designed as a pipelined structure for obtaining the same throughput as a conventional static CMOS CLA. Proposed logic shows four to six times power reduction with a practical loading and operation frequency range. An inductor-based supply clock generation circuit is proposed. Circuits are designed using 1.0-μm CMOS technology with a reduced threshold voltage of 0.2 V     

低功耗、高性能多米诺电路电荷自补偿技术

提出了一种电荷自补偿技术来降低多米诺电路的功耗,并提高了电路的性能.采用电荷自补偿技术设计了具有不同下拉网络(PDN)和上拉网络(PUN)的多米诺电路,并分别基于65,45和32nm BSIM4 SPICE模型进行了HSPICE仿真.仿真结果表明,电荷自补偿技术在降低电路功耗的同时,提高了电路的性能.与常规多米诺电路技术相比,采用电路自补偿技术的电路的功耗延迟积(PDP)的改进率可达42.37%.此外,以45nm Zipper CMOS全加器为例重点介绍了功耗分布法,从而优化了自补偿路径,达到了功耗最小化的目的.最后,系统分析了补偿通路中晶体管宽长比,电路输入矢量等多方面因素对补偿通路的影响.     

STM32F101VB微处理器在气相色谱仪中的应用

由于传统的气相色谱仪外围接口电路存在不通用缺陷,且控制核心单片机无法满足现代气相色谱仪对多维图谱大量数据处理的要求。针对上述问题,研究了一种基于STM32F101VB微处理器的气相色谱仪控制电路。该微处理器使用高性能的ARM Cortex-M3 32位的RISC内核,具有增强I/O端口和APB总线的功能,适用于气相色谱仪的新型控制核心。该设计满足了现代气相色谱仪对通用接口和多维大量数据处理的要求。     

A Novel Charge Recycling Design Scheme Based on Adiabatic Charge Pump

Power consumption has become a critical design criterion for integrated circuits given the growing importance of portable battery-operated devices. A typical CMOS gate driven by power supply (V_DD), draws energy equal to C_LV_DD ² during every cycle of operation. We propose a new approach to recycle the charge with an adiabatic charge pump that moves the slower adiabatic components away from the critical path of logic. The critical path of the system, and hence the delay, do not change. This is achieved by overlapping the adiabatic charge pump delays with the computing path logic delays. Many embedded high performance applications such as digital signal processing (DSP), which exhibit datapath parallelism, are ideal candidates for this scheme. The proposed method has been implemented in DSP computations. SPICE simulations-based results indicate that the proposed scheme reduces energy consumption in these DSP circuits by as much as 18% (on average 9.94%) with no perceptible loss in performance. The area penalty for these energy savings are in the 1%-2% range, The leakage energy reduction in 45-nm BPTM averages 46%.     

A 1.3-ns 32-word×32-bit three-port BiCMOS register file

This paper describes a CMOS multiport static memory cell with which it is possible to use current-switching bipolar peripheral circuits to maintain small voltage swings throughout the read access path while retaining the high density of CMOS memory arrays. An experimental 32-word×32 bit three-port register file has been designed and implemented using this cell. The register file was fabricated in a 0.6-μm BiCMOS technology and operates from a single -3.3-V power supply with ECL-compatible I/O circuits. Under nominal operating conditions at 20°C, the measured pin-to-pin access time is 1.3 ns. The minimum write enable pulse width required is less than 1 ns, and the power dissipation, excluding the output buffers, is 650 mW at a clock rate of 100 MHz     

Design of ternary adiabatic multiplier on switch-level

The design of ternary adiabatic multiplier adopting switch-level design techniques is proposed in this paper. First by using the theory of three essential circuit elements, the switch-level functional expressions of the carry and product circuit models, which compose one bit ternary adiabatic multiplier, are derived. Consequently, the corresponding circuit structures can be obtained, and the evaluation and energy recovery for ternary circuit can be realized by bootstrapped NMOS transistors and cross-memory structure. Based on the designed circuits, the four bits ternary adiabatic multiplier is further realized by adopting the ripple carry manner. The PSPICE simulation results indicate that the designed circuits have correct logic function and are characterized with distinctive low power consumption.     

绝热无比型动态触发器和同步时序电路综合

该文从电路三要素理论出发研究低功耗电路，定量描述绝热无比型动态记忆电路。绝热无比型动态触发器利用电容接收和保存信息，避免目前绝热电路中电容上的信息得而复失的现象，其中绝热D和T'触发器只用6管，带‘与或非’输入的绝热D触发器只用9管。在上述理论基础上该文提出绝热无比型动态同步时序电路综合方法，用此法设计出绝热5421BCD码十进制计数器，仅用32管，总功耗小于一个PAL－2N四位二进制计数器的功耗，计算机模拟验证该文方法正确。     

QSERL: quasi-static energy recovery logic

A new quasi-static energy recovery logic family (QSERL) using the principle of adiabatic switching is proposed in this paper. Most of the previously proposed adiabatic logic styles are dynamic and require complex clocking schemes. The proposed QSERL uses two complementary sinusoidal supply clocks and resembles the behavior of static CMOS. Thus, switching activity is significantly lower than dynamic logic. In addition, QSERL circuits can be directly derived from static CMOS circuits. A high-efficiency clock generation circuitry, which generates two complementary sinusoidal clocks compatible to QSERL, is also presented in this paper. The adiabatic clock circuitry locks the frequency of clock signals, which makes it possible to integrate adiabatic modules into a VLSI system. We have designed an 8×8 carry-save multiplier using QSERL logic and two phase sinusoidal clocks. SPICE simulation shows that the QSERL multiplier can save 34% of energy over static CMOS multiplier at 100 MHz     

一种双极型基本电流镜的改进电路

在低电压、低功耗电流模式信号处理电路设计中，电流镜是必不可少的器件。他不仅实现电流信号的复制或倍乘/倍减，极性互补的电流镜还可以实现差动--单端电流信号的交换，还可提供高输出阻抗以便产生稳定的电流。在本文双极型电流镜的改进电路中，通过利用复合管的放大作用，实现了跟随误差的减小。     

低功耗绝热SRAM

文章提出了一种新的绝热电路,并以该绝热电路为驱动,设计了一种低功耗绝热SRAM.由于所提出的绝热电路能以完全绝热的方式回收位线和字线上大开关电容的电荷,因此使该SRAM的功耗大大减小.我们采用0.25μm TSMC工艺,在时钟频率25～200MHz范围内对绝热SRAM进行了能耗和功能的HSPICE仿真,结果显示,与用传统的CMOS电路设计的SRAM相比,可节能80%左右.     

Improved structure for adiabatic CMOS circuits design

Two adiabatic circuits with complementary structure and operation are proposed in this paper. They employ two-phase sinusoidal power clock. The power consumption of the proposed circuits is comparable to that of some previously reported circuits. The problem of floating output nodes is solved by connecting two MOS transistors to the power clock. In particular, using the proposed architecture more than one stage of gates can be computed simultaneously within a single clock-phase, compared to only one stage is computed in every phase by most other adiabatic logic families. With this feature, the latency of the complex logic circuit is greatly improved and the number of buffers required for a pipelining circuit is also reduced. In this paper, a 2:1 multiplexer and full adder are illustrated and simulated. From the PSPICE simulation results, the effectiveness of the proposed approach and the low power characteristic of the designed circuits are validated.     

Miniaturized Gysel power divider with nth harmonics suppression

In this paper, a miniaturized Gysel power divider with n^th harmonic suppression has been presented. The Gysel power divider retains its capability of high-power handling, while extreme size reduction makes it suitable for application in small-sized circuits with higher order harmonics rejection. A lowpass filter with high performance and appropriate characteristic has been placed instead of the conventional transmission lines a quarter wavelength. It results in the size reduction and harmonics rejection of the Gysel power divider, effectively. The presented Gysel power divider operated at center frequency of 0.764 GHz with fractional bandwidth of 36%. To substantiate the validity and efficiency of the proposed circuits, the designed power divider was fabricated and measured. It is seen that the results of the measurements and simulations are highly consistent together. The main frequency; the return loss of the port 1, the return loss of the port 2, isolation, and insertion loss are 28, 29, 32 and 1.3 dB, respectively. The overall circuit size is 22.1 mm × 65.7 mm.     

0.5-μm 3.3-V BiCMOS standard cells with 32-kilobyte cache andten-port register file

BiCMOS standard cell macros, including a 0.5-W 3-ns register file, a 0.6-W 5-ns 32-kbyte cache, a 0.2-W 3-ns table look-aside buffer (TLB), and a 0.1-W 3-ns adder, are designed with a 0.5-μm BiCMOS technology. A supply voltage of 3.3 V is used to achieve low power consumption. Several BiCMOS/CMOS circuits, such as a self-aligned threshold inverter (SATI) sense amplifier and an ECL HIT logic are used to realize high-speed operation at the low supply voltage. The performance of the BiCMOS macros is verified using a fabricated test chip     

A 32×32-bit multiplier using multiple-valued MOS current-modecircuits

A 32×32-bit multiplier using multiple-valued current-mode circuits has been fabricated in 2-μm CMOS technology. For the multiplier based on the radix-4 signed-digit number system, 32×32-bit two's complement multiplication can be performed with only three-stage signed-digit full adders using a binary-tree addition scheme. The chip contains about 23600 transistors and the effective multiplier size is about 3.2×5.2 mm², which is half that of the corresponding binary CMOS multiplier. The multiply time is less than 59 ns. The performance is considered comparable to that of the fastest binary multiplier reported     

基于微带双脊间隙波导技术的Ka波段六端口网络电路

面向毫米波高精度雷达探测应用,文中提出了一种基于微带双脊间隙波导技术的六端口网络电路。设计了基 于微带双脊间隙波导的功分器和耦合器电路,提出了微带双脊间隙波导至微带线的新型过渡转换结构,并基于简化的六 端口网络原理框图,将所设计的功分器、耦合器以及过渡转换结构进行有机组合,实现了所设计的Ka 波段六端口网络电 路。实验测试结果表明:在所设计的37.5 GHz~ 42.5 GHz 频率范围内,输入端口1 与四个输出端口间的相位差均 在±2.5°以内,输入端口2与四个输出端口间的相位差均在±5°内,工作中心频率处的输入输出间插入损耗约为7.3 dB。 实验与仿真结果吻合较好。