低功耗非全摆幅互补传输管加法器

文章提出了一种新型传输管全加器,该全加器采用互补传输管逻辑（Complementary Pass-Transistor Logic）实现.与现有的CPL全加器相比：该全加器具有面积、进位速度和功耗上的优势：并且提供了进位传播信号的输出,可以更简单的构成旁路进位加法器（Carry SkipAdder）.在此全加器基础上可以实现一种新型行波进位加法器（Ripple Carry Adder）,其内部进位信号处于非全摆幅状态,具有高速低功耗的特点.HSPICE模拟表明：对4位加法器而言,其速度接近CMOS提前进位加法器（Carry Look ahead Adder）,而功耗减小了61%.适用于高性能、低功耗的VLSI电路设计.     

采用对称结构MRF逻辑的亚微瓦级超低功耗加法器设计

文中提出了一种具有高抗干扰能力的对称结构改进型MRF逻辑,并由此采用混合设计策略实现了一个8位超前进位加法器．该加法器在SynopsysHSPICE模拟仿真平台上使用台积电的65nm低K电介质工艺器件模型进行了验证．电路仿真结果表明,在0．25V的工作电压下,该加法器的功耗达到了亚微瓦级．与先前的对应设计相比,晶体管数量减小44．3％,功耗降低了34．9％～38．8％．     

64位超前进位对数加法器的设计与优化

设计一个应用于高性能微处理器的快速64位超前进位对数加法器.通过分析超前进位对数加法器原理,提出了改进四进制Kogge-Stone树算法的64位超前进位对数加法器结构,并结合使用多米诺动态逻辑、时钟延迟多米诺逻辑和传输门逻辑等技术来设计和优化电路.该加法器采用SMIC 0.18 μm CMOS工艺实现,在最坏情况下完成一次加法运算时间为486.1 ps,与相同工艺和相同电路结构采用静态CMOS实现相比,大大减少了加法器各级门的延迟时间,取得良好的电路性能.     

基于Sklansky结构的24位并行前缀加法器的设计与实现

针对串行进位加法器存在的延时问题,采用一种基于Sklansky结构的并行前缀加法器,通过对并行前缀加法器各个模块进行优化,设计实现了一个24位并行前缀加法器。通过与24位串行进位加法器进行延时比较,结果表明,Sklansky并行前缀结构的加法器,能有效提高运算速度。     

基于逻辑结构的超前进位加法器的设计

通过对计算机加法器的研究,从门电路标准延迟模型出发,在对超前进位加法器逻辑公式研究的基础上,在主要考虑速度的前提下,给出了超前进位加法器的逻辑电路的设计方案。主要对16位、32位加法器的逻辑电路进行分析设计,通过计算加法器的延迟时间来对比超前进位加法器与传统串行进位链加法器,得出超前进位算法在实际电路中使加法器的运算速度达到最优。     

基于模块化结构的N位加法器的测试生成

针对单个ｓｔｕｃｋ－ａｔ故障，研究了Ｎ位加法器的测试矢量生成问题，对于行波进位加法器，只需８个测试矢量就可得到１００％的故障覆盖率；对于Ｎ位先行进位加法器，只需Ｎ＾２＋２Ｎ＋３个测试矢量即可得到１００％的故障覆盖率。     

一种自定时的前置进位加法器设计

从时序控制的角度出发,研究提高加法器性能的方法。在研究前置进位加法器的算法和结构后,又对多米诺电路的时钟控制技术进行深入分析。结合前置进位结构和自定时时钟控制．设计了一个32b多米诺加法器。该加法器能有效地提高时钟使用率。在TSMC0．18um工艺下,加法器的最大延时为970ps,约为相同工艺下13倍FO4的延时。     

用于加法器的功耗延迟积优化混合进位算法

为了实现高性能的加法器,提出了面向功耗延迟积(PDP)优化的混合进位算法。该算法能快速搜索加法器的混合进位,以优化PDP。采用超前进位算法和行波进位算法交替混合,兼具超前进位算法速度快和行波进位算法功耗低的特点。该算法采用C语言实现并编译,结果应用于MCNC Benchmark电路,进行判定测试。与应用三种传统算法的加法器相比,应用该算法的加法器在位数为8位、16位、32位和64位时,PDP改进量分别为40.0%、70.6%、85.6%和92.9%。     

对数跳跃加法器的算法及结构设计

本文介绍一种新型加法器结构——对数跳跃加法器,该结构结合进位跳跃加法器和树形超前进位加法器算法,将跳跃进位分组内的进位链改成二叉树形超前进位结构,组内的路径延迟同操作数长度呈对数关系,因而结合了传统进位跳跃结构面积小、功耗低的特点和ELM树形CLA在速度方面的优势.在结构设计中应用Ling's算法设计进位结合结构,在不增加关键路径延迟的前提下,将初始进位嵌入到进位链.32位对数跳跃加法器的最大扇出为5,关键路径为8级逻辑门延迟,结构规整,易于集成.spectre电路仿真结果表明,在0.25μmCMOS工艺下,32位加法器的关键路径延迟为760ps,100MHz工作频率下功耗为5.2mW.     

基于计数器实现的加法器自测试

文章研究了行波进位加法器和先行进位加法器的测试向量生成，并基于计数器实现了这两种加法器的自测试。实验结果表明，所得的测试向量针对不同的目标工艺均可以实现被测加法器的100％故障覆盖率，且测试向量生成电路易扩展，能够实现测试复用。     

Self-Checking Carry-Select Adder Design Based on Two-Rail Encoding

Carry-select adders are one of the faster types of adders. This paper proposes a scheme that encodes the sum bits using two-rail codes; the encoded sum bits are then checked by self-checking checkers. The multiplexers used in the adder are also totally self-checking. The scheme is illustrated with the implementation of a 2-bit carry select adder that can detect all single stuck-at faults on-line; the detection of double faults is not guaranteed. Adders of arbitrary size can be constructed by cascading the appropriate number of such 2-bit adders. A range of adders from 4 to 128 bits is designed using this approach employing a 0.5-mum CMOS technology. The transistor overhead in implementing these self-checking adders varies from 19.51% to 20.94%, and the area overhead varies from 16.07% to 20.67% compared to adders without built-in self-checking capability.     

High Speed Error Tolerant Adder for Multimedia Applications

In this paper, a 1-bit modified full adder (MFA) cell is proposed. This eliminates the carry propagation during the addition by allowing errors in the carry bit. Using the proposed MFA, a 16-bit high speed error tolerant adder (HSETA) circuit is designed with conventional carry select adder (CSLA) structure for higher order bits and MFA based structure for lower order bits. The performance of HSETA is compared with existing adders in terms of accuracy, gate count, delay and power dissipation. The gate count of the HSETA is reduced by 23% and speed is improved by 43% compared to a conventional 16-bit adder structure. Further, implementation on FPGA Spartan 6 shows that HSETA uses 53% fewer LUT and 63% fewer slices compared to the conventional adder. Image blending application is used to evaluate the performance of the HSETA. In addition, to perform extensive error analysis, an analytical model is developed for HSETA and tested for varying bit widths and input probabilities. The analytical model is validated through simulation.     

Evaluation of three 32-bit CMOS adders in DCVS logic for self-timedcircuits

The efficient implementation of adders in differential logic can be carried out using a new generate signal (N) presented in this paper. This signal enables iterative shared transistor structures to be built with a better speed/area performance than a conventional implementation. It also allows adders developed in domino logic to be easily adapted to differential logic. Based on this signal, three 32-b adders in differential cascode switch voltage (DCVS) logic with completion circuit for applications in self-timed circuits have been fabricated in a standard 1.0-μm two-level metal CMOS technology. The adders are: a ripple-carry (RC) adder, a carry look-ahead (CLA) adder, and a binary carry look-ahead (BCL) adder. The RC adder has the best levels of performance for random input data, but its delay is significantly influenced by the length of the carry propagation path, and thus is not recommended in circuits with nonrandom input operands. The BCL adder is the fastest but has a high cost in chip area. The CLA adder provides an intermediate option, with an area which is 20% greater than that of the RC adder. Its average delay is slightly greater than that of the other two adders, with an addition time which increases slowly with the carry propagate length even for adders with a high number of bits     

Multilevel Reverse-Carry Addition: Single and Dual Adders

The multilevel reverse-carry approach has been proposed previously for fast computation of the most-significant carry of an adder. In this paper, this approach is extended to generate several carries and is applied to the implementation of single and dual adders. Specifically, the operands are split into blocks and each block is added to produce the sum and the sum plus one. Concurrently with these additions the multilevel reverse-carry approach is used to generate the input carries of these blocks. Finally, these carries are used to select among the sum and the sum plus one.The delay and complexity of the resulting architecture for a 64-bit adder has been estimated, considering the load introduced by long connections, resulting in a reduction of about 15% in the critical path delay and comparable complexity with respect to traditional implementations of prefix-tree based adders.     

Reconfigurable Carry Look-Ahead Adder Trading Accuracy for Energy Efficiency

The modern portable devices exhibiting multimedia applications demand higher energy efficient signal processing due to limited battery size. The approximate adders have shown a remarkable energy-efficiency over the accurate adders for error tolerant applications. In this paper, three novel approximate carry look-ahead adder (ACLA) architectures are proposed. These approximate ACLAs are achieved by simplifying the Boolean expression of carry generation logic such that the probability of error is small while eliminating number of logic gates. Further, a novel accuracy reconfigurable CLA (Re-CLA) that provides desired quality/accuracy in the given energy budget is proposed. The post layout synthesis results using Synopsys IC Compiler of the proposed adders are computed and analysed against the existing adders. These results demonstrate 37.67%, 18.21%, 18.14% and 15.92% reduction in energy consumption by the proposed 8-bit ACLA-I, -II, -III and -IV adders respectively over the existing approximate adder. Further, the proposed 8-bit and 16-bit Re-CLAs require only 1.92% and 7.08% more energy over the existing CLA for achieving accuracy reconfigurability. Finally, the synthesis results of the Gaussian smoothing filters embedded with the proposed adders show higher energy efficiency with acceptable image quality over the state-of-the-art adder architectures.

     

A low-power adder operating on effective dynamic data ranges

To design a power-efficient digital signal processor, this study develops a fundamental arithmetic unit of a low-power adder that operates on effective dynamic data ranges. Before performing an addition operation, the effective dynamic ranges of two input data are determined. Based on a larger effective dynamic range, only selected functional blocks of the adder are activated to generate the desired result while the input bits of the unused functional blocks remain in their previous states. The added result is then recovered to match the required word length. Using this approach to reduce switching operations of noneffective bits allows input data in 2's complement and sign magnitude representations to have similar switching activities. This investigation thus proposes a 2's complement adder with two master-stage and slave-stage flip-flops, a dynamic-range determination unit and a sign-extension unit, owing to the easy implementation of addition and subtraction in such a system. Furthermore, this adder has a minimum number of transistors addressed by carry-in bits and thus is designed to reduce the power consumption of its unused functional blocks. The dynamic range and sign-extension units are explored in detail to minimize their circuit area and power consumption. Experimental results demonstrate that the proposed 32-bit adder can reduce power dissipation of conventional low-power adders for practical multimedia applications. Besides the ripple adder, the proposed approach can be utilized in other adder cells, such as carry lookahead and carry-select adders, to compromise complexity, speed and power consumption for application-specific integrated circuits and digital signal processors.     

Constant addition with flagged binary adder architectures

The goal of this paper is to present architectures that provide the flexibility within a regular adder to augment/decrement the sum of two numbers by a constant. This flexibility adds to the functionality of a regular adder, achieving a comparable performance to conventional designs, thereby eliminating the need of having a dedicated adder unit to perform similar tasks. This paper presents an adder design to accomplish three-input addition if the third operand is a constant. This is accomplished by the introduction of flag bits. Such designs are called Enhanced Flagged Binary Adders (EFBA). It also examines the effect on the performance of the adder when the operand size is expanded from 16 bits to 32 and 64 bits. A detailed analysis has been provided to compare the performance of the new designs with carry-save adders in terms of delay, area and power.     

Energy efficient computing by multi-mode addition

While adders are usually designed for the worst-case where their carry propagates through the entire bits, those cases rarely happen at real operation. This work takes advantage of the infrequent worst-case occurrences by designing adders for the average-case. Such design implies that computation errors may happen. Those are being corrected by implementing multi-mode addition with the aid of a dedicated control circuit. A power-delay-energy model is presented, enabling to find the optimal design point. We show that for cases where the system׳s critical paths are dictated by the adders, the system׳s operation voltage can be scaled, without harming the clock cycle and with very small performance degradation. For an adder per-se, potential energy savings of up to 50% is shown. The multi-mode adder has been integrated in a 32-bit pipelined MIPS processor, validating the correctness of such design approach.     

Designing Dynamic Carry Skip Adders: Analysis and Comparison

Addition represents an important operation that significantly impacts the performance of almost every data processing system. Due to their importance and popularity, addition algorithms and their corresponding circuit implementations have consistently received attention in research circles, over the years. One of the most popular implementations for long adders is the carry skip adder. In this paper, we present the design space exploration for a variety of carry skip adder implementations. More specifically, the paper focuses on the implementation of these adders using traditional as well as novel dynamic circuit design styles. 8–16–32–64-bit adders were implemented using traditional domino, footless domino, and data driven dynamic logic (D3L) in ST Microelectronics 45 nm 1 V CMOS process. In order to further exploit the advantages of the domino and D3L approaches, a new hybrid methodology combining both strategies was implemented and presented in this work. The adders were analyzed for energy-delay trade-offs at different process corners. They were also examined for their sensitivity to process and supply voltage variations. Comparative simulation results reveal that the full D3L adder ensures a better energy-delay product over all process corners (down to 34 % and 25 % lower than the domino and hybrid implementations, respectively, at the typical corner), while showing at the same time similar performance in terms of process and supply voltage variability as compared to the other considered carry skip adder configurations.