Failure study of Sn37Pb PBGA solder joints using temperature cycling,random vibration and combined temperature cycling and random vibration tests

In this paper, the tin-lead (Sn-37wt%Pb) eutectic solder joints of plastic ball grid array (PBGA) assemblies are tested using temperature cycling, random vibrations, and combined temperature cycling and vibration loading conditions. The fatigue lives, failure modes for the solder joints and the typical locations of the failed solder joints for single-variable loading and combined loading conditions are compared and analyzed. The results show much earlier solder joint failure for combined loading than that for either temperature cycling or pure vibration loading at room temperature. The primary failure mode is cracking within the bulk solder under temperature cycling, whereas the crack propagation path is along the intermetallic compound (IMC) layer for vibration loading. The solder joints subjected to combined loading exhibit both types of failure modes observed for temperature cycling and vibration loading; in addition, cracking through the IMC and the bulk solder is observed in the combined test. For temperature cycling and vibration loading, the components in the central region of the printed circuit board (PCB) have more failed solder joints than other components, whereas for combined loading, the number of failed solder joints in the components in different locations of the PCB is approximately the same.     

基于FEA的Cu pad模型对焊点可靠性的影响分析

随着集成电路封装技术的发展,器件焊点可靠性成为国内外研究的重点,该文介绍了影响BGA焊点可靠性的常见因素,并以一块电路板为例,构建带有焊点亚结构——Cu pad和无Cu pad的两种电路板模型,仿真分析热循环条件下Cu pad对焊点可靠性的影响,为整板简化建模提供参考意见。     

Experimental and statistical analyses of surface-mount technologyPLCC solder-joint reliability

The mechanical integrity of surface-mount technology (SMT) plastic leaded chip carrier (PLCC) solder joints has been studied by a four-point mechanical flexure fatigue test. The effects of printed circuit board (PCB) pad surface composition and testing temperature on solder-joint reliability are emphasized. Three sets of PCBs have been tested, one with Cu-Ni-Sn pad surface metallurgy, one with Cu-Ni-Au, and one with SMOBC/SSC (solder mask over bare copper selective solder coating). The solder composition was the 63 wt.%Sn/37 wt.%Pb eutectic. A two-parameter Weibull distribution was used for the lifetime model for these three products. The uniformity, quality, reliability, and a comparison of these products are discussed. The joints formed on Cu-Ni-Au and SMOBC boards were appreciably more reliable than those formed on the Cu-Ni-Sn board     

Computational parametric analyzes on the solder joint reliability of bottom leaded plastic (BLP) package

The bottom-leaded plastic (BLP) package is a lead-on-chip type of chip scale package (CSP) developed mainly for memory devices. Because the BLP package is one of the smallest plastic packages available, solder joint reliability becomes a critical issue. In this study, a 28-pin BLP package is modeled to investigate the effects of molding compound and leadframe material properties, the thickness of printed circuit board (PCB), the shape of solder joint and the solder pad size on the board level solder joint reliability. A viscoplastic constitutive relation is adopted for the modeling of solder in order to account for its time and temperature dependence on thermal cycling. A three-dimensional nonlinear finite element analysis based on the above constitutive relation is conducted to model the response of a BLP assembly subjected to thermal cycling. The fatigue life of the solder joint is estimated by the modified Coffin-Manson equation. The two coefficients in the modified Coffin-Manson equation are also determined. Parametric studies are performed to investigate the dependence of solder joint fatigue life on various design factors.     

A new experimental method to evaluate creep fatigue life of flip-chip solder joints with underfill

A new accelerated stress test method was developed to evaluate creep life of flip-chip solder joints with underfill. With this method, a cyclic creep test can be done simply by applying a displacement to the FR-4 printed circuit board (PCB) board in the axial direction. The creep fatigue test was performed under displacement control with real-time electrical continuity monitoring. Test results show that the displacement arising from the force is equivalent to the thermal stress during thermal expansion. It was found that the magnitude of displacement was proportional to the inelastic strain sustained by the solder joints. This indicates that the creep fatigue life obtained will not only reflect the quality of the solder joints, but can also be used to characterize the reliability of the flip-chip assembly. Finite element modeling was also performed to confirm the agreement of deformation of the solder joints under mechanical and thermal loading. Results suggest that deformation and strain of the flip-chip assembly are consistent or comparable between the mechanical and thermal cycling. The failure analysis indicates that fatigue cracks often initiate from the top edge of a corner solder joint in the creep fatigue test, which is similar to what would happen in thermal cycling test. Lastly, the effect of underfill on the creep fatigue test is discussed. It is postulated that the test method is applicable to other flip-chip assemblies, such as conductive adhesive interconnections.     

Reliability analysis and design for the fine-pitch flip chip BGA packaging

The geometry of solder joints in the flip chip technologies is primarily determined by the associated solder volume and die/substrate-side pad size. In this study, the effect of these parameters on the solder joint reliability of a fine-pitched flip chip ball grid array (FCBGA) package is extensively investigated through finite element (FE) modeling and experimental testing. To facilitate thermal cycling (TC) testing, a simplified FCBGA test vehicle with a very high pin counts (i.e., 2499 FC solder joints) is designed and fabricated. By the vehicle, three different structural designs of flip chip solder joints, each of which consists of a different combination of these design parameters, are involved in the investigation. Furthermore, the associated FE models are constructed based on the predicted geometry of solder joints using a force-balanced analytical approach. By way of the predicted solder joint geometry, a simple design rule is created for readily and qualitatively assessing the reliability performance of solder joints during the initial design stage. The validity of the FE modeling is extensively demonstrated through typical accelerated thermal cycling (ATC) testing. To facilitate the testing, a daisy chain circuit is designed, and fabricated in the package for electrical resistance measurement. Finally, based on the validated FE modeling, parametric design of solder joint reliability is performed associated with a variety of die-side pad sizes. The results show that both the die/substrate-side pad size and underfill do play a significant role in solder joint reliability. The derived results demonstrate the applicability and validity of the proposed simple design rule. It is more surprising to find that the effect of the contact angle in flip chip solder joint reliability is less significant as compared to that of the standoff height when the underfill is included in the package.     

Board level solder joint reliability analysis of stacked die mixed flip-chip and wirebond BGA

Stacked die BGA has recently gained popularity in telecommunication applications. However, its board level solder joint reliability during the thermal cycling test is not as well-studied as common single die BGA. In this paper, solder joint fatigue of lead-free stacked die BGA with mixed flip-chip (FC) and wirebond (WB) interconnect is analyzed in detail. 3D fatigue model is established for stacked die BGA with considerations of detailed pad design, realistic shape of solder ball, and non-linear material properties. The fatigue model applied is based on a modified Darveaux’s approach with non-linear viscoplastic analysis of solder joints. Based on the FC–WB stack die configuration, the critical solder ball is observed located between the top and bottom dice corner, and failure interface is along the top solder/pad interface. The modeling predicted fatigue life is first correlated to the thermal cycling test results using modified correlation constants, curve-fitted from in-house lead-free TFBGA46 (thin-profile fine-pitch BGA) thermal cycling test data. Subsequently, design analyzes are performed to study the effects of 20 key design variations in package dimensions, material properties, and thermal cycling test conditions. In general, thinner PCB and mold compound, thicker substrate, larger top or bottom dice sizes, thicker top die, higher solder ball standoff, larger solder mask opening, smaller PCB pad size, smaller thermal cycling temperature range, longer ramp time, and shorter dwell time contribute to longer fatigue life. SnAgCu is a common lead-free solder, and it has much better board level reliability performance than eutectic solder based on modeling results, especially low stress packages.     

Sensitivity Design of DL-WLCSP Using DOE With Factorial Analysis Technology

Newer, faster, and smaller electronic packaging approaches with high I/O counts and more complex semiconductor devices are emerging steadily and rapidly. Wafer-level chip scaling package (WLCSP) has a high potential for future electronic packaging. However, the solder joint reliability for a large chip size of about 100 mm² without underfill remains a troubling issue that urgently requires a solution. To this end, a double-layer WLCSP (DL-WLCSP) with stress compliant layers and dummy solder joint is adopted in this research in order to study the design parameters of enhancing the solder joint fatigue life. To ensure the validity of the analysis methodology, a test vehicle of Rambus DRAM is implemented to demonstrate the applicability and reliability of the proposed DL-WLCSP. The results of the thermal cycling in the experimental test show good agreement with the simulated analysis. Furthermore, to investigate the reliability impact of the design parameters, including solder volume, the arrangement of the die-side and substrate-side pad diameter, second compliant layer thickness, die thickness, and the printed circuit board (PCB) thickness, a design of experiment (DOE) with factorial analysis is adopted to obtain the sensitivity information of each parameter by the three-dimensional nonlinear finite-element models (FEMs). The statistics results of the analysis of variance reveal that the thickness of the second stress compliant layer and the volume of the solder joint can effectively reduce the stress concentration phenomenon, which occurs around the outer corner of the solder joint. In addition, the evident interaction between design parameters can also be obtained. The smaller thermal strains can be achieved through a better combination of design parameters of the geometry so as to provide the actual requirement of the physical information prior to manufacturing     

Board level reliability of PBGA using flex substrate

Assurance of board level reliability is necessary and required for adopting any new packages into products. This paper presents board level reliability test results of a flex substrate BGA under thermal and bend cyclic tests. It is well known that solder joint reliability is affected by many factors, such as the size of chip, joint stand-off height, pad design, test board surface finish, substrate gold plating thickness and the utilization of underfill material, etc. However, most of the works have been conducted are BGA on rigid substrates. In this work, thermal cyclic test is performed to re-examine these factors using package housed on a flex substrate. Bending test with two deflections is also performed to investigate solder joint fatigue life and failure modes under mechanically repetitive loading.Two-parameter Weibull model is used to analyze joint fatigue life. Failure analysis is conducted and discussed for each case. Under temperature cycling test, chip size, polyimide thickness and underfill material utilization were found to have significant impacts on joint fatigue life, especially the effect of applying underfill material to the joint. Epoxy thickness was found to have little effect on the joint fatigue life for this case.The effects of test board surface finish and substrate gold plating thickness on the joint fatigue life were found coupled. The term “substrate” here refers to the chip carrier, while the “board” here refers to motherboard, which is the board to assemble test vehicles on. The gold thickness here all refers to the electrolytic gold plating on the substrate. Using organic solderability preservative boards, substrate gold plating thickness affects joint fatigue life slightly, but with Au–Ni test boards, the effect is tremendous. The difference is due to different intermetallic compounds (IMC) formed. In other words, different IMC systems are formed due to different combination of test board surface finish and substrate gold plating thickness. As a result, different IMC induces different failure modes. The joint fatigue life under cyclic bend test with different deflections is also probed and shown. The corresponding failure modes are also discussed.     

Board level solder joint reliability modeling and testing of TFBGA packages for telecommunication applications

For thin-profile fine-pitch BGA (TFBGA) packages, board level solder joint reliability during the thermal cycling test is a critical issue. In this paper, both global and local parametric 3D FEA fatigue models are established for TFBGA on board with considerations of detailed pad design, realistic shape of solder joint, and nonlinear material properties. They have the capability to predict the fatigue life of solder joint during the thermal cycling test within ±13% error. The fatigue model applied is based on a modified Darveaux’s approach with nonlinear viscoplastic analysis of solder joints. A solder joint damage model is used to establish a connection between the strain energy density (SED) per cycle obtained from the FEA model and the actual characteristic life during the thermal cycling test. For the test vehicles studied, the maximum SED is observed at the top corner of outermost diagonal solder ball. The modeling predicted fatigue life is first correlated to the thermal cycling test results using modified correlation constants, curve-fitted from in-house BGA thermal cycling test data. Subsequently, design analysis is performed to study the effects of 14 key package dimensions, material properties, and thermal cycling test condition. In general, smaller die size, higher solder ball standoff, smaller maximum solder ball diameter, bigger solder mask opening, thinner board, higher mold compound CTE, smaller thermal cycling temperature range, and depopulated array type of ball layout pattern contribute to longer fatigue life.     

Thermal cycling analysis of flip-chip solder joint reliability

The reliability concern in flip-chip-on-board (FCOB) technology is the high thermal mismatch deformation between the silicon die and the printed circuit board that results in large solder joint stresses and strains causing fatigue failure. Accelerated thermal cycling (ATC) test is one of the reliability tests performed to evaluate the fatigue strength of the solder interconnects. Finite element analysis (FEA) was employed to simulate thermal cycling loading for solder joint reliability in electronic assemblies. This study investigates different methods of implementing thermal cycling analysis, namely using the "dwell creep" and "full creep" methods based on a phenomenological approach to modeling time independent plastic and time dependent creep deformations. There are significant differences between the "dwell creep" and "full creep" analysis results for the flip chip solder joint strain responses and the predicted fatigue life. Comparison was made with a rate dependent viscoplastic analysis approach. Investigations on thermal cycling analysis of the temperature range, (ΔT) effects on the predicted fatigue lives of solder joints are reported     

Reliability and RF performance of BGA solder joints with plastic-core solder balls in LTCC/PWB assemblies

In this paper board-level reliability of low-temperature co-fired ceramic (LTCC) modules with thermo-mechanically enhanced ball-grid-array (BGA) solder joint structure mounted on a printed wiring board (PWB) was experimentally investigated by thermal cycling tests in the 0–100 °C and −40 to 125 °C temperature ranges. The enhanced joint structure comprised solder mask defined (SMD) AgPt pad metallization, eutectic solder and plastic-core solder balls (PCSB). Similar daisy-chained LTCC modules with non-collapsible 90Pb10Sn solder spheres were used for a reference test set. The reliability of the joint structures was analyzed by resistance measurements, X-ray microscopy, scanning acoustic microscopy (SAM) and SEM/EDS investigation. In addition, a full-wave electromagnetic analysis was performed to study effects of the plastic-core material on the RF performance of the LTCC/BGA package transition up to millimeter-wave frequencies. Thermal cycling results of the modules with PCSBs demonstrated excellent fatigue performance over that of the reference. In the harsher cycling test, Weibull’s shape factor β values of 7.9 and 4.8, and characteristic lifetime θ values of 1378 and 783 were attained for the modules with PCSBs and 90Pb10Sn solder spheres, respectively. The primary failure mode in all test assemblies was fatigue cracking in eutectic solder on the ceramic side.     

Surface property of passivation layer on integrated circuit chip and solder mask layer on printed circuit board

Adhesion of underfill to passivation layer on integrated circuit chip and solder mask layer on printed circuit board is critical to the reliability of an underfilled flip chip package. In this study, the surface properties of solder mask and four passivation materials: benzocyclobutene (BCB), polyimide (PI), silicon dioxide (SiO/sub 2/), and silicon nitride (SiN) were investigated. A combination of both wet and dry cleaning processes was very effective to remove contaminants from the surface. The element oxygen, introduced during O/sub 2/ plasma treatment or UV/O/sub 3/ treatment, led to the increase of the base component of surface tension. X-ray photoelectron spectroscopy (XPS) experiments confirmed the increase of oxygen concentration at the surface after UV/O/sub 3/ treatment. Wetting of underfill on passivation and solder mask was slightly improved at higher temperatures. Although UV/O/sub 3/ cleaning and O/sub 2/ plasma treatment significantly improved the wetting of underfill on passivation materials, they did not improve adhesion strength of epoxy underfill to passivation. Therefore, the wetting was not the controlling factor in adhesion of the system studied.     

Coupling effects of mechanical vibrations and thermal cycling on reliability of CCGA solder joints

The microstructures and crack propagation behavior of CCGA (ceramic column grid array) solder joints after sinusoidal vibration loading, random vibration loading, and thermal cycling test have been discussed in this study. The failure mechanism of solder joints was analyzed using an experimental method and finite element analysis. It was found that the failed solder joints mainly distributed at the peripheral area in the solder column arrays and the crack initiation was mainly caused by mechanical vibrations. The deformation of PCB (printed circuit board) introduced by mechanical vibrations brought the outermost solder columns in CCGA devices with significant stress concentration and induced the initiation of cracks. Furthermore, cracks propagated during the process of mechanical vibrations and thermal cycling. The cracks propagated rapidly and the solder joints finally failed. The structure of the PCB holder was improved to relieve the vibration response from the peripheral joints. No visible crack was found in the solder joints after the same mechanical vibrations and thermal cycling test. The reliability of solder joints have been greatly improved with the new PCB holder.     

Impact of underfill and other physical dimensions on Silicon Lateral IGBT package reliability using computer model with discrete and continuous design variables

An effort to design and build a prototype LED driver system which is energy efficient, highly compact and with few component count was initiated by a consortium UK universities. The prototype system will be based on Silicon Lateral IGBT (LIGBT) device combined with chip on board technology. Part of this effort, finite element modelling and analysis were undertaken in order to mitigate the underfill dielectric breakdown failure and solder interconnect fatigue failure of the LIGBT package structure. Electro-static analysis was undertaken to predict the extreme electric field distribution in the underfill. Based on electro-static analysis, five commercial underfill were selected for thermo-mechanical finite element analysis on solder joint fatigue failure prediction under cyclic loading. A design optimisation analysis was endeavoured to maximise the solder interconnect reliability by utilising a computer model with continuous variable (physical dimensions) and discrete variables (underfill type) and a stochastic optimiser such as multi-objective mixed discrete particle swarm optimisation. From the optimisation analysis best trade off solution are obtained.     

Board level solder joint reliability analysis and optimization of pyramidal stacked die BGA packages

Due to requirements of cost-saving and miniaturization, stacked die BGA has recently gained popularity in many applications. However, its board level solder joint reliability during the thermal cycling test is not as well-studied as common single die BGA. In this paper, solder joint fatigue of wirebond stacked die BGA is analyzed in detail. 3D fatigue model is established for stacked die BGA with considerations of detailed pad design, realistic shape of solder ball, and non-linear material properties. The fatigue model applied is based on a modified Darveaux's approach with non-linear viscoplastic analysis of solder joints. The critical solder ball is observed located between the top and bottom dice corner, and failure interface is along the top solder/pad interface. The modeling predicted fatigue life is first correlated to the thermal cycling test results using modified correlation constants, curve-fitted from in-house TFBGA (thin-profile fine-pitch BGA) thermal cycling test data. Subsequently, design analyses are performed to study the effects of 16 key design variations in package dimensions, material properties, and thermal cycling test conditions. In general, smaller top and bottom dice sizes, thicker top or bottom die, thinner PCB, thicker substrate, higher solder ball standoff, larger solder mask opening size, smaller maximum ball diameter, smaller PCB pad size, smaller thermal cycling temperature range, longer ramp time, and shorter dwell time contribute to longer fatigue life. The effect of number of layers of stacked-die is also investigated. Finally, design optimization is performed based on selected critical design variables.     

温度与振动耦合条件下的电路板级焊点失效模式与疲劳寿命分析

基于正交试验法研究不同温度与振动耦合条件下的板级焊点失效行为与模式,采用L₉（34）混合水平正交表设计了不同温度（T）、加速度功率谱密度（PSD）与频率（V）条件下的加速寿命试验,结果表明三者对焊点可靠性影响程度为T>PSD>V,且温度是影响焊点失效模式的主要因素,随温度的升高,焊点裂纹逐渐从近封装侧的界面金属化合物（IMC）层向钎体内部扩展,焊点失效模式从脆性断裂向韧性断裂演化.基于焊点失效数据分析,发现焊点疲劳寿命对数值与PCB板背侧最大应变范围存在关联关系,并采用多项式拟合的方法建立了焊点疲劳寿命模型,拟合结果显示,该模型能较好的评估温度与振动耦合条件下的焊点寿命,预测精度较高.     

Mechanical deflection system (MDS) test and methodology for PBGAsolder joint reliability

A mechanical deflection system (MDS) was developed for highly accelerated tests to evaluate the solder joint fatigue performance in printed circuit board assemblies. The MDS test system can be used for design verification and qualification tests for solder joint reliability. Cyclic twisting deformation is imposed on an assembled printed circuit board (PCB) at isothermal conditions. The MDS test technique makes a significant contribution to reducing solder joint reliability testing cycle time. Fatigue performance of the PBGA solder joints subjected to the MDS test was investigated by three-dimensional finite element modeling. The solder joint fatigue lives were computed for several different MDS test conditions     

厚铜多层印制板的工程设计与生产控制

文章分析了厚铜多层印制板的主要制作难点,如内外层厚铜线路制作、厚铜多层印制板压合、厚铜多层印制板钻孔、厚铜多层印制板阻焊印刷等。针对主要制作难点,文章介绍了如何从板材和半固化片选用,压合叠层结构优化,内层线路图形设计补偿,钻孔设计,阻焊设计等工程设计手段来提高产品可靠性,以及介绍了重要制作工序的生产控制要点,有效提高了厚铜多层印制板的品质可靠性。     

Intermetallics Characterization of Lead-Free Solder Joints under Isothermal Aging

Solder interconnect reliability is influenced by environmentally imposed loads, solder material properties, and the intermetallics formed within the solder and the metal surfaces to which the solder is bonded. Several lead-free metallurgies are being used for component terminal plating, board pad plating, and solder materials. These metallurgies react together and form intermetallic compounds (IMCs) that affect the metallurgical bond strength and the reliability of solder joint connections. This study evaluates the composition and extent of intermetallic growth in solder joints of ball grid array components for several printed circuit board pad finishes and solder materials. Intermetallic growth during solid state aging at 100°C and 125°C up to 1000 h for two solder alloys, Sn-3.5Ag and Sn-3.0Ag-0.5Cu, was investigated. For Sn-3.5Ag solder, the electroless nickel immersion gold (ENIG) pad finish was found to result in the lowest IMC thickness compared to immersion tin (ImSn), immersion silver (ImAg), and organic solderability preservative (OSP). Due to the brittle nature of the IMC, a lower IMC thickness is generally preferred for optimal solder joint reliability. A lower IMC thickness may make ENIG a desirable finish for long-life applications. Activation energies of IMC growth in solid-state aging were found to be 0.54 ± 0.1 eV for ENIG, 0.91 ± 0.12 eV for ImSn, and 1.03 ± 0.1 eV for ImAg. Cu₃Sn and Cu₆Sn₅ IMCs were found between the solder and the copper pad on boards with the ImSn and ImAg pad finishes. Ternary (Cu,Ni)₆Sn₅ intermetallics were found for the ENIG pad finish on the board side. On the component side, a ternary IMC layer composed of Ni-Cu-Sn was found. Along with intermetallics, microvoids were observed at the interface between the copper pad and solder, which presents some concern if devices are subject to shock and vibration loading.