可重构计算混合系统硬件的设计与实现

可重构计算系统中软硬件资源的管理缺乏统一的机制,资源不能被有效利用。为此,设计并实现一种硬件任务模型,为上层软件提供统一的硬件接口,使操作系统能够对软硬件任务进行统一管理,并给出硬件任务下载器的实现结构及工作流程。实验结果表明,该硬件任务模型的运行效率较高,硬件任务下载器能较大地提高硬件任务的下载速率。     

基于FPGA的可重构JH算法设计与实现

针对现有可重构JH算法硬件实现方案吞吐量较低的问题,利用查找表方法对S盒进行优化,使改进的JH算法在现场可编程门阵列上实现时具有速度快和面积小的特点,在此基础上提出一种可重构方案。实验结果证明,该方案最高时钟频率可达322.81 MHz,占用 1 405 slices,具有资源占用少、性能参数较好、功耗较低等特点。     

基于虚拟可重构电路的演化硬件

针对演化硬件中高效的染色体编码问题,该文采用虚拟可重构电路(VRC)实现内进化方式的演化硬件。VRC是由可重配置功能块(CFB)组成的阵列,CFB之间通过多路选择开关电路建立信号传输通道。染色体可以对CFB的功能选择和多路选择开关状态直接进行编码,以此减少自身的长度。实例证明了该方法的有效性。     

可重构计算硬件平台的改进设计

针对现有可重构计算硬件平台配置时间长、灵活性受限的缺陷,提出一种改进设计。基于支持二维重构区域的Virtex-4现场可编程门阵列(FPGA)芯片,使重构模块放置更灵活、芯片面积利用率更高,通过将单片FPGA和外设集成在一块印刷电路板上,使系统的结构更紧凑,利用FPGA内嵌微处理器减轻通信和访存开销。调试结果表明,改进平台灵活性较高、功能和可扩展性更强。     

面向可重构计算系统的模块映射算法

为消除重构时间对可重构计算系统性能的影响,针对多重构模块,提出一种基于动态部分可重构技术的顺序型应用程序模块映射算法。利用动态可重构技术的高效性和灵活性,通过隐藏重构时间,达到减少程序执行时间和提高系统性能的目的。基于JPEG编码测试实例的实验结果表明,运用该算法实现的模块映射方案其程序执行速度是软件实现方式的3.31倍,是硬件方式的2.59倍。     

基于FPGA的AES加/解密算法的可重构设计

高级加密标准(AES)的传统实现方法是对加/解密算法进行单独设计,占用了过多的硬件资源。该文在分析AES加/解密算法机理的基础上,介绍了算法各模块的设计方法,通过分析提取了加/解密算法之间存在的共性,给出算法的可重构设计实例。通过FPGA仿真验证,该方案与传统设计方案相比,减少了资源的消耗。     

一种神经网络硬件实现的可重构设计

以BP网络为例,提出了一种可重构神经网络硬件实现方法。通过可重构体系结构、可重构部件的设计,可以灵活地实现不同规模、传递函数及学习方法的神经网络,从而搭建起神经网络快速硬件实现的平台。经过对一个模式识别问题的实现和测试,证明了这种设计方法的可行性。     

数据加密在可重构系统中的设计

阐述了可重构技术在密集型计算领域的广阔应用前景.基于该技术的数据加密系统兼具了硬件的效率和软件的灵活性,有着重要的理论与实际意义.在可重构系统基础上设计并实现了数据的加密计算.给出了一种通用的加密模块接口的设计方法,用于实现对加密模块的状态控制,并向接口用户提供一个简单易用,与底层实现无关的接口.在XUP开发平台上,用AES和DES数据加密算法进行了功能验证和性能分析,表明该方法行之有效.     

可重构测试仪器设计

介绍了发展可重构仪器技术的必要性，总结了可重构仪器的设计思想，针对可重构仪器的设计重点：硬件方面，介绍了作为可重构处理的关键之处的FPGA的发展现状；软件方面，引入框架复用的概念，很好地解决了将可重用构件组装成应用程序的问题。给出了采用“应用程序框架＋可复用构件”的开发方法的实例。     

可重构散列函数密码芯片的设计与实现

根据不同环境对安全散列算法安全强度的不同要求,采用可重构体系结构的思想和方法,设计一种可重构的散列函数密码芯片。实验结果表明,在Altera Stratix II系列现场可编程门阵列上,SHA-1, SHA-224/256, SHA-384/512的吞吐率分别可达到727.853 Mb/s, 909.816 Mb/s和1.456 Gb/s。     

基于随机森林算法的谷物粉分类及硬件加速

针对传统谷物粉种类检测速度较慢的问题,基于ZYNQ平台实现随机森林算法辅助微波无损检测技术对谷物粉种类进行高效准确识别。通过对随机森林模型硬件实现的分析研究,提出了一种改进模型参数结构,有效节省了硬件存储资源的消耗。为了缩短算法预测时间并降低系统功耗,在硬件实现时引入提前终止识别机制,在保证准确率不变的前提下避免不必要的决策树预测过程。针对Zedboard开发板,设计一种模型参数存储方案,充分利用片上资源保证系统正常工作。实验结果表明,与传统CPU实现随机森林算法相比,该方案在ZYNQ上运行的实测时间缩短约54.2%,同时没有引起识别精度的损失。     

基于FPGA的HEVC后处理CNN硬件加速器研究

针对高效视频编解码标准中后处理CNN算法在通用平台运行时产生的高延时缺点,提出一种基于现场可编程逻辑门阵列（FPGA）的后处理卷积神经网络硬件并行架构。提出的并行架构通过改进输入与输出缓冲的数据并发过程,调整卷积模块整体并行度,加快模块硬件流水。实验结果表明,基于本文所提出的并行架构设计的CNN硬件加速器在Xilinx ZCU102上处理分辨率为176×144视频流,计算性能相当于每秒360.5 GFLOPS,计算速度可满足81.01 FPS,相比时钟频率4 GHz的Intel i7-4790K,计算速度加快了76.67倍,相比NVIDIA GeForce GTX 750Ti加速了32.50倍。在计算能效比方面,本文后处理CNN加速器功耗为12.095 J,能效比是Intel i7-4790K的512.90倍,是NVIDIA GeForce GTX 750Ti的125.78倍。     

The case for reconfigurable hardware in wearable computing

Wearable computers are embedded into the mobile environment of their users. A design challenge for wearable systems is to combine the high performance required for tasks such as video decoding with the low energy consumption required to maximise battery runtimes and the flexibility demanded by the dynamics of the environment and the applications. In this paper, we demonstrate that reconfigurable hardware technology is able to answer this challenge. We present the concept and the prototype implementation of an autonomous wearable unit with reconfigurable modules (WURM). We discuss experiments that show the uses of reconfigurable hardware in WURM: ASICs-on-demand and adaptive interfaces. Finally, we present an experiment with an operating system layer for WURM.     

基于遗传算法的可重构系统软硬件划分

在考虑动态部分重构及重构延时等特征的基础上,采用遗传算法及其与爬山算法的融合实现可重构系统软硬件任务的划分,并采用动态优先级调度算法进行划分结果的评价。实验表明,在可重构系统的资源约束等条件下,算法能够有效地实现应用任务图到可重构系统的时空映射。     

Biometrics-based consumer applications driven by reconfigurable hardware architectures

Nowadays the development of automatic biometrics-based personal recognition systems is a reality in the current technological age. Not only those applications demanding stringent security levels but also many daily use consumer applications request the existence of high performance computational platforms in charge of recognizing the identity of an individual based on the analysis of his/her physiological or behavioural characteristics. The state of the art points out two main open problems in the implementation of such automatic applications: on the one hand, the needed improvement of the reliability level of the existing recognition systems in terms of accuracy, security and real-time performances; on the other hand, the cost reduction of those physical platforms in charge of the processing.This work addresses those limitations of current systems and aims at finding the proper system architecture to develop this kind of high-performance applications at low cost. Because of that, those existing solutions based on expensive multiprocessor systems like HPC (High Performance Computer), GPU (Graphics Processing Unit), or PC (Personal Computer) platforms need to be discarded, and instead of them embedded system solutions based on programmable logic devices are suggested in this work. The programmability performances of FPGA (Field Programmable Gate Array) devices together with the inherent parallelism of hardware design provide the needed flexibility to develop made-to-measure coprocessors in charge of accelerating those time-critical computational tasks. To address the cost of the system, dynamically reconfigurable FPGAs are suggested in this work. The scheduling of the recognition application into a series of mutually exclusive tasks, and the reutilization of those functional resources available in the FPGA by multiplexing different coprocessors in the same area along the application execution time allows reducing the size of the device and therefore its cost at the expense of the reconfiguration overhead.The hardware-software co-design of an AFAS (automatic fingerprint-based authentication system) under two different run-time reconfigurable platforms is presented as the proof of concept of the suggested architecture. The outstanding results achieved in this work pave the way for the implementation of biometric applications by means of run-time reconfigurable FPGAs.     

A hardware intelligent processing accelerator for domestic service robots

ABSTRACT

We present a method for implementing hardware intelligent processing accelerator on domestic service robots. These domestic service robots support human life; therefore, they are required to recognize environments using intelligent processing. Moreover, the intelligent processing requires large computational resources. Therefore, standard personal computers (PCs) with robot middleware on the robots do not have enough resources for this intelligent processing. We propose a ‘connective object for middleware to an accelerator (COMTA),’ which is a system that integrates hardware intelligent processing accelerators and robot middleware. Herein, by constructing dedicated architecture digital circuits, field-programmable gate arrays (FPGAs) accelerate intelligent processing. In addition, the system can configure and access applications on hardware accelerators via a robot middleware space; consequently, robotic engineers do not require the knowledge of FPGAs. We conducted an experiment on the proposed system by utilizing a human-following application with image processing, which is commonly applied in the robots. Experimental results demonstrated that the proposed system can be automatically constructed from a single-configuration file on the robot middleware and can execute the application 5.2 times more efficiently than an ordinary PC.     

蚁群算法硬件实现的研究进展

蚁群算法是优化领域中新出现的一种启发式仿生类智能进化算法,该算法采用分布式并行计算和正反馈机制．首先综述了蚁群算法及其硬件实现的研究进展,并讨论了蚁群算法硬件的主要特点;然后,着重介绍了基于现场可编程门阵列（FPGA）的蚁群算法硬件实现方案,简要阐述了蚁群算法在软硬件划分领域的应用进展;最后,展望了蚁群算法硬件实现领域未来的研究方向和内容．     

BIT试验中VME总线故障注入设备控制单元设计

针对航空电子设备BIT(机内测试)试验,设计了一种基于FPGA（现场可编程门阵列）的VME总线故障注入设备。该设备的控制单元用于完成故障注入设备的总体控制,是实现故障注入任务的关键。详细分析了VME总线故障注入设备的总体框架,给出了VME总线故障注入设备控制单元的设计方案,包括详细的软、硬件设计方法以及该系统的工作流程,并通过测试工具验证了控制单元设计和功能的正确性。最后,讨论了BIT试验中故障注入技术应用未来研究工作的开展方向。     

面向小型边缘计算的深度可分离神经网络模型与硬件加速器设计

神经网络参数量和运算量的扩大,使得在资源有限的硬件平台上流水线部署神经网络变得更加困难。基于此,提出了一种解决深度学习模型在小型边缘计算平台上部署困难的方法。该方法基于应用于自定义数据集的深度可分离网络模型,在软件端使用迁移学习、敏感度分析和剪枝量化的步骤进行模型压缩,在硬件端分析并设计了适用于有限资源FPGA的流水线硬件加速器。实验结果表明,经过软件端的网络压缩优化,这种量化部署模型具有94.60%的高准确率,16.64 M的较低的单次推理定点数运算量和0.079 M的参数量。此外,经过硬件资源优化后,在国产FPGA开发板上进行流水线部署,推理帧率达到了366 FPS,计算能效为8.57 GOPS/W。这一研究提供了一种在小型边缘计算平台上高性能部署深度学习模型的解决方案。     

多种哈希算法的可重构硬件架构设计

针对现有的哈希算法硬件架构仅实现少量几种算法的问题,设计了一种可实现SM3,MD5,SHA-1以及SHA-2系列共7种哈希算法的可重构IP,以满足同一系统对安全性可选择的需求。通过分析各哈希算法及其运算逻辑的相似性,该设计最大化地重用加法器和寄存器,极大地减少了总的实现面积。此外,该设计灵活可配,可以对内存直接存取。以Altera的Stratix II为FPGA目标器件,其最高频率可达100 MHz,总面积较现有设计减少26.7%以上,且各算法单位面积吞吐率均优于现有设计。