Efficient Distributed On-Chip Decoupling Capacitors for Nanoscale ICs

A distributed on-chip decoupling capacitor network is proposed in this paper. A system of distributed on-chip decoupling capacitors is shown to provide an efficient solution for providing the required on-chip decoupling capacitance under existing technology constraints. In a system of distributed on-chip decoupling capacitors, each capacitor is sized based on the parasitic impedance of the power distribution grid. Various tradeoffs in a system of distributed on-chip decoupling capacitors are also discussed. Related simulation results for typical values of on-chip parasitic resistance are also presented. The worst case error is 0.003% as compared to SPICE.      

基于介质片加载实现MIMO介质谐振器天线解耦

提出了一种通过在介质谐振器(DR)上表面侧边加载介质片(DS)来实现1×2 MIMO介质谐振器天线(DRA)解耦的新方法。1×2 MIMO DRA采用双层介质基板结构以优化阻抗匹配特性和辐射特性,两DR的边到边间距为0,天线工作在毫米波频段。所加载的DS使得DR内的场重新分布并向DS加载区域以及DS内集中,从而减弱耦合到另一DR单元的场强以实现解耦效果。基于ANSYS HFSS的仿真结果表明天线的-10 dB阻抗匹配带宽为25.6%(22.75～29.43 GHz),带内最大实现了30 dB的隔离度的增强。     

基于自适应遗传算法的去耦电容器自动选择

针对在电源分配网络设计过程中,人工选择去耦电容器个数会导致反复设计的问题,提出了基于自适应遗传算法的去耦电容器自动选择的方法。该方法模拟达尔文生物进化论的自然选择过程,在满足目标阻抗的同时,选择出使用去耦电容器总个数最少的方案,以实现自动选择的目的。仿真结果与PCB全波仿真软件结果对比表明,该方法能够满足工程应用的要求,并已被某大型IT企业所采用。     

Flexible Electronics: Thin Silicon Die on Flexible Substrates

Silicon thinned to 50 mum and less is flexible allowing the fabrication of flexible and conformable electronics. Two techniques have been developed to achieve this goal using thinned die: die flip chip bonded onto flexible substrates [polyimide and liquid crystal polymer (LCP)] and die flip chip laminated onto LCP films. A key to achieving each of these techniques is the thinning of die to a thickness of 50 mum or thinner. Conventional grinding and polishing can be used to thin to 50 mum. At 50 mum, the active die becomes flexible and must be handled by temporarily bonding it to a holder die for assembly. Both reflow solder and thermocompression assembly methods are used. In the case of solder assembly, underfill is used to reinforce the solder joints. With thermocompression bonding of the die to an LCP substrate, the LCP adheres to the die surface, eliminating the need for underfill.     

用于芯片级封装载板的绝缘材料

电子产品向轻、薄、多功能及高频高速的方向发展对用于封装基般的绝缘材料提出了更高的要求,本文从材料 的电性能、力学性能、热性能以及与标准PCB制作工艺相容性等方面阐述了芯片级封装载板对绝缘材料的要求。     

Layout of Decoupling Capacitors in IP Blocks for 90-nm CMOS

On-chip decoupling capacitors (decaps) in the form of MOS transistors are widely used to reduce power supply noise. This paper provides guidelines for standard cell layouts of decaps for use within Intellectual Property (IP) blocks in application-specific integrated circuit (ASIC) designs. At 90-nm CMOS technology and below, a tradeoff exists between high-frequency effects and electrostatic discharge (ESD) reliability when designing the layout of such decaps. In this paper, the high-frequency effects are modeled using simple equations. A metric is developed to determine the optimal number of fingers based on the frequency response. Then, a cross-coupled design is described that has been recently introduced by cell library developers to handle ESD problems. Unfortunately, it suffers from poor response times due the large resistance inherent in its design. Improved cross-coupled designs are presented that properly balance issues of frequency response with ESD performance, while greatly reducing thin-oxide gate leakage.      

Oxide-Nitride Storage Dielectric Formation in a Single-Furnace Process for Trench DRAM

A simplified and integrated technique has been proposed to form an oxide/nitride storage dielectric in a single-furnace process by low-pressure oxidation and nitride film deposition with an extra$hboxN_2hboxO$treatment for the trench dynamic random access memory (DRAM). Compared to the conventional nitride/oxide dielectric, this newly developed dielectric enjoys cell-capacitance-enhancement factor as high as 12.5% without degrading the leakage current and electron-trapping property. From the reliability test, the qualification for the DRAM application is also proven by the dielectric lifetime longer than 10-years. Most importantly, this technique can reduce the production cycle time without an additional equipment investment, which is essential in the cost-competitive DRAM arena.     

有机显示器和电子器件的柔性基板和封装

尽管柔性显示技术面临性能的挑战,第一款商业化的产品仍计划在2006-2007年度投入市场。     

Efficient Full-Wave Characterization of Discrete High-Density Multiterminal Decoupling Capacitors for High-Speed Digital Systems

This paper presents an efficient surface-based finite-element method for the full-wave characterization of high-density and multiterminal decoupling capacitors (2, 8, 14, and any arbitrary number of terminals). In contrast to traditional finite-element methods that involve 3-D volumetric unknowns, this method reduces the unknowns one needs to solve to those on 2-D surfaces only. In addition, the reduction from the 3-D volume-based matrix to a 2-D surface-based one is achieved efficiently by exploiting the geometrical specialty of the decap structure. The entire numerical procedure is numerically rigorous without making any approximation. Its efficiency and accuracy have been demonstrated by both measurements and numerical experiments. Based on its fast and accurate solution, different design configurations of capacitors were studied to identify the optimal configuration that can maximize the performance of a decoupling capacitor. Furthermore, the full-wave model obtained from the proposed method was employed to assess the accuracy of conventional series lumped RLC capacitor models. In addition, the full-wave model was incorporated into a high-performance microprocessor's power delivery network to investigate system performance.     

柔性衬底上六噻吩薄膜的有序生长

采用石英晶体微天平实时监测薄膜生长速率,控制衬底温度和生长速率,分别在柔性聚乙烯吡咯烷酮(PVP)绝缘层和柔性氧化铟锡(ITO)透明导电层上真空蒸发沉积了分子有序排列的六噻吩薄膜.X射线衍射分析表明,对PVP层而言,六噻吩薄膜有序生长的条件为衬底温度90°c、生长速率10 nm/min,六噻吩分子链始终与衬底平行,降低衬底温度将导致薄膜结晶度的下降.而对ITO层来说,六噻吩薄膜有序生长的条件为衬底温度50℃、生长速率10 nm/min,衬底温度显著影响了六噻吩分子取向,室温下六噻吩分子链与衬底成一定夹角,随着温度的提高六噻吩分子链趋向与衬底平行.对PVP和ITO衬底,生长速率太高或太低都将导致薄膜结晶度的下降.     

Organic Thin‐Film Transistors with Anodized Gate Dielectric Patterned by Self‐Aligned Embossing on Flexible Substrates

An upscalable, self‐aligned patterning technique for manufacturing high‐ performance, flexible organic thin‐film transistors is presented. The structures are self‐aligned using a single‐step, multi‐level hot embossing process. In combination with defect‐free anodized aluminum oxide as a gate dielectric, transistors on foil with channel lengths down to 5 μm are realized with high reproducibility. Resulting on‐off ratios of 4 × 10⁶ and mobilities as high as 0.5 cm² V^?1 s^?1 are achieved, indicating a stable process with potential to large‐area production with even much smaller structures.     

有机显示器和电子器件的柔性基板和封装

尽管柔性显示技术面临性能的挑战，第一款商业化的产品仍计划在2006-2007年度投入市场。     

Transfer Processes for Thermally Stable Large-Size TFT Flexible Substrates

We report on glass etching transfer processes to obtain thermally stable large-size TFT flexible substrates on plastic film bases. The transfer processes include high-pressure jet etching that allows us to achieve good etch-rate uniformity over the large area and the utilization of an adhesive having a low elastic modulus. From the experiments and simulations, we find that using an adhesive having a low elastic modulus is effective in reducing bend of the flexible substrate under thermal stresses. The simulations also predict that the reduction in the bend corresponds to the reduction in the principal stress of the adhesive, leading to the suppression of the film peeling off from the thinned glass. Using the transfer processes, we have successfully fabricated thermally stable TFT flexible substrates (300 mmtimes350 mm times200 mum) that have satisfactory electrical characteristics     

Realization of Flexible Plasma Display Panels on PET Substrates

DC plasma display panels are fabricated on flexible polyethylene terephtalate (PET) substrates. Each pixel consists of laterally placed anode and cathode electrodes. All electrical elements are formed on a single PET substrate, whereas a second substrate is needed to encapsulate the panel. Silver is used as the metal for each electrode and standard photolithography is used to form each cell. A 150-/spl mu/m-thick layer of a UV-curable polymeric adhesive was used to form barrier ribs to both electrically isolate neighboring cells and to encapsulate the plasma. Conversion of vacuum UV into visible light is possible by blast-embedding of proper phosphor grains into the top substrate. The current-voltage and turn-on voltage versus pressure characteristics are examined. Effect of curvature on turn-on voltage is addressed.     

Novel Integration of Metal–Insulator–Metal (MIM) Capacitors Comprising Perovskite-type Dielectric and Cu Bottom Electrode on Low-Temperature Packaging Substrates

In this letter, a novel integration scheme, for metal-insulator-metal capacitors comprising perovskite-type dielectrics and Cu-based bottom electrodes, has been demonstrated on low-temperature FR4 packaging substrates. Cu oxidation during dielectric deposition and postannealing is completely avoided by a dielectric-first process flow with Ti as oxygen-getter. By using evaporated barium strontium titanate as capacitor dielectric, a maximum capacitance density (~1250 nF/cm² at 100 kHz) and moderate leakage current (< 4 times 10^-5 A/cm² at 2 V) have been achieved with rapid thermal annealing at 700degC. Higher temperature leads to dielectric degradation. Combined with advanced deposition techniques, this integration scheme enables realization of high-performance embedded capacitors that can be integrated with printed circuit board technology.     

MnO2-Based Electrochemical Supercapacitors on Flexible Carbon Substrates

Manganese dioxide films were grown on large area flexible carbon aerogel substrates. Characterization by x-ray diffraction confirmed α-MnO₂ growth. Three types of films were compared as a function of hexamethylenetetramine (HMTA) concentration during growth. The highest concentration of HM TA produced MnO₂ flower-like films, as observed by scanning electron microscopy, whose thickness and surface coverage lead to both a higher specific capacitance and higher series resistance. Specific capacitance was measured to be 64 F/g using a galvanostatic setup, compared to the 47 F/g-specific capacitance of the carbon aerogel substrate. Such supercapacitor devices can be fabricated on large area sheets of carbon aerogel to achieve high total capacitance.     

Analysis of the Influence of Substrate on the Performance of On-Chip MOS Decoupling Capacitors

The interaction between substrate and devices is normally neglected during the design of on-chip MOS decoupling capacitors (decaps). However, it may significantly influence the decap performance to reduce high-frequency power supply noise. In this paper we propose a novel six-parameter analytical decap model which accounts for substrate and device interactions. Our model has been compared against state-of-the-art decap models. Moreover, it has been extensively validated through simulations and measurements. For 65 nm LP-CMOS, a close correlation has been obtained over a large frequency range from 10 MHz up to 10 GHz. Furthermore, we introduce the maximum decap admittance as a new metric for decap performance qualification. Closed-form expressions have been derived to calculate maximum admittance. Finally, we determine the relationship between relevant figure-of-merit parameters for decap design optimization.     

CaZrO3掺杂对耐高温陶瓷电容介电性能的影响

用钛酸铋钠(BNT)改性亚微米级钛酸钡合成居里温度较高的基料。在Nb2O5-Ta2O5-ZnO基础配方体系基础上,利用CaZrO3对其掺杂改性,得到了介电性能优越的耐高温电容器陶瓷材料,其居里温度高(150℃),介电常数相对较高(1 200以上)。从离子取代及微观结构表征等方面研究了不同CaZrO3掺杂量对改性钛酸钡陶瓷的介电常数、容温变化率和介电损耗的影响,为研制耐高温多层陶瓷电容器(MLCC)提供了参考。     

Effects of Sulfur Passivation on Germanium MOS Capacitors With HfON Gate Dielectric

In this letter, we study the effects of sulfur (S) passivation, using aqueous ammonium sulfide ((NH₄)₂S), on germanium (Ge) MOS capacitors with sputtered HfON as gate dielectric and TaN as metal-gate electrode. Compared with control samples, the S passivation can effectively reduce both equivalent oxide thickness and interface-state density. X-ray-photoelectron-spectroscopy analysis shows that (NH₄)₂S treatment can reduce the Ge-O bonds on Ge surface. The thermal stability of the S passivation under different postmetal-annealing temperatures was also examined, and it was found that samples with (NH₄)₂S treatment exhibit stable Ge/high-fc interface upon 550-deg C postmetal-deposition annealing, whereas interface quality degrades for those samples without S passivation.