Retargeting a hardware compiler using protocol converters

We show how to retarget a compiler for occam-like programs from generating two-phase delay-insensitive circuits to generating four-phase speed independent circuits. The specifications of the two-phase circuit elements for our compiler are used to produce a set of equivalent specifications for four-phase circuit elements using a set of protocol converters. Automatic tools have been used in checking that our four-phase implementations satisfy their specifications.     

The design of a pascal compiler

The development of a compiler for the programming language PASCAL¹ is described in some detail. Design decisions concerning the layout of program and data, the organization of the compiler including its syntax analyser, and the over-all approach to the project are discussed. The compiler is written in its own language and was implemented for the CDC 6000 computer family. The reader is expected to be familiar with Reference 1.     

树型编译系统设计

从编译系统的用户界面出发,探讨了不同类型用户界面的优缺点。提出了语句模块预处理-编译器的设计思路,阐述了此设计方法基于树型界面实现可视化编译系统的具体实现步骤,重点讨论了树型系统部分的实现方法。     

Handling advanced scheduling heuristics under a hardware compiler generation environment

The complexity of modern digital systems requires complex design entry methods and thus, language based designs are often an appealing alternative for schematics. Language based design entry, supports high-level design transformations through formal and executable traditional compiler construction problem specifications, their main advantages being modularity and declarative notation. In this paper, this idea is exploited under a powerful compiler construction system and a methodology is given to design formal and executable high-level hardware manipulators. In effect, this methodology stands as a meta-level between hardware transformations and their implementation and can be valuable in fast evaluation of new ideas and techniques.     

Architectural design of MDX compiler via attribute-driven design

MDX is a language that expresses selections, calculations, and some metadata definitions against an Online Analytical Processing （OLAP） database. As the user interface with OLAP, the MDX complier is a major component of the OLAP analysis server. This paper addresses the system design of MDX compiler via the ADD method, meaning that system requirements, including functional and quality requirements and constraints, are considered as drivers in the design process. The output architecture satisfies not only that the functional requirements but also the important qualities the system must possess.     

The Monarch parallel processor hardware design

The Monarch architecture team took advantage of custom VLSI in the design of a shared-memory parallel processor. The simple structure eases the task of programming a massively parallel machine     

自动指纹识别系统的硬件逻辑实现

介绍基于NIOSⅡ嵌入式处理器的自动指纹识别系统的实现方法;具体说明自动指纹识别系统的基本原理、硬件结构设计、用户自定制指令和SOPC系统设计;详细说明如何在SOPC开发工具中完成系统的硬件开发和在NIOSⅡIDE集成开发环境中完成系统的软件开发。     

Normal form approach to compiler design

This paper demonstrates how reduction to normal form can help in the design of a correct compiler for Dijkstra's guarded command language. The compilation strategy is to transform a source program, by a series of algebraic manipulations, into a normal form that describes the behaviour of a stored-program computer. Each transformation eliminates high-level language constructs in favour of lower-level constructs. The correctness of the compiler follows from the correctness of each of the algebraic transformations.     

V-Pascal: An automatic vectorizing compiler for Pascal with no language extensions

An automatic vectorizing compiler called V-Pascal is described in detail. The compiler has been designed and implemented with a view to vectorizing Pascal source programs. Using the mechanism of vector indirect addressing, it reduces multiply nestedfor loops to equivalent single loops, which are then executed by vector mode with sufficiently long vector lengths. TheD matrix, which is an adjacency matrix giving dependences between intermediate code nodes, plays an important role in the V-Pascal compiler. It is demonstrated that, in some cases, the V-Pascal compiler yields object code that runs faster than the Fortran counterpart. This paper mainly presents the basic constituents of the Version 1 of the V-Pascal compiler. Version 2 includes higher functions such as vectorization ofwhile-do loops and recursive procedures, vectorization of character string manipulations and relational database operations (written in Pascal), and automatic parallel decomposition for multiprocessor environments.     

硬件实时操作系统的设计与实现

在阐述了硬件实时操作系统的结构和运行机制的基础上,着重论述了基于FPGA设计实现的硬件实时操作系统,并在Actel公司的APA075上实现了任务调度、中断管理、定时器管理等实时操作系统基本功能。该硬件实时操作系统具有强实时性、高确定性和低系统开销等优点。     

The microprocessor in manufacturing: Systems and hardware design considerations

Microprocessors are finding an expanding role in manufacturing, particularly in data collection and in process and machine control. Their capabilities, their power, and their ability to control processes and machines, are being more fully realized every day.

The expanding application of micros is explored. The use of a micro for a specific application is discussed.     

PXA255处理器最小系统的硬件设计

本设计采用的Xscale架构处理器是为新一代无线手持应用产品开发的嵌入式处理器,是PCA()开发式平台构架中的应用子系统与通信子系统的嵌入式处理器。本文根据作者的实际开发,针对IntelXSale架构处理器芯片PXA255结构特点,主要研究了该芯片最小系统硬件电路设计的方法,系统由JTAG仿真接口电路,电源电路,复位电路,以及外围存储器接口电路组成。并结合实际应用情况,给出了相应电路。     

Evolvable hardware: using evolutionary computation to design and optimize hardware systems

Evolvable hardware lies at the intersection of evolutionary computation and physical design. Through the use of evolutionary computation methods, the field seeks to develop a variety of technologies that enable automatic design, adaptation, and reconfiguration of electrical and mechanical hardware systems in ways that outperform conventional techniques. This article surveys evolvable hardware with emphasis on some of the latest developments, many of which deliver performance exceeding traditional methods. As such, the field of evolvable hardware is just now starting to emerge from the research laboratory and into mainstream hardware applications.     

一种基于ADL的编译器自动生成方法研究

编译器是嵌入式系统软件中的重要组成部分,它对嵌入式系统的软件开发有重要影响。本文在将体系结构描述语言(ADL)与传统可移植编译器相结合,自动生成嵌入式系统编译器的思想基础上,对自动生成工具genmd的结构进行了分析。重点对其指令识别和机器描述生成部分进行了抽象和建模。同时,针对genmd不支持分支跳转类指令的问题提出了改进方案。     

Implementing macro test in silicon compiler design

A testability strategy for a complex VLSI device that is implemented in the Piramid digital-signal-processor silicon compiler is presented. The macro test method proposed supports built-in self-test, scan test, restricted partial scan, and test-control logic at various levels in the design hierarchy. The strategy uses techniques such as a macro test plan, transfer information, and intermediate vector storage. The overhead from adding testability is only 10% of the total area and test-program generation is done with 100% fault coverage in a very short time, since there is no need for global test-pattern generation. A set of tools that guide the testability implementation from design to the final test program is described     

Model checking: a hardware design perspective

Current practices in the verification of commercial hardware designs (digital, synchronous, and sequential semiconductors) are described. Recent advances in verification by the mathematical technique called model checking are described, and requirements for the successful application of model checking in commercial design are discussed.     

A novel compiler support for automatic parallelization on multicore systems

The widespread use of multicore processors is not a consequence of significant advances in parallel programming. In contrast, multicore processors arise due to the complexity of building power-efficient, high-clock-rate, single-core chips. Automatic parallelization of sequential applications is the ideal solution for making parallel programming as easy as writing programs for sequential computers. However, automatic parallelization remains a grand challenge due to its need for complex program analysis and the existence of unknowns during compilation. This paper proposes a new method for converting a sequential application into a parallel counterpart that can be executed on current multicore processors. It hinges on an intermediate representation based on the concept of domain-independent kernel (e.g., assignment, reduction, recurrence). Such kernel-centric view hides the complexity of the implementation details, enabling the construction of the parallel version even when the source code of the sequential application contains different syntactic variations of the computations (e.g., pointers, arrays, complex control flows). Experiments that evaluate the effectiveness and performance of our approach with respect to state-of-the-art compilers are also presented. The benchmark suite consists of synthetic codes that represent common domain-independent kernels, dense/sparse linear algebra and image processing routines, and full-scale applications from SPEC CPU2000.     

The design and implementation of an ASN.1-C compiler

Abstract syntax notation one (ASN.1) has been widely used in international standard specification: its transfer-syntax, the basic encoding rules (BER), is used as the external data representation. A BER implementation called the ED library is presented. The ED library includes a number of encoding and decoding routines that may be used as primitive functions to compose encoders and decoders for arbitrarily complicated ASN.1 data types. Based on the ED library an ASN.1-C compiler, called CASN1, is designed and implemented to free the protocol implementers from the arduous work of translating protocol-defined data-types and constructing their encoders and decoders. Given an ASN.1 protocol specification, CASN1 automatically translates the input ASN.1 modules into C and generates the BER encoders and decoders for the protocol defined data-types. The CASN1 design principles, user interface, and some example applications are discussed. The performance of the ED library and generated CASN1 code is also measured and discussed     

一种基于ARM的集中器的硬件实现

介绍了一种以ARM9为核心,以Windows CE5.0为操作系统的集中器。它符合国家电网的Q/GDW 374.2-2009技术标准,可以在国家电网中使用。给出了集中器的系统框图,介绍了集中器的主要实现电路,论述了其主要工作原理。     

一种嵌入式运动控制系统的硬件设计

运动控制技术是制造业中的一项重要技术,它的发展将极大地提高现代制造业的整体水平。本文分析了在工业运动控制器中经常用到的关键技术,并设计了一套嵌入式运动控制系统的硬件结构。