Effect of Hydrogen implantation on polysilicon p-n junctions

The effect of hydrogen implantation on theI(V)characteristics of lateral polysilicon p-n junctions is reported. After implantation with hydrogen and annealing at 400°C, a moderate decrease in the forward current and a large decrease in the reverse current is observed. In addition, the reverse breakdown voltage is increased. Best results were obtained for hydrogen dose of 10¹⁶cm^-2. The measurements are explained by considering both electric field enhancement of emission and capture rates and the generation of new trap levels by ion implantation.     

CMOS shallow-trench-isolation to 50-nm channel widths

The applicability of shallow-trench-isolation (STI) for CMOS to 50-nm channel widths has been explored. Transistors with channel width to 50 nm and trench width to 200 nm have been fabricated. A comparison of several oxide-filled and polysilicon field-plate-filled STI structures is presented including processing, device performance, and isolation leakage. It is shown that V_th roll off as a function of channel width can be made as small as 65 mV and 145 mV at 100 nm channel width for polysilicon and oxide filled STI, respectively. Off-state currents less than 5×10^-12 A/μm and subthreshold slope around 80 mV/dec have been reached. Isolation breakdown voltages are about 8 V. Poly-filled STI effectively reduces channel edge effects, and provides excellent off-state, on-state, and turn-on characteristics all the way to 50-nm channel widths     

Optimized trench MOSFET technologies for power devices

Low-voltage silicon trench power MOSFETs with forward conductivities approaching the silicon limit are reported. Vertical trench power MOSFETs with the measured performances of V_DB =55 V (R_sp=0.2 mΩ-cm², k _D=5.7 Ω-pF) and V_DB=35 V (R_sp=0.15 mΩ-cm², k_D =4.3 Ω-PF) were developed where V_DB is the drain-source avalanche breakdown voltage, R_sp is the specific on-state resistance, and k_D=R _spC_sp is the input device technology factor where C_sp is the specific MOS gate input capacitance. The optimum device performance resulted from an advanced trench processing technology that included (1) an improved RIE process to define scaled vertical silicon trenches, (2) silicon trench sidewall cleaning to reduce the surface damage, and (3) a novel polysilicon gate planarization technique using a sequential oxidation/oxide etchback, process. The measured performances are shown to be in excellent agreement with the two-dimensional device simulations and the calculated results obtained from an analytical model     

Avalanche phenomena in 4H-SiC p-n diodes fabricated by aluminum orboron implantation

Characteristics of p-n junction fabricated by aluminum-ion (Al⁺) or boron-ion (B⁺) implantation and high-dose Al⁺-implantation into 4H-SiC (0001) have been investigated. By the combination of high-dose (4×10¹⁵ cm^-2) Al⁺ implantation at 500°C and subsequent annealing at 1700°C, a minimum sheet resistance of 3.6 kΩ/□ (p-type) has been obtained. Three types of diodes with planar structure were fabricated by employing Al+ or B+ implantation. B ⁺-implanted diodes have shown higher breakdown voltages than Al⁺-implanted diodes. A SiC p-n diode fabricated by deep B+ implantation has exhibited a high breakdown voltage of 2900 V with a low on-resistance of 8.0 mΩcm² at room temperature. The diodes fabricated in this study showed positive temperature coefficients of breakdown voltage, meaning avalanche breakdown. The avalanche breakdown is discussed with observation of luminescence     

一种基于VDMOS技术的浅沟槽平面栅MOSFET新结构

本文基于VDMOS技术提出了一种浅沟槽平面栅MOSFET（TPMOS）新结构,其中浅沟槽位于VDMOS多晶硅平面栅下方n-漂移区的两元胞中央。与传统的VDMOS结构相比,新结构不仅可以显著改善器件的导通电阻(RON)和击穿电压(VBR),减小它们对栅极长度的依赖,而且除浅沟槽外,制作工艺与VDMOS完全兼容。采用TPMOS结构可为器件设计和制造提供更大的自由度。     

A high-voltage polysilicon TFT with multigate structures

An approach is proposed for obtaining a high-voltage thin-film transistor (TFT) with multigate structure where polysilicon TFTs are connected in series. A basic principle for high-voltage operation has been investigated in detail through calculations based on a model describing log I_DS-V_GS characteristics observed in a single-gate polysilicon TFT. It has been found that off-state (V_GS<0) operation of the polysilicon TFT causes a large increase of breakdown voltage of the multigate TFT with the result that a nearly equal fraction of drain voltage is applied across the region around each elemental TFT. The breakdown voltage of drain of the fabricated multigate TFT which has five elemental TFTs has been elevated up to 80 V     

4H-SiC TSOB结势垒肖特基二极管静态特性

为增强器件的反向耐压能力,降低器件的漏电功耗,采用Silvaco TCAD对沟槽底部具有SiO₂间隔的结势垒肖特基二极管(TSOB)的器件特性进行了仿真研究。通过优化参数来改善导通压降(V_F)-反向漏电流(I_R)和击穿电压的折衷关系。室温下,沟槽深度为2.2 μm时,器件的击穿电压达到1 610 V。正向导通压降为2.1 V,在V_F=3 V时正向电流密度为199 A/cm²。为进一步改善器件的反向阻断特性,在P型多晶硅掺杂的有源区生成一层SiO₂来优化漂移区电场分布,此时改善的器件结构在维持正向导通压降2.1 V的前提下,击穿电压达到1 821 V,增加了13%。在1 000 V反向偏置电压下,反向漏电流密度比普通结构降低了87%,有效降低了器件的漏电功耗。普通器件结构的开/关电流比为2.6×10³(1 V/-500 V),而改善的结构为1.3×10⁴(1 V/-500 V)。     

A High-Performance Polysilicon Thin-Film Transistor Built on a Trenched Body

In this paper, a high-performance polysilicon thin-film transistor (poly-Si TFT) with a trenched body is proposed, fabricated, and studied. This new trenched TFT can be easily produced by filling and etch-back technology without destroying the channel film quality. The addition of the body trench is found to reduce the off-state leakage current by 70% on average, because the trench induces a carrier scattering effect in the poly-Si grain-boundary traps, thereby affecting the leakage path. Although the off-state current is substantially reduced, the on-state current is comparable with that of a conventional TFT. Our multiple-trenched-body TFT is also shown to improve the breakdown voltage by 11%.      

Process and device performance of a high-speed double poly-Sibipolar technology using borosenic-poly process with coupling-baseimplant

Use of boron and arsenic diffusions through an emitter polysilicon film (borosenic-poly emitter-base process) produces a transistor base width of less than 100nm with an emitter junction depth of 50 nm and an emitter-to-base reverse leakage current of approximately 70 pA. The borosenic-poly process resolves both the channeling and shadowing effects of a sidewall-oxided spacer during the base boron implantation. The process also minimizes crystal defects generated during the emitter and base implantations. The coupling-base boron implant significantly improves a wide variation in the emitter-to-collector periphery punchthrough voltage without degrading the emitter-to-base breakdown voltage current gain, cutoff frequency, or ECL gate delay time. A deep trench isolation with 4-μm depth and 1.2-μm width reduces the collector-to-substrate capacitance to 9 fF, while maintaining a transistor-to-transistor isolation voltage of greater than 25 V. The application of self-aligned titanium silicide technology to form polysilicon resistors without holes and to reduce the sheet resistance of the emitter and collector polysilicon electrodes to 1 Ω/square is discussed     

SOI电路窄沟槽隔离技术研究

文章利用SOI材料片做衬底,开展了SOI电路窄沟槽隔离技术的研究,解决了窄槽刻蚀、多晶硅回填、平整化等技术难题,获得了优化的SOI电路窄沟槽隔离工艺技术条件;岛与岛之间的隔离击穿达到300 V,为下一步研制生产SOI电路打下了坚实的基础.     

A new shallow trench and planar gate MOSFET structure based on VDMOS technology

This paper proposes a new shallow trench and planar gate MOSFET(TPMOS) structure based on VDMOS technology,in which the shallow trench is located at the center of the n~- drift region between the cells under a planar polysilicon gate.Compared with the conventional VDMOS,the proposed TPMOS device not only improves obviously the trade-off relation between on-resistance and breakdown voltage,and reduces the dependence of on-resistance and breakdown voltage on gate length,but also the manufacture process is compatible with that of the VDMOS without a shallow trench,thus the proposed TPMOS can offer more freedom in device design and fabrication.     

Breakdown voltage enhancement of the p-n junction by self-aligneddouble diffusion process through a tapered SiO2 implant mask

The low doping region extension at the edge of the junction curvature is implemented with the self-aligned double diffusion process using a tapered SiO₂ implant mask. The p⁺-p-n diodes fabricated with the proposed double diffusion process have relaxed the surface electric field at the junction curvature and increased the breakdown voltage by 140 V, compared with the cylindrical p-n junction. It is also found that the breakdown voltage of the p⁺ -p-n diodes having the field plate (FP) over the tapered oxide is 500 V, while that of the conventional p-n junction with the FP is 280 V     

The TEOS CVD oxide deposited on phosphorus in situ dopedpolysilicon with rapid thermal annealing

A TEOS oxide deposited on the phosphorus in situ doped polysilicon annealed with RTA is shown to have good electrical characteristics such as a high breakdown field (>12 MV/cm), especially for the positive bias, and a large Qbd (26 Coul/cm²). The improvement is believed to be due to the relatively smooth surface of the in situ doped polysilicon and the reduction of the trapping density by RTA     

Polyoxides grown on n+ polysilicon

The polarity asymmetry on the electrical characteristics of the oxides grown on n⁺ polysilicon (polyoxides) was investigated in terms of the oxidation process, the doping level of the lower polysilicon layer, the oxidation temperature and the oxide thickness. It was found that the thin polyoxide prepared by using a low-temperature wafer loading and N₂ pre-annealing process, has a smoother polyoxide/polysilicon interface and exhibits a lower oxide tunneling current, a higher dielectric breakdown field when the top electrode is positively biased, a lower electron trapping rate and a larger charge-to-breakdown than does the normal polyoxide. The polarity asymmetry is also strongly dependent on the doping level of the lower polysilicon layer, the oxidation temperature and the oxide thickness. It was found that only the thinner polyoxides (⩽240 Å) grown on the heavily-doped polysilicon film (30 Ω/sq) by using the higher-temperature oxidation process (⩾950°C) conduct a less oxide tunneling current when the top electrode is positively biased     

High quality interpoly dielectrics deposited on thenitrided-polysilicon for nonvolatile memory devices

High quality interpoly dielectrics have been fabricated by using NH₃ and N₂O nitridation on polysilicon and deposition of tetra-ethyl-ortho-silicate (TEOS) oxide with N₂O annealing. The surface roughness of polysilicon is improved and the value of weak bonds is reduced due to nitrogen incorporation at the interface, which improves the integrity of interpoly dielectrics. The improvements include a higher barrier height, breakdown strength, and charge-to-breakdown, and a lower leakage current and charge trapping rate than counterparts. It is found that this method can simultaneously improve both charge-to-breakdown (up to 20 C/cm² ) and electric breakdown field (up to 17 MV/cm)     

一种低功耗4H-SiC IGBT的仿真研究

针对传统沟槽栅4H-SiC IGBT关断时间长且关断能量损耗高的问题,文中利用Silvaco TCAD设计并仿真了一种新型沟槽栅4H-SiC IGBT结构。通过在传统沟槽栅4H-SiC IGBT结构基础上进行改进,在N ⁺缓冲层中引入两组高掺杂浓度P区和N区,提高了N ⁺缓冲层施主浓度,折中了器件正向压降与关断能量损耗。在器件关断过程中,N ⁺缓冲层中处于反向偏置状态的PN结对N ^-漂移区中电场分布起到优化作用,加速了N ^-漂移区中电子抽取,在缩短器件关断时间和降低关断能量损耗的同时提升了击穿电压。Silvaco TCAD仿真结果显示,新型沟槽栅4H-SiC IGBT击穿电压为16 kV,在15 kV的耐压设计指标下,关断能量损耗低至4.63 mJ,相比传统结构降低了40.41%。     

Effects of surface pretreatment of polysilicon electrode prior toSi3N4 deposition on the electrical characteristicsof Si3N4 dielectric films

Effects of various surface pretreatments of polysilicon electrode prior to Si₃N₄ deposition on leakage current, time-dependent dielectric breakdown (TDDB) and charge trapping characteristics of thin Si₃N₄ films deposited on rugged and smooth poly-Si are investigated. Surface pretreatments consist of different combinations of HF clean, rapid thermal H₂ -Ar clean, and rapid thermal NH₃-nitridation (RTN) and are intended to modify the surface of bottom poly-Si electrode. Results show that RTN treatments lead to lower leakage current, reduced charge trapping, and superior TDDB characteristics as compared to rapid thermal H₂-Ar clean     

高压槽型SOI LDMOS槽区设计的普适方法

论文介绍了高压SOI槽型LDMOS不同槽介质,槽宽和槽深设计的普适方法。该方法考虑了击穿电压和导通电阻的折中关系。浅而宽的槽适合用高介电常数材料填充,深而窄的槽适合用低介电常数材料填充。论文还讨论了真空槽的情况。仿真结果表明由于器件总宽度的降低,采用低介电常数材料填充槽区可以获得更高的设计优值。     

Characterization of polysilicon oxides thermally grown anddeposited on the polished polysilicon films

This work examines the characteristics of polyoxides thermally grown and deposited on polished polysilicon films. A well-controlled chemical mechanical polishing (CMP) process is also presented to achieve a planar surface morphology for polysilicon films. The thermally-grown and deposited polyoxides on the polished polysilicon films exhibit a lower leakage current, higher dielectric breakdown field, higher electron barrier height, lower electron trapping rate, lower density of trapped charges, and markedly higher charge to breakdown (Q_bd) than the conventional polyoxide. In particular, the deposited polyoxide on the polished polysilicon film has the highest dielectric breakdown field, lowest electron trapping rate, and highest charge to breakdown due to the planar polyoxide/polysilicon interface. In addition, experimental results indicate that the trapped charges of the polished samples are located in the polyoxides' upper portion, which differs from conventional polyoxides. Undoubtedly, the deposited polyoxide on the polished polysilicon film considered herein is the most promising candidate to yield optimum characteristics of polyoxide     

Scaled dielectric antifuse structure for field-programmable gatearray applications

A scaled antifuse structure consisting of a nitride-oxide (NO) dielectric sandwiched between two polysilicon layers is presented. In addition to reducing the effective thickness of the antifuse dielectric, the current conduction asymmetry of the NO layer is also utilized to lower the breakdown voltage to 10.6 V, and consequently the programming voltage to 13.5 V, which is lower than that of previously reported antifuse structures. Time-dependent dielectric breakdown (TDDB) measurements verify that this scaled antifuse structure exhibits a lifetime exceeding ten years (>1×10¹² s) at 5.5 V in the unprogrammed state. Since a significant fraction of the total measured antifuse resistance is contributed by the sheet resistance of the polysilicon electrodes, this structure also demonstrates the reduction of this resistance component through silicidation of both top and bottom electrodes in the area outside of the antifuse. This poly-poly antifuse structure offers reduction in programmed voltage, reduction in silicon device area, simple peripheral circuitry design, and faster circuit operation due to lower capacitance than previous poly-N⁺ antifuse structures