共查询到20条相似文献,搜索用时 12 毫秒
1.
《Electron Devices, IEEE Transactions on》1986,33(2):270-274
The effect of hydrogen implantation on theI(V) characteristics of lateral polysilicon p-n junctions is reported. After implantation with hydrogen and annealing at 400°C, a moderate decrease in the forward current and a large decrease in the reverse current is observed. In addition, the reverse breakdown voltage is increased. Best results were obtained for hydrogen dose of 1016cm-2. The measurements are explained by considering both electric field enhancement of emission and capture rates and the generation of new trap levels by ion implantation. 相似文献
2.
The applicability of shallow-trench-isolation (STI) for CMOS to 50-nm channel widths has been explored. Transistors with channel width to 50 nm and trench width to 200 nm have been fabricated. A comparison of several oxide-filled and polysilicon field-plate-filled STI structures is presented including processing, device performance, and isolation leakage. It is shown that Vth roll off as a function of channel width can be made as small as 65 mV and 145 mV at 100 nm channel width for polysilicon and oxide filled STI, respectively. Off-state currents less than 5×10-12 A/μm and subthreshold slope around 80 mV/dec have been reached. Isolation breakdown voltages are about 8 V. Poly-filled STI effectively reduces channel edge effects, and provides excellent off-state, on-state, and turn-on characteristics all the way to 50-nm channel widths 相似文献
3.
Low-voltage silicon trench power MOSFETs with forward conductivities approaching the silicon limit are reported. Vertical trench power MOSFETs with the measured performances of V DB =55 V (R sp=0.2 mΩ-cm2, k D=5.7 Ω-pF) and V DB=35 V (R sp=0.15 mΩ-cm2, k D =4.3 Ω-PF) were developed where V DB is the drain-source avalanche breakdown voltage, R sp is the specific on-state resistance, and k D=R spC sp is the input device technology factor where C sp is the specific MOS gate input capacitance. The optimum device performance resulted from an advanced trench processing technology that included (1) an improved RIE process to define scaled vertical silicon trenches, (2) silicon trench sidewall cleaning to reduce the surface damage, and (3) a novel polysilicon gate planarization technique using a sequential oxidation/oxide etchback, process. The measured performances are shown to be in excellent agreement with the two-dimensional device simulations and the calculated results obtained from an analytical model 相似文献
4.
Negoro Y. Miyamoto N. Kimoto T. Matsunami H. 《Electron Devices, IEEE Transactions on》2002,49(9):1505-1510
Characteristics of p-n junction fabricated by aluminum-ion (Al+) or boron-ion (B+) implantation and high-dose Al+-implantation into 4H-SiC (0001) have been investigated. By the combination of high-dose (4×1015 cm-2) Al+ implantation at 500°C and subsequent annealing at 1700°C, a minimum sheet resistance of 3.6 kΩ/□ (p-type) has been obtained. Three types of diodes with planar structure were fabricated by employing Al+ or B+ implantation. B +-implanted diodes have shown higher breakdown voltages than Al+-implanted diodes. A SiC p-n diode fabricated by deep B+ implantation has exhibited a high breakdown voltage of 2900 V with a low on-resistance of 8.0 mΩcm2 at room temperature. The diodes fabricated in this study showed positive temperature coefficients of breakdown voltage, meaning avalanche breakdown. The avalanche breakdown is discussed with observation of luminescence 相似文献
5.
本文基于VDMOS技术提出了一种浅沟槽平面栅MOSFET(TPMOS)新结构,其中浅沟槽位于VDMOS多晶硅平面栅下方n-漂移区的两元胞中央。与传统的VDMOS结构相比,新结构不仅可以显著改善器件的导通电阻(RON)和击穿电压(VBR),减小它们对栅极长度的依赖,而且除浅沟槽外,制作工艺与VDMOS完全兼容。采用TPMOS结构可为器件设计和制造提供更大的自由度。 相似文献
6.
Uemoto Y. Fujii E. Emoto F. Nakamura A. Senda K. 《Electron Devices, IEEE Transactions on》1991,38(1):95-100
An approach is proposed for obtaining a high-voltage thin-film transistor (TFT) with multigate structure where polysilicon TFTs are connected in series. A basic principle for high-voltage operation has been investigated in detail through calculations based on a model describing log I DS-VGS characteristics observed in a single-gate polysilicon TFT. It has been found that off-state (V GS<0) operation of the polysilicon TFT causes a large increase of breakdown voltage of the multigate TFT with the result that a nearly equal fraction of drain voltage is applied across the region around each elemental TFT. The breakdown voltage of drain of the fabricated multigate TFT which has five elemental TFTs has been elevated up to 80 V 相似文献
7.
为增强器件的反向耐压能力,降低器件的漏电功耗,采用Silvaco TCAD对沟槽底部具有SiO2间隔的结势垒肖特基二极管(TSOB)的器件特性进行了仿真研究。通过优化参数来改善导通压降(VF)-反向漏电流(IR)和击穿电压的折衷关系。室温下,沟槽深度为2.2 μm时,器件的击穿电压达到1 610 V。正向导通压降为2.1 V,在VF=3 V时正向电流密度为199 A/cm2。为进一步改善器件的反向阻断特性,在P型多晶硅掺杂的有源区生成一层SiO2来优化漂移区电场分布,此时改善的器件结构在维持正向导通压降2.1 V的前提下,击穿电压达到1 821 V,增加了13%。在1 000 V反向偏置电压下,反向漏电流密度比普通结构降低了87%,有效降低了器件的漏电功耗。普通器件结构的开/关电流比为2.6×103(1 V/-500 V),而改善的结构为1.3×104(1 V/-500 V)。 相似文献
8.
《Electron Devices, IEEE Transactions on》2008,55(9):2417-2422
9.
Yamaguchi T. Yu Y.-C.S. Lane E.E. Lee J.S. Patton E.E. Herman R.D. Ahrendt D.R. Drobny V.F. Yuzuriha T.H. Garuts V.E. 《Electron Devices, IEEE Transactions on》1988,35(8):1247-1256
Use of boron and arsenic diffusions through an emitter polysilicon film (borosenic-poly emitter-base process) produces a transistor base width of less than 100nm with an emitter junction depth of 50 nm and an emitter-to-base reverse leakage current of approximately 70 pA. The borosenic-poly process resolves both the channeling and shadowing effects of a sidewall-oxided spacer during the base boron implantation. The process also minimizes crystal defects generated during the emitter and base implantations. The coupling-base boron implant significantly improves a wide variation in the emitter-to-collector periphery punchthrough voltage without degrading the emitter-to-base breakdown voltage current gain, cutoff frequency, or ECL gate delay time. A deep trench isolation with 4-μm depth and 1.2-μm width reduces the collector-to-substrate capacitance to 9 fF, while maintaining a transistor-to-transistor isolation voltage of greater than 25 V. The application of self-aligned titanium silicide technology to form polysilicon resistors without holes and to reduce the sheet resistance of the emitter and collector polysilicon electrodes to 1 Ω/square is discussed 相似文献
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11.
This paper proposes a new shallow trench and planar gate MOSFET(TPMOS) structure based on VDMOS technology,in which the shallow trench is located at the center of the n~- drift region between the cells under a planar polysilicon gate.Compared with the conventional VDMOS,the proposed TPMOS device not only improves obviously the trade-off relation between on-resistance and breakdown voltage,and reduces the dependence of on-resistance and breakdown voltage on gate length,but also the manufacture process is compatible with that of the VDMOS without a shallow trench,thus the proposed TPMOS can offer more freedom in device design and fabrication. 相似文献
12.
Han-Soo Kim Seong-Dong Kim Min-Koo Han Seok-Nam Yoon Yearn-Ik Choi 《Electron Device Letters, IEEE》1995,16(9):405-407
The low doping region extension at the edge of the junction curvature is implemented with the self-aligned double diffusion process using a tapered SiO2 implant mask. The p+-p-n diodes fabricated with the proposed double diffusion process have relaxed the surface electric field at the junction curvature and increased the breakdown voltage by 140 V, compared with the cylindrical p-n junction. It is also found that the breakdown voltage of the p+ -p-n diodes having the field plate (FP) over the tapered oxide is 500 V, while that of the conventional p-n junction with the FP is 280 V 相似文献
13.
Chyuan Haur Kao Chao Sung Lai Chung Len Lee 《Electron Device Letters, IEEE》1997,18(11):526-528
A TEOS oxide deposited on the phosphorus in situ doped polysilicon annealed with RTA is shown to have good electrical characteristics such as a high breakdown field (>12 MV/cm), especially for the positive bias, and a large Qbd (26 Coul/cm2). The improvement is believed to be due to the relatively smooth surface of the in situ doped polysilicon and the reduction of the trapping density by RTA 相似文献
14.
Shye Lin Wu Chun Yuan Chen Ta Yow Lin Chung Len Lee Tan Fu Lei Mong Song Liang 《Electron Devices, IEEE Transactions on》1997,44(1):153-159
The polarity asymmetry on the electrical characteristics of the oxides grown on n+ polysilicon (polyoxides) was investigated in terms of the oxidation process, the doping level of the lower polysilicon layer, the oxidation temperature and the oxide thickness. It was found that the thin polyoxide prepared by using a low-temperature wafer loading and N2 pre-annealing process, has a smoother polyoxide/polysilicon interface and exhibits a lower oxide tunneling current, a higher dielectric breakdown field when the top electrode is positively biased, a lower electron trapping rate and a larger charge-to-breakdown than does the normal polyoxide. The polarity asymmetry is also strongly dependent on the doping level of the lower polysilicon layer, the oxidation temperature and the oxide thickness. It was found that only the thinner polyoxides (⩽240 Å) grown on the heavily-doped polysilicon film (30 Ω/sq) by using the higher-temperature oxidation process (⩾950°C) conduct a less oxide tunneling current when the top electrode is positively biased 相似文献
15.
Wen Luh Yang Tien Sheng Chao Chun-Ming Cheng Tung Ming Pan Tan Fu Lei 《Electron Devices, IEEE Transactions on》2001,48(7):1304-1309
High quality interpoly dielectrics have been fabricated by using NH3 and N2O nitridation on polysilicon and deposition of tetra-ethyl-ortho-silicate (TEOS) oxide with N2O annealing. The surface roughness of polysilicon is improved and the value of weak bonds is reduced due to nitrogen incorporation at the interface, which improves the integrity of interpoly dielectrics. The improvements include a higher barrier height, breakdown strength, and charge-to-breakdown, and a lower leakage current and charge trapping rate than counterparts. It is found that this method can simultaneously improve both charge-to-breakdown (up to 20 C/cm2 ) and electric breakdown field (up to 17 MV/cm) 相似文献
16.
针对传统沟槽栅4H-SiC IGBT关断时间长且关断能量损耗高的问题,文中利用Silvaco TCAD设计并仿真了一种新型沟槽栅4H-SiC IGBT结构。通过在传统沟槽栅4H-SiC IGBT结构基础上进行改进,在N +缓冲层中引入两组高掺杂浓度P区和N区,提高了N +缓冲层施主浓度,折中了器件正向压降与关断能量损耗。在器件关断过程中,N +缓冲层中处于反向偏置状态的PN结对N -漂移区中电场分布起到优化作用,加速了N -漂移区中电子抽取,在缩短器件关断时间和降低关断能量损耗的同时提升了击穿电压。Silvaco TCAD仿真结果显示,新型沟槽栅4H-SiC IGBT击穿电压为16 kV,在15 kV的耐压设计指标下,关断能量损耗低至4.63 mJ,相比传统结构降低了40.41%。 相似文献
17.
Yoon G.W. Joshi A.B. Kwong D.L. Mathews V.K. Thakur R.P.S. Fazan P.C. 《Electron Devices, IEEE Transactions on》1994,41(3):347-351
Effects of various surface pretreatments of polysilicon electrode prior to Si3N4 deposition on leakage current, time-dependent dielectric breakdown (TDDB) and charge trapping characteristics of thin Si3N4 films deposited on rugged and smooth poly-Si are investigated. Surface pretreatments consist of different combinations of HF clean, rapid thermal H2 -Ar clean, and rapid thermal NH3-nitridation (RTN) and are intended to modify the surface of bottom poly-Si electrode. Results show that RTN treatments lead to lower leakage current, reduced charge trapping, and superior TDDB characteristics as compared to rapid thermal H2-Ar clean 相似文献
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19.
Tan Fu Lei Juing-Yi Cheng Shyh Yin Shiau Tien Sheng Chao Chao Sung Lai 《Electron Devices, IEEE Transactions on》1998,45(4):912-917
This work examines the characteristics of polyoxides thermally grown and deposited on polished polysilicon films. A well-controlled chemical mechanical polishing (CMP) process is also presented to achieve a planar surface morphology for polysilicon films. The thermally-grown and deposited polyoxides on the polished polysilicon films exhibit a lower leakage current, higher dielectric breakdown field, higher electron barrier height, lower electron trapping rate, lower density of trapped charges, and markedly higher charge to breakdown (Qbd) than the conventional polyoxide. In particular, the deposited polyoxide on the polished polysilicon film has the highest dielectric breakdown field, lowest electron trapping rate, and highest charge to breakdown due to the planar polyoxide/polysilicon interface. In addition, experimental results indicate that the trapped charges of the polished samples are located in the polyoxides' upper portion, which differs from conventional polyoxides. Undoubtedly, the deposited polyoxide on the polished polysilicon film considered herein is the most promising candidate to yield optimum characteristics of polyoxide 相似文献
20.
Liu D.K.Y. Chen K. Tigelaar H. Paterson J. Chen S.O. 《Electron Device Letters, IEEE》1991,12(4):151-153
A scaled antifuse structure consisting of a nitride-oxide (NO) dielectric sandwiched between two polysilicon layers is presented. In addition to reducing the effective thickness of the antifuse dielectric, the current conduction asymmetry of the NO layer is also utilized to lower the breakdown voltage to 10.6 V, and consequently the programming voltage to 13.5 V, which is lower than that of previously reported antifuse structures. Time-dependent dielectric breakdown (TDDB) measurements verify that this scaled antifuse structure exhibits a lifetime exceeding ten years (>1×1012 s) at 5.5 V in the unprogrammed state. Since a significant fraction of the total measured antifuse resistance is contributed by the sheet resistance of the polysilicon electrodes, this structure also demonstrates the reduction of this resistance component through silicidation of both top and bottom electrodes in the area outside of the antifuse. This poly-poly antifuse structure offers reduction in programmed voltage, reduction in silicon device area, simple peripheral circuitry design, and faster circuit operation due to lower capacitance than previous poly-N+ antifuse structures 相似文献