A 1.2-V 1.5-Gb/s 72-Mb DDR3 SRAM

A 1.2-V 72-Mb double data rate 3 (DDR3) SRAM achieves a data rate of 1.5 Gb/s using dynamic self-resetting circuits. Single-ended main data lines halve the data line precharging power dissipation and the number of data lines. Clocks phase shifted by 0/spl deg/, 90/spl deg/, and 270/spl deg/ are generated through the proposed clock adjustment circuits. The latter circuits make input data sampled with an optimized setup/hold window. On-chip input termination with a linearity error of /spl plusmn/4.1% is developed to improve signal integrity at higher data rates. A 1.2-V 1.5-Gb/s 72-Mb DDR3 SRAM is fabricated in a 0.10-/spl mu/m CMOS process with five metals. The cell size and the chip size are 0.845 /spl mu/m/sup 2/ and 151.1 mm/sup 2/, respectively.     

Mixed body bias techniques with fixed V/sub t/ and I/sub ds/ generation circuits

There remains a need to improve sub-1-V CMOS VLSIs with respect to variation in transistor behavior. In this paper, to minimize variation in delay and the noise margin of the circuits in processors, we propose several mixed body bias techniques using body bias generation circuits. In these circuits, either the saturation region of the current between source and drain (I/sub ds/) or the threshold voltage (V/sub t/) of PMOS/NMOS is permanently fixed, regardless of temperature range or variation in process. A test chip that featured these body bias generation circuits was fabricated using a 130-nm CMOS process with a triple-well structure. The mixed body bias techniques which keep the I/sub ds/ of the MOS in the decoder and I/O circuits of a register file fixed and maintain the V/sub t/ of the MOS in both the memory cell and domino circuits of the register file fixed resulted in positive temperature dependence of delay from -40 /spl deg/C to 125 /spl deg/C, 85% reduction of the delay variation compared with normal body bias (NBB) at V/sub DD/ = 0.8 V. In addition, the results using these techniques show a 100-mV improvement in lower operating voltage compared with NBB at -40 /spl deg/C on a 4-kb SRAM.     

New miniature 15-20-GHz continuous-phase/amplitude control MMICs using 0.18-/spl mu/m CMOS technology

The design and performance of two new miniature 360/spl deg/ continuous-phase-control monolithic microwave integrated circuits (MMICs) using the vector sum method are presented. Both are implemented using commercial 0.18-/spl mu/m CMOS process. The first phase shifter demonstrates all continuous phase and an insertion loss of 8 dB with a 37-dB dynamic range from 15 to 20 GHz. The chip size is 0.95 mm /spl times/ 0.76 mm. The second phase shifter can achieve all continuous phase and an insertion loss of 16.2 dB with a 38.8-dB dynamic range at the same frequency range. The chip size is 0.71 mm /spl times/ 0.82 mm. To the best of the authors' knowledge, these circuits are the first demonstration of microwave CMOS phase shifters using the vector sum method with the smallest chip size for all MMIC phase shifters with 360/spl deg/ phase-control range above 5 GHz reported to date.     

A 14-bit high-temperature /spl Sigma//spl Delta/ modulator in standard CMOS

Experimental verification is given for the use of /spl Sigma//spl Delta/ modulation for high-temperature applications (/spl ges/approximately 150/spl deg/C) in a standard CMOS process. Switched-capacitor circuits are used to implement a second-order single-stage and a third-order 2-1 MASH /spl Sigma//spl Delta/ modulator with single-bit quantization. The two modulators have an oversampling ratio of 256 with an input signal bandwidth of 500 Hz. The modulators were fabricated in a 1.5-/spl mu/m standard CMOS technology. A fully differential signal path and near minimum sized switches are used to mitigate the effect of large junction-to-substrate leakage current present at high temperatures. Experimental results show both modulators are capable of over 14 bits of resolution at 225/spl deg/C and over 13 bits of resolution at 255/spl deg/C. Results show that the single-stage modulator is more resistant to high-temperature circuit impairment than is the MASH cascaded structure.     

Subharmonically pumped CMOS frequency conversion (up and down) circuits for 2-GHz WCDMA direct-conversion transceiver

Subharmonically pumped frequency down- and upconversion circuits are implemented in 0.18-/spl mu/m mixed-mode CMOS technology for 2-GHz direct-conversion WCDMA transceiver applications. These circuits operate in quadrature double-balanced mode and a required octet-phases (0/spl deg/, 45/spl deg/, 90/spl deg/, 135/spl deg/, 180/spl deg/, 225/spl deg/, 270/spl deg/, and 315/spl deg/) local oscillator (LO) signal comes from an active multiphases LO generator composed of a polyphase filter and active 45/spl deg/ phase shifting circuits. For linearity improvement, predistortion compensation and negative feedback schemes are used in the frequency down- and upconversion circuits, respectively. The downconverter achieves a conversion voltage gain of 20 dB (to 1-M/spl Omega/ load), 4-dBm IIP3 (18-dBm OIP3 to 50-/spl Omega/ load), 41-dBm IIP2 and 8.5-dB DSB NF at 1-MHz IF frequency, consuming 13.4 mA from 1.8-V supply, in the WCDMA Rx band (2110-2170 MHz). The upconverter, operating as two switched gain modes in the WCDMA Tx band (1920-1980 MHz), consumes 19.4 mA from 1.8-V supply and shows 14.5-dB conversion power gain, 15 -dBm OIP3 (0.5-dBm IIP3) and -11 dBm P/sub 1dB/ at maximum gain mode. At minimum gain mode, it realizes -0.3-dB conversion loss, 10.7-dBm OIP3 (11-dBm IIP3) and 0-dBm P/sub 1dB/, respectively. 3GPP WCDMA modulation tests are performed for both up- and downconversion circuits and the results are discussed in this paper.     

A 0.18-/spl mu/m CMOS offset-PLL upconversion modulation loop IC for DCS1800 transmitter

A DCS1800 offset-phase-locked-loop upconversion modulation loop integrated circuit (IC) fabricated in a 0.18-/spl mu/m CMOS technology is presented in this paper. This IC operates at 2.8-V supply voltage with a current consumption of 36 mA. The measured root-mean-square and peak phase errors of the Gaussian minimum shift keying (GMSK) transmission signal are 1.6/spl deg/ and 4/spl deg/, respectively. It is shown that such circuits can be implemented in CMOS process with current dissipation and performance comparable to BiCMOS chips. Advantages of upconversion modulation loop and design issues of I/Q modulators are also described.     

A monolithic 10-bit A/D using I/SUP 2/L and LWT thin-film resistors

Describes the function, circuit details, and performance of a monolithic 10-bit A/D converter. The converter is a successive approximation type using linear compatible I/SUP 2/L for the SAR. The converter is completely self-contained, including both clock and voltage reference. Biasing is arranged to take advantage of naturally occurring interfaces in the circuitry, simplifying the overall circuit in comparison to discrete or hybrid approaches. The processing also includes on-chip thin-film resistors which are laser-wafer-trimmed (LWR) for overall accuracy and temperature stability. The finished circuits operate with no missing codes over the -55/spl deg/ to +125/spl deg/C temperature range.     

A new compact temperature-compensated CMOS current reference

This paper describes a new circuit integrated on silicon, which generates temperature-independent bias currents. Such a circuit is firstly employed to obtain a current reference with first-order temperature compensation, then it is modified to obtain second-order temperature compensation. The operation principle of the new circuits is described and the relationships between design and technology process parameters are derived. These circuits have been designed by a 0.35 /spl mu/m BiCMOS technology process and the thermal drift of the reference current has been evaluated by computer simulations. They show good thermal performance and in particular, the new second-order temperature-compensated current reference has a mean temperature drift of only 28 ppm//spl deg/C in the temperature range between -30/spl deg/C and 100/spl deg/C.     

A Programmable Surface Acoustic Wave Matched Filter for Phase-Coded Spread Spectrum Waveforms (Short Papers)

A programmable surface acoustic wave (SAW) matched filter for biphase-coded spread spectrum waveforms has been constructed using a temperature-stable ST-cut quartz tapped delay line (TDL) and silicon-on-sapphire integrated control circuits. Construction is hybrid with wire stitch bond interconnections between the acoustic and microelectronic portions of the device. The SAW TDL operates at 120-MHz center frequency with 100-ns spacing between adjacent taps for a 10-MHz chip rate. The output of each tap can be individually switched to a load with 0 or 180/spl deg/ phase shift by the silicon-on-sapphire integrated control circuits. The high-speed capability of silicon-on-sapphire integrated circuits allows programming (code changing) to be achieved with a serial data input at 10-MHz rates, while the low temperature coefficient of ST-cut quartz allows satisfactory operation over a wide temperature range (-25/spl deg/C to +85/spl deg/C).     

5-GHz 32-bit integer execution core in 130-nm dual-V/sub T/ CMOS

A 32-bit integer execution core containing a Han-Carlson arithmetic-logic unit (ALU), an 8-entry /spl times/ 2 ALU instruction scheduler loop and a 32-entry /spl times/ 32-bit register file is described. In a 130 nm six-metal, dual-V/sub T/ CMOS technology, the 2.3 mm/sup 2/ prototype contains 160 K transistors. Measurements demonstrate capability for 5-GHz single-cycle integer execution at 25/spl deg/C. The single-ended, leakage-tolerant dynamic scheme used in the ALU and scheduler enables up to 9-wide ORs with 23% critical path speed improvement and 40% active leakage power reduction when compared to a conventional Kogge-Stone implementation. On-chip body-bias circuits provide additional performance improvement or leakage tolerance. Stack node preconditioning improves ALU performance by 10%. At 5 GHz, ALU power is 95 mW at 0.95 V and the register file consumes 172 mW at 1.37 V. The ALU performance is scalable to 6.5 GHz at 1.1 V and to 10 GHz at 1.7 V, 25/spl deg/C.     

Second generation I/SUP 2/L/MTL: a 20 ns process/structure

A high performance, second generation I/SUP 2/L/MTL gate for digital LSI applications with TTL compatibility has successfully been designed, characterized, and demonstrated fully functional over a wide current range and the military temperature range of -55 to 125/spl deg/C. Performance is measured using an in-line five-collector gate having one end injector. The gate performed with the following characteristics at 100 /spl mu/A injector current: /spl beta//SUB U//SUP eff//spl ges/4 for all collectors at 25/spl deg/C and /spl ges/2.5 at -55/spl deg/C, /spl alpha//SUB rec///spl alpha//SUB F//spl cong/0.58 and /spl tau/~/SUB d/=18-20 ns from -55 to 125/spl deg/C, and a speed-power product of 1.4 pJ at 25/spl deg/C. At low injector currents, a constant speed-power product of 0.36 pJ at 25/spl deg/ was obtained.     

Green's Functions For Triangular Segments In Planar Microwave Circuits

Green's functions are developed for the analysis of triangular segments in microwave planer circuits. Three types of triangles (30/spl deg/-60/spl deg/ right-angle, equilateral and isosceles right-angled) are treated by placing additional image sources outside the triangular region.     

Stability of amorphous-silicon TFTs deposited on clear plastic substrates at 250/spl deg/C to 280/spl deg/ C

Amorphous-silicon (a-Si) thin-film transistors (TFTs) were fabricated on a free-standing new clear plastic substrate with high glass transition temperature (T/sub g/) of >315/spl deg/ C and low coefficient of thermal expansion of <10 ppm/ /spl deg/ C. Maximum process temperatures on the substrates were 250/spl deg/C and 280/spl deg/C, close to the temperatures used in industrial a-Si TFT production on glass substrates. The first TFTs made at 280/spl deg/C have dc characteristics comparable to TFTs made on glass. The stability of the 250/spl deg/C TFTs on clear plastic is approaching that of TFTs made on glass at 300/spl deg/C-350/spl deg/C. TFT characteristics and stability depend only on process temperature and not on substrate type.     

Al/sub 0.10/Ga/sub 0.90/As-GaAs microcoolers

GaAs-based microcoolers were fabricated and tested. An Al/sub 0.10/Ga/sub 0.90/As layer grown on GaAs, having a lower thermal conductivity and comparable electrical conductivity to that of the substrate, was employed in the microcooler structure to reduce the heat conduction back from the heat sink. Maximum cooling temperatures of 0.87 /spl deg/C and 2.3 /spl deg/C were obtained at ambient temperatures of 25 /spl deg/C and 100 /spl deg/C, respectively, from 60 /spl times/ 60 /spl mu/m microcoolers.     

W-band CPW RF MEMS circuits on quartz substrates

This paper presents W-band coplanar waveguide RF microelectromechanical system (MEMS) capacitive shunt switches with very low insertion loss (-0.2 to -0.5 dB) and high-isolation (/spl les/ -30 dB) over the entire W-band frequency range. It is shown that full-wave electromagnetic modeling using Sonnet can predict the performance of RF MEMS switches up to 120 GHz. Also presented are W-band 0/spl deg//90/spl deg/ and 0/spl deg//180/spl deg/ switched-line phase shifters with very good insertion loss (1.75 dB/bit at 90 GHz) and a wide bandwidth of operation (75-100 GHz). These circuits are the first demonstration of RF MEMS digital-type phase shifters at W-band frequencies and they outperform their solid-state counterparts by a large margin.     

Design of Digital Loaded-Line Phase-Shift Networks for Microwave Thin-Film Applications

This paper describes the design approach, fabrication techniques, and electrical performance for two types of microwave hybrid thin-film phase shifters. Emphasis is placed on the practical aspects of the overall design and fabrication. A simplified set of design equations for loaded-line phase-shift networks is presented and divided into three categories based on the type of loading employed. The two circuits presented are a 4-bit 90/spl deg/ network employing single-section multibits to minimize physical size, and a 4-bit 360/spl deg/ network employing the 45/spl deg/ section as a basic building block.     

Design of Digital Loaded-Line Phase-Shift Networks for Microwave Thin-Film Applications

This paper describes the design approach, fabrication techniques, and electrical performance for two types of microwave hybrid thin-film phase shifters. Emphasisis placed on the practical aspects of the overall design and fabrication. A simplified set of design equations for loaded-line phase-shift networks is presented and divided into three categories based on the type of loading employed. The two circuits presented are a 4-bit 90 /spl deg/ network employing single-section multibits to minimize physical size, and a 4-bit 360 /spl deg/ network employing the 45 /spl deg/ section as a basic building block.     

Microwave Circuits for High-Efficiency Operation of Transferred Electron Oscillators

Compact circuits for obtaining high-efficiency operation of high-power transferred electron oscillators (TEOs) in L-band are described. One is a coaxial resonator and the other employs coupled TEM lines. The circuits are shown analytically and experimentally to be capable of matching a wide range of fundamental device impedances. Provisions for independently tuning the second-harmonic impedance over a wide range are included in both types of circuits. Pulsed conversion efficiencies up to 32 percent have been obtained TEOs mounted in the coaxial resonators and up to 27 percent with TEOs in the coupled TEM-line structures. The impedance at the second harmonic has been shown quantitatively to be extremely important in controlling device efficiency. By varying the second-harmonic tuning the device performance can be varied from high-efficiency operation to no output. Oscillators using these cavities were temperature stable over a wide range. The operating frequency of TEOs in the coaxial cavity and the coupled-TEM-line cavity varied less than 30 and 40 kHz//spl deg/C, respectively, over the range from - 54/spl deg/C to +125/spl deg/C.     

A micropower logarithmic A/D with offset and temperature compensation

Logarithmic circuits are useful in many applications that require nonlinear signal compression, such as in speech recognition front-ends (SRFEs) and cochlear implants or bionic ears (BEs). A logarithmic current-input analog-to-digital converter (A/D) with temperature compensation and automatic offset calibration is presented in this paper. It employs a diode to compute the logarithm, a wide linear range transconductor to perform voltage-to-current conversion, and a dual-slope auto- zeroing topology with 60 dB of dynamic range for sampling the envelope of speech signals. The temperature dependence of the logarithm inherent in a diode implementation is automatically cancelled in our circuit topology. Experimental results from a 1.5-/spl mu/m 3-V BiCMOS process show that the converter achieves a temperature stability lower than 150 ppm//spl deg/C from 12/spl deg/C to 42/spl deg/C, and consumes only 3 /spl mu/W of power when sampling at 300 Hz. At this level of power consumption, we show that the design is thermal-noise limited to 8 bits of precision. This level of precision is more than adequate for deaf patients and for speech recognition front-ends. The power consumption is almost two orders of magnitude lower than state-of-the-art DSP implementations, and the use of a local feedback topology achieves a 2.5-bit improvement over conventional dual-slope designs.     

Complementary metal-oxide-semiconductor thin-film transistor circuits from a high-temperature polycrystalline silicon process on steel foil substrates

We fabricated CMOS circuits from polycrystalline silicon films on steel foil substrates at process temperatures up to 950/spl deg/C. The substrates were 0.2-mm thick steel foil coated with 0.5-/spl mu/m thick SiO/sub 2/. We employed silicon crystallization times ranging from 6 h (600/spl deg/C) to 20 s (950/spl deg/C). Thin-film transistors (TFTs) were made in either self-aligned or nonself-aligned geometries. The gate dielectric was SiO/sub 2/ made by thermal oxidation or from deposited SiO/sub 2/. The field-effect mobilities reach 64 cm/sup 2//Vs for electrons and 22 cm/sup 2//Vs for holes. Complementary metal-oxide-silicon (CMOS) circuits were fabricated with self-aligned TFT geometries, and exhibit ring oscillator frequencies of 1 MHz. These results lay the groundwork for polycrystalline silicon circuitry on flexible substrates for large-area electronic backplanes.