电火花加工半导体靶材料工艺探索

介绍了用电火花成形机在半导体硅片上开展加工孔和槽的研究情况 ,并对硅片的固定、电极的材料和电加工参数进行了探索     

硅片电火花线切割加工技术的发展

利用电火花线切割加工技术加工硅片能直接得到大尺寸、超薄硅片,且不受硅晶体晶向的影响,设备成本低,切割效率较高,因而研究和开发硅片电火花线切割加工技术是一个很有发展潜力和应用前景的课题。     

大直径硅片超精密磨削技术的研究与应用现状

随着IC制造技术的飞速发展，为了增加IC芯片产量和降低单元制造成本，硅片趋向大直径化，原始硅片的厚度也相应增大以保证大尺寸硅片的强度；与此相反，为了满足IC封装的要求，芯片的厚度却不断减小，需要对图形硅片进行背面减薄。硅片和芯片尺寸变化所导致的硅片加工量的增加以及对硅片加工精度和表面质量更高的要求，使已有的硅片加工技术面临严峻的挑战。本文详细分析了传统硅片加工工艺的局限性，介绍了几种大直径硅片超精密磨削加工工艺的原理和特点，评述了国内外硅片超精密磨削技术与装备研究和应用的现状及发展方向，强调了我国开展大直径硅片超精密磨削技术和装备研究的必要性。     

硅片化学机械抛光技术的研究进展

随着硅片厚度的增大和芯片厚度的减小,硅片在加工中的材料去除量增大,如何提高其加工效率就成了研究的热点之一。由于化学机械抛光过程复杂,抛光后硅片的质量受到多种因素的影响,主要包括抛光设备的技术参数、耗材(抛光垫和抛光液)的性质和硅片自身在抛光时的接触应力状态等。本文介绍了硅片化学机械抛光技术的研究进展,讨论了影响硅片抛光后表面质量和表面材料去除率的因素,如抛光液、抛光垫、抛光压力等,并对目前用于硅片化学机械抛光的先进设备进行了综述。      

半导体用高纯钨靶材的制备技术与应用

难熔金属钨及钨合金由于具有高温稳定性好、电子迁移抗力高以及电子发射系数高等优点,在半导体大规模集成电路制造过程中有着广泛的应用。本文对半导体用高纯钨及钨合金靶材的应用领域、性能要求以及制备方法进行了详细的分析,并对其发展趋势进行了展望。高纯钨及钨合金靶材主要用于制造半导体集成电路的栅电极、连接布线、扩散阻挡层等,对材料的纯度、杂质元素含量、致密度、晶粒尺寸及晶粒组织均匀性等方面都有着极高的要求。高纯钨及钨合金靶材主要采用热压、热等静压等方式来制备,采用中频烧结+压力加工的方式可以制备出高纯度、高致密度的钨靶材,但晶粒尺寸及晶粒组织均匀性控制方面,与热等静压制备的钨靶仍有一定的差距。     

中国铝板带产业发展状况

简述了近年来中国铝板带产业产能、产量、进出口量、关键经营指标、技术装备水平、龙头企业发展等产业运行情况.分析了中国铝板带产业具备的优势与存在的问题,面临的机遇与挑战,并提出了今后发展建议.     

Fine grinding of silicon wafers

Silicon wafers are used for the production of most microchips. Various processes are needed to transfer a silicon crystal ingot into wafers. As one of such processes, surface grinding of silicon wafers has attracted attention among various investigators and a limited number of articles can be found in the literature. However, no published articles are available regarding fine grinding of silicon wafers. In this paper, the uniqueness and the special requirements of the silicon wafer fine grinding process are introduced first. Then some experimental results on the fine grinding of silicon wafers are presented and discussed. Tests on different grinding wheels demonstrate the importance of choosing the correct wheel and an illustration of the proper selection of process parameters is included. Also discussed are the effects of the nozzle position and the flow rate of the grinding coolant.     

Mechano-chemical polishing of silicon wafers

Rapid progress in recent IC fabrication industry has increased the demand of tight specification of non-uniformity (NU) and surface polishing in silicon wafer planarization. Chemical–mechanical polishing (CMP) is currently the most popular method for IC wafer planarization. However, the sub-surface damage problem caused by hard abrasives and chemical waste problem of CMP have decreased the throughput and increased the cost of IC fabrication. This study is to investigate the mechano-chemical polishing (MCP) of silicon wafers by slurry of soft abrasives, BaCO₃ and through experiments to verify that the solid phase chemical reaction (SPCR) is the main reaction process involved in MCP. A planarization mechanism with compliance has been designed and tested through MCP experiments. Experimental results of MCP of silicon wafers have achieved the average of surface roughness improvement ratio (SRIR) to 99% and the surface roughness R_a=0.633 nm measured by atomic force microscope (AFM). The material removal rate (MRR) has been calculated and the significant influence of slurry weight percent and polishing pressure have been found. The NU has also been estimated for evaluation of MCP parameters. The sub-surface damage of silicon wafer has not yet been found in experimental results and hence the MCP process of silicon wafers has been verified to become a green or environment-friendly technology of silicon wafer planarization.     

硅产业发展现状分析

近年来光伏产业的迅猛崛起,推动了硅产业的加速发展,硅产品经历了从供不应求到产能过剩的巨变。本文以工业硅、有机硅、多晶硅和单晶硅四种典型硅产品的生产、市场供需、企业运营状况等方面详细分析了国内外硅产业发展现状,对比分析了发达国家和中国硅产业的特点,论述了我国硅产业发展中存在的问题。     

Surface damage in wire-cut silicon wafers

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Grinding induced subsurface cracks in silicon wafers

Silicon wafers are used for production of most microchips. Various processes are needed to transfer a silicon crystal ingot into wafers. To ensure high surface quality, the damage layer generated by each of the machining processes (such as lapping and grinding) has to be removed by its subsequent processes. Therefore it is essential to assess the subsurface damage for each machining process. This paper presents the observation of subsurface cracks in silicon wafers machined by surface grinding process. Based on cross-sectional microscopy methods, several crack configurations are identified. Samples taken from different locations on the wafers are examined to investigate the effects of sample location on crack depth. The effects of grinding parameters such as feedrate and wheel rotational speed on the depth of subsurface crack have been studied by a set of factorial design experiments. Furthermore, the relation between the depth of subsurface crack and the wheel grit size is experimentally determined.     

Microbridge testing of silicon oxide/silicon nitride bilayer films deposited on silicon wafers

The present work further develops the microbridge testing method to characterize mechanical properties of bilayer thin films. We model the substrate deformation with three coupled springs and consider residual stress in each layer to formulate deflection versus load under large deformation, resulting in a closed-form formula. If the mechanical properties of one layer are available, the closed formula is able to simultaneously evaluate the Young's modulus and residual stress of the other layer, and the bending strength of the bilayer films from the microbridge test. The analytic results are confirmed by finite element calculations. Using a load and displacement sensing nanoindenter system equipped with a microwedge probe, we conduct microbridge tests on low-temperature silicon oxide/silicon nitride bilayer films prepared by the microelectromechanical technique. The experimental results verify the proposed method, yielding the Young's modulus of 41.00±3.60 GPa, the residual stress of −180.88±7.90 MPa and the bending strength of 0.903±0.111 GPa for the low-temperature silicon oxide films.     

Fine grinding of silicon wafers: designed experiments

Silicon wafers are the most widely used substrates for semiconductors. The falling price of silicon wafers has created tremendous pressure to develop cost-effective processes to manufacture silicon wafers. Fine grinding possesses great potential to reduce the overall cost for manufacturing silicon wafers. The uniqueness and the special requirements of fine grinding have been discussed in a paper published earlier in this journal. As a follow-up, this paper presents the results of a designed experimental investigation into fine grinding of silicon wafers. In this investigation, a three-variable two-level full factorial design is employed to reveal the main effects as well as the interaction effects of three process parameters (wheel rotational speed, chuck rotational speed and feed-rate). The process outputs studied include grinding force, spindle motor current, cycle time, surface roughness and grinding marks.     

Edge chipping of silicon wafers in diamond grinding

Although diamond grinding is the most commonly used machining technique in silicon wafer thinning, it often induces edge chipping which leads to wafer breakage. This study investigates edge chipping of silicon wafer in diamond grinding. The study correlates edge chipping with the crystallographic orientation and thickness of a silicon wafer, as well as grinding process conditions, such as wheel grit size, grinding mode and feed rate. It identifies edge chipping in terms of critical thickness, geometry and dimensions. The study discusses the mechanisms of edge chipping based on machining mechanics and energy theories. Conclusions are drawn to summarize the study.