Single-Chip Eye Tracker Using Smart CMOS Image Sensor Pixels

The eye tracker is a system that detects the point where the user gazes on. The conventional eye tracker using a Charge-Coupled Device (CCD) camera needs many peripherals and software computation causing high cost, computation time and power consumption. This paper proposes a single-chip eye tracker using smart CMOS Image Sensor (CIS) pixels. The proposed eye tracker does not require additional peripherals and operates at higher speed than the conventional approach. The prototype chip was designed and fabricated for a 32 × 32 smart CIS pixels array with a 0.35-μ m CMOS process. The test results show ± 1 pixel error at the rate of 125 frame-per-second. The power consumption is 260 mW with 3.3 V supply voltage and the silicon area is 3.8 mm²     

DESIGN AND IMPLEMENTATION OF CMOS IMAGE SENSOR

I. Introduction Complementary Metal Oxide Semiconductor (CMOS) image sensor has been becoming in-creasingly significant in the field of solid image sensor. Compared with Charge-Coupled Device (CCD) image sensor, CMOS image sensor possesses many advantages, such as smaller size, more con-venient to be integrated with other devices, lower power consumption and cost, etc[1,2]. To date, CMOS image sensor is adopted in almost all mo-biles which can take pictures. In addition, CMOS image …     

A 160×120 Light‐Adaptive CMOS Vision Chip for Edge Detection Based on a Retinal Structure Using a Saturating Resistive Network

We designed and fabricated a vision chip for edge detection with a 160×120 pixel array by using 0.35 µm standard complementary metal‐oxide‐semiconductor (CMOS) technology. The designed vision chip is based on a retinal structure with a resistive network to improve the speed of operation. To improve the quality of final edge images, we applied a saturating resistive circuit to the resistive network. The light‐adaptation mechanism of the edge detection circuit was quantitatively analyzed using a simple model of the saturating resistive element. To verify improvement, we compared the simulation results of the proposed circuit to the results of previous circuits.     

A 256×256 pixel smart CMOS image sensor for line-based stereovision applications

This paper presents a 256×256 pixel smart CMOS image sensor for line based vision applications. By combining the edge-based analog processing technique with an active pixel array, a dense and fast on-chip analog image processing has been achieved. The on-chip processing unit includes (1) an analog histogram equalizer, (2) a programmable recursive Gaussian filter, (3) a spatio-temporal differentiator, and (4) a local extrema extractor. An electronic shutter is applied to the active pixel sensor array in order to adapt the exposure time as a function of global illumination. The on-chip histogram equalizer extends the image into a constant and optimal range for all the following processing operators and gives a stable and predictable precision of the analog processing. A prototype chip has been designed and fabricated in a standard 0.8-μm CMOS process with double poly and double metal, giving a pixel pitch of 20 μm and die size of 7×7 mm². A line processing time is compatible with TV line scan period. The worst case power consumption measures 40 mA at 5 V     

DESIGN AND IMPLEMETTATION OF CMOS IMAGE SENSOR

A single Complementary Metal Oxide Semiconductor (CMOS) image sensor based on 0.35 μm process along with its design and implementation is introduced in this paper. The pixel architecture of Active Pixel Sensor (APS) is used in the chip, which comprises a 256×256 pixel array together with column amplifiers, scan array circuits, series interface, control logic and Analog-Digital Converter (ADC). With the use of smart layout design, fill factor of pixel cell is 43%. Moreover, a new method of Dynamic Digital Double Sample (DDDS) which removes Fixed Pattern Noise (FPN) is used.The CMOS image sensor chip is implemented based on the 0.35 μm process of chartered by Multi-Project Wafer (MPW). This chip performs well as expected.     

A Single‐Chip Video/Audio CODEC for Low Bit Rate Application

In this paper, we present a design of video and audio single chip encoder/decoder for portable multimedia application. The single‐chip called as video audio signal processor (VASP) consists of a video signal processing block and an audio signal processing block. This chip has mixed hardware/software architecture to combine performance and flexibility. We designed the chip by partitioning between video and audio block. The video signal processing block was designed to implement hardwired solution of pixel input/output, full pixel motion estimation, half pixel motion estimation, discrete cosine transform, quantization, run length coding, host interface, and 16 bits RISC type internal controller. The audio signal processing block is implemented with software solution using a 16 bits fixed point DSP. This chip contains 142,300 gates, 22 kbits FIFO, 107 kbits SRAM, and 556 kbits ROM, and the chip size is 9.02 mm ×9.06 mm which is fabricated using 0.5 micron 3‐layer metal CMOS technology.     

A multisampling time-domain CMOS imager with synchronous readout circuit

A novel multisampling time-domain architecture for CMOS imagers with synchronous readout and wide dynamic range is proposed. The proposed multisampling architecture requires only a single bit per pixel memory instead of 8 bits which is typical for time-domain active pixel architectures. The goal is to obtain a time-domain imager with high dynamic range that requires lower number of transistors per pixel in order to achieve higher fill-factor. The maximum frame rate is analyzed as a function of number of bits and array size. The analysis shows that it is possible to achieve high frame rates and operate in video mode having 10 bit pixel data resolution. Also, we present analysis of the impact of comparator offset voltage on the fixed pattern noise. The architecture was implemented in an imager prototype with 32 × 32 pixel array fabricated in AMS CMOS 0.35 μm and was characterized for sensitivity, noise and color response. The pixel size is 30 μm × 26 μm and it is composed of an n+/psub photodiode, a comparator and a D flip-flop with a 16% fill-factor.     

基于HV-CMOS工艺集成PIN光敏元的CMOS传感器设计

PIN光电二极管相对于pn结型光电二极管具有结电容小、量子效率高等优点,但采用标准低压CMOS(LV-CMOS)工艺研制的CMOS传感器只能实现基于n阱/p衬底的pn结光敏元与片上电路的集成,高压CMOS(HV-CMOS)工艺的发展为CMOS电路与PIN光敏元列阵的单片集成提供了可能。基于HV-CMOS工艺设计了一种集成PIN光敏元列阵的CMOS传感器,并对器件的光电响应进行了测试评估。结果表明,集成PIN光敏元的CMOS传感器具有更高的像素增益和量子效率,而暗电流、输出摆幅、线性度等特性保持良好。在500~900nm宽波段范围内,器件的量子效率均达到80%以上,在950nm附近的量子效率达到25%,优于采用其他工艺制作的CMOS传感器。     

InGaAs单光子雪崩焦平面研究进展（特邀）

雪崩光电二极管（APD）是一种高灵敏度光电器件。按照工作电压的不同可分为线性APD和盖革APD。其中,盖革APD的工作电压高于击穿电压,利用半导体材料内部载流子的高雪崩增益可实现单光子级信号探测,也被称为单光子雪崩光电二极管（SPAD）。InGaAs材料SPAD在0.9~1.7 μm光谱范围内有高量子效率,是1.06、1.55 μm主动激光探测的理想探测器。通过将高效率InGaAs SPAD阵列芯片与CMOS计时/计数读出电路芯片集成封装,制备的雪崩焦平面探测器可对光子信号进行时间量化,在三维激光雷达、远距离激光通信、稀疏光子探测等领域有广泛应用。介绍了InGaAs单光子雪崩焦平面的器件结构及基本原理,在此基础上回顾了国内外雪崩焦平面技术的研究进展,并对未来发展方向进行了展望。     

一种高性能红外焦平面阵列读出电路

提出了一种快闪式红外焦平面阵列读出电路。采用改进的直接注入型单元电路,积分电容大小可选,能适应大范围的光背景条件,并且增加了图像变换(倒置/反转)功能。一款128×128阵列的读出电路已经基于标准0.5μmCMOS工艺实现,整体芯片的面积为8.0mm×8.5mm。实测结果表明,此读出电路具有良好的光电转换能力,同时具有功耗低、输出摆幅大、动态范围大等优点。     

Research on Column FPN and Black Level Calibration in Large Array CMOS Image Sensor

A technical investigation, research and im-plementation is presented to correct column fixed pattern noise and black level in large array Complementary metal oxide semiconductor (CMOS) image sensor. Through making a comparison among reported solution, and give large array CMOS image sensor design and considerations, according to our previous analysis on non-ideal factor and error source of piecewise Digital to analog converter (DAC) in multi-channels, an improving accurate piecewise DAC with adaptive switch technique is developed. The research theory has verified by a high dynamic range and low column Fixed pattern noise (FPN) CMOS image sensor prototype chip, which consisting of 8320×8320 pixel array was designed and fabricated in 55nm CMOS 1P4M standard process. The chip active area is 48mm×48mm with a pixel size of 5.7μm×5.7μm. The measured results achieved a high intrinsic dynamic range of 75dB, a low FPN and black level of 0.06％, a low photo response non-uniformity of 1.5％ respectively, and an excellent raw sample image taken by the prototype sensor.     

A LIDAR sensor prototype with embedded 14-bit 52 ps resolution ILO-TDC array

High resolution light detection and ranging (LIDAR) systems enable rapid imaging and mapping for applications such as autonomous vehicles and robotics. This paper presents a high-resolution LIDAR sensor system-on-a-chip (SoC) prototype containing a 31 × 2 pixel channel array with the input time-of-flight resolved by a 32 × 1 time-to-digital converter (TDC) array. A low-power avalanche photodiode (APD) receiver front-end with output bit-line sharing allows an array implementation and achieves ? 22 dBm sensitivity. Injection-locked oscillators (ILOs) are utilized in a TDC design to both minimize clock distribution power and improve timing accuracy. An on-chip phase-looked loop calibrates for ILO global PVT variations and ensures reliability over a wide operating range. Fabricated in GP 65 nm CMOS, the 14-bit TDC consumes 788 μW/channel and achieves 52 ps resolution over an 830 ns full-scale range, 37.2 ps_rms single-shot precision, 11 ps_rms channel uniformity, and DNL/INL of 0.56/1.56 LSB, respectively. This electrical characterization projects that the SoC has the potential for 0.78 cm ranging precision over a 124 m maximum ranging distance. Sensor testing with a pulsed laser and an APD array hybrid-integrated with the CMOS SoC shows a measurement range of over 700 ns with a 3.2 ns maximum single-shot error.     

Wide dynamic range snapshot APS for ultra low-power applications

A novel wide dynamic range (WDR) snapshot active pixel sensor for ultra-low power applications is presented. The proposed imager allows capturing of fast moving objects in the field of view and provides WDR by applying adaptive exposure time to each pixel, according to the local illumination intensity level. Driven by low-power dissipation requirements, the proposed pixel is operated by dual low voltage supplies (1.2 and 1.8 V) and utilizes an advanced low-power sensor design methodology. A test chip of a 32*32 array has been implemented in a standard 0.35-/spl mu/m CMOS technology. A single pixel occupies 18*32 /spl mu/m area and is expected to dissipate 18.5 nW at video rate. System architecture and operation are discussed and simulation results are presented.     

A Fully Synthesizable Bluetooth Baseband Module for a System‐on‐a‐Chip

Bluetooth is a specification for short‐range wireless communication using the 2.4 GHz ISM band. It emphasizes low complexity, low power, and low cost. This paper describes an area‐efficient digital baseband module for wireless technology. For area‐efficiency, we carefully consider hardware and software partitioning. We implement complex control tasks of the Bluetooth baseband layer protocols in software running on an embedded microcontroller. Hardware‐efficient functions, such as low‐level bitstream link control; host controller interfaces (HCIs), such as universal asynchronous receiver transmitter (UART) and universal serial bus (USB) interfaces; and audio Codec are performed by dedicated hardware blocks. Furthermore, we eliminate FIFOs for data buffering between hardware functional units. The design is done using fully synthesizable Verilog HDL to enhance the portability between process technologies so that our module can be easily integrated as an intellectual property core on system‐on‐a‐chip (SoC) ASICs. A field programmable gate array (FPGA) prototype of this module was tested for functional verification and realtime operation of file and bitstream transfers between PCs. The module was fabricated in a 0.25‐µm CMOS technology, the core size of which was only 2.79 mm×2.80 mm.     

A 1 K×1 K high dynamic range CMOS image sensor with on-chipprogrammable region-of-interest readout

An integrated 1024×1024 CMOS image sensor with programmable region-of-interest (ROI) readout and multiexposure technique has been developed and successfully tested. Size and position of the ROI is programmed based on multiples of a minimum readout kernel of 32×32 pixels. Since the dynamic range of the irradiance normally exceeds the electrical dynamic range of the imager that can be covered using a single integration time, a multiexposure technique has been implemented in the imager. Subsequent sensor images are acquired using different integration times and recomputed to form a single composite image. A newly developed algorithm performing the recomputation is presented. The chip has been realized in a 0.5-μm n-well standard CMOS process. The pixel pitch is 10 μm² and the total chip area is 164 mm ²     

CMOS active pixel image sensor

A new CMOS active pixel image sensor is reported. The sensor uses a 2.0 μm double-poly, double-metal foundry CMOS process and is realized as a 128×128 array of 40 μm×40 μm pixels. The sensor features TTL compatible voltages, low noise and large dynamic range, and will be useful in machine vision and smart sensor applications     

Ultra‐small Form‐Factor Helix on Pad‐Type Stage‐Bypass WCDMA Tx Power Amplifier Using a Chip‐Stacking Technique and a Multilayer Substrate

A fully integrated small form‐factor HBT power amplifier (PA) was developed for UMTS Tx applications. For practical use, the PA was implemented with a well configured bottom dimension, and a CMOS control IC was added to enable/disable the HBT PA. By using helix‐on‐pad integrated passive device output matching, a chip‐stacking technique in the assembly of the CMOS IC, and embedding of the bulky inductive lines in a multilayer substrate, the module size was greatly reduced to 2 mm × 2.2 mm. A stage‐bypass technique was used to enhance the efficiency of the PA. The PA showed a low idle current of about 20 mA and a PAE of about15% at an output power of 16 dBm, while showing good linearity over the entire operating power range.     

一个128×128CMOS快照模式焦平面读出电路设计

本文介绍了一个工作于快照模式的CMOS焦平面读出电路新结构——DCA(Direct-injection Charge Amplifier)结构.该结构像素电路仅用4个MOS管,采用特殊的版图设计并用PMOS管做复位管,既可保证像素内存储电容足够大,又可避免复位电压的阈值损失,从而提高了读出电路的电荷处理能力.由于像素电路非常简单,且该结构能有效消除列线寄生电容C_bus的影响,因此该结构非常适用于小像素、大规模的焦平面读出电路.采用DCA结构和1.2μm双硅双铝(DPDM-Double-Poly Double-Metal)标准CMOS工艺设计了一个128×128规模焦平面读出电路试验芯片,其像素尺寸为50×50μm²,电荷处理能力达11.2pC.本文详细介绍了该读出电路的体系结构、像素电路、探测器模型和工作时序,并给出了精确的HSPICE仿真结果和试验芯片测试结果.     

Analogue CMOS prototype vision chip with prewitt edge processing

In this study, the design and realization of an analogue CMOS prototype vision chip with Prewitt edge processing is presented. The chip is designed with voltage and current mode and the main parts are one 16?×?16 pixel array, one pair of absolute value circuits and two transimpedance amplifiers. The technology process is TSMC 0.35???m. The edge processing is performed parallely on pixel level. The performance of the sensor comprises a processing time of 450?ns; optical dynamic range of 53?dB; power consumption at 30 frames per second of 1.5?mW; peak signal to noise ratio of 44?dB.     

基于CMOS集成有源传感器的 新型高能物理粒子轨迹追踪器

本文研究了一个采用标准0.35μm CMOS 工艺制造的新型高能物理粒子轨迹追踪器.这个新型的追踪器运用CMOS有源像素传感器技术(CMOS Monolithic Active Pixel Sensors,MAPS)将信号的探测与处理电路集成在一起,在像素的内部实现了相关双次采样操作(Correlated Doubled Sampling,CDS).实验芯片包含一个128行×32列的像素矩阵,其中,像素的大小为25×25μm².通过采用放射源⁵⁵Fe的测定, 得到像素的等效输入随机噪声 (Temporal Noise) 仅为12个电子而固定噪声(Fixed Pattern Noise,FPN)仅为4个电子.传感器的电荷-电压转换系数(Charge-to-Voltage conversion Factor,CVF)为60μV/e^-.测试中,芯片的信号读取速度达到了12μs/帧.