Ultrathin-body SOI MOSFET for deep-sub-tenth micron era

A 40-nm-gate-length ultrathin-body (UTB) nMOSFET is presented with 20-nm body thickness and 2.4-nm gate oxide. The UTB structure eliminates leakage paths and is an extension of a conventional SOI MOSFET for deep-sub-tenth micron CMOS. Simulation shows that the UTB SOI MOSFET can be scaled down to 18-nm gate length with <5 nm UTB. A raised poly-Si S/D process is employed to reduce the parasitic series resistance     

The enhancement of gate-induced-drain-leakage (GIDL) current inshort-channel SOI MOSFET and its application in measuring lateralbipolar current gain β

An off-state leakage current unique for short-channel SOI MOSFETs is reported. This off-state leakage is the amplification of gate-induced-drain-leakage current by the lateral bipolar transistor in an SOI device due to the floating body. The leakage current can be enhanced by as much as 100 times for 1/4 μm SOI devices. This can pose severe constraints in future 0.1 μm SOI device design. A novel technique was developed based on this mechanism to measure the lateral bipolar transistor current gain β of SOI devices without using a body contact     

Sub-50 nm P-channel FinFET

High-performance PMOSFETs with sub-50-nm gate-length are reported. A self-aligned double-gate MOSFET structure (FinFET) is used to suppress the short-channel effects. This vertical double-gate SOI MOSFET features: 1) a transistor channel which is formed on the vertical surfaces of an ultrathin Si fin and controlled by gate electrodes formed on both sides of the fin; 2) two gates which are self-aligned to each other and to the source/drain (S/D) regions; 3) raised S/D regions; and 4) a short (50 nm) Si fin to maintain quasi-planar topology for ease of fabrication. The 45-nm gate-length p-channel FinFET showed an I_dsat of 820 μA/μm at V_ds=V_gs=1.2 V and T _ox=2.5 mm. Devices showed good performance down to a gate-length of 18 nm. Excellent short-channel behavior was observed. The fin thickness (corresponding to twice the body thickness) is found to be critical for suppressing the short-channel effects. Simulations indicate that the FinFET structure can work down to 10 nm gate length. Thus, the FinFET is a very promising structure for scaling CMOS beyond 50 nm     

ESD robustness prediction and protection device design in partially depleted SOI technology

In this paper we investigate and develop models for partially-depleted silicon-on-insulator (SOI) (PD–SOI) device failure under EOS/ESD stress. The model and experimental data show that due to increased device self-heating, the second-breakdown current per micron width (I_t2) for salicided PD-SOI metal-oxide semiconductor field effect transistor (MOSFET)s with Si film thickness of 100 nm is about 50% of that in their bulk counterparts under human body model (HBM–ESD) stress pulses. Furthermore, I_t2 did not scale with device width. Therefore, ESD protection devices with non-silicided S/D diffusions and source-body tied MOSFETs are investigated for improved ESD protection levels. Compact ESD protection networks using the source-body tied device may have been shown to achieve HBM–ESD protection levels of ±3.75 kV (Smith JC, Lien M, Veeraghaven S. An ESD protection circuit for TFSOI technology. International SOI Conf. Proc. 1996. pp. 170–71).     

PD SOI nMOSFETs中浮体效应对辐照性能的影响

在SIMOX衬底上制备了H形栅和环形栅PD SOI nMOSFETs,并研究了浮体效应对辐照性能的影响.在106rad(Si)总剂量辐照下,所有器件的亚阈特性未见明显变化.环形栅器件的背栅阈值电压漂移比H型栅器件小33%,其原因是碰撞电离使环形栅器件的体区电位升高,在埋氧化层中形成的电场减小了辐照产生的损伤.浮体效应有利于改进器件的背栅抗辐照能力.     

Influence of Floating Body Effect on Radiation Hardness of PD SOI nMOSFETs

H-gate and closed-gate PD SOI nMOSFETs are fabricated on SIMOX substrate,and the influence of floating body effect on the radiation hardness is studied.All the subthreshold characteristics of the devices do not change much after radiation of the total dose of 1e6rad(Si).The back gate threshold voltage shift of closed-gate is about 33% less than that of Hgate device.The reason should be that the body potential of the closed-gate device is raised due to impact ionization,and an electric field is produced across the BOX.The floating body effect can improve the radiation hardness of the back gate transistor.     

A silicon/indium arsenide source structure to suppress the parasitic bipolar-induced breakdown effect in SOI MOSFETs

We introduce Silicon/indium arsenide (Si/InAs) source submicron-device structure in order to minimize the impact of floating body effect on both the drain breakdown voltage and single transistor latch in ultra thin SOI MOSFETs. The potential barrier of valence band between source and body reduces by applying the Indium Arsenide (InAs) layer at the source region. Therefore, we can improve the drain breakdown by suppressing the parasitic NPN bipolar device and the hole accumulation in the body. As confirmed by 2D simulation results, the proposed structure provides the excellent performance compared with a conventional SOI MOSFET thus improving the reliability of this structure in VLSI applications.     

Principles of transient charge pumping on partially depleted SOIMOSFETs

A new method to determine the interface trap density in partially depleted silicon-on-insulator (SOI) floating body MOSFETs is proposed for the first time. It can be considered as a "transient" charge-pumping (CP) technique in contrast to the normally used "steady-state" method. In our technique, majority carriers are removed from the floating body by applying a burst of pulses to the transistor gate. The change in the linear drain current after each pulse is used to determine the device interface trap density. The unique advantage of this method is the possibility to use it to characterize SOI MOSFETs without a body contact. The technique proposed is simple, reliable, and can be used for the characterization of deep submicron devices     

超薄体MOSFET的结构优化

对UTB器件的各结构参数进行了优化,给出了UTB器件设计的指导方向.在UTB器件的设计中,有三个重要参数,即器件的源漏提升高度、锗硅栅(GexSi1-x)中Ge含量的摩尔百分比和硅膜的厚度,并对这三个结构参数对器件性能的影响进行了模拟分析,给出了器件各结构参数的优化方向,找出了可行Ge含量的摩尔百分比和可行硅膜厚度之间的设计容区.通过模拟分析发现,只要合理选择器件的结构参数,就能得到性能优良的UTB器件.     

An experimental study on transport issues and electrostatics of ultrathin body SOI pMOSFETs

We present an experimental study of the transport properties (low field hole mobility /spl mu//sub h/) and electrostatics (threshold voltage V/sub th/, and gate-to-channel capacitance C/sub gc/) of ultrathin body (UTB) SOI pMOSFETs using a large RingFet structure. Body thicknesses were /spl sim/4.3 nm to 50 nm. We find that 1) hole mobility decreases significantly as T/sub Si/<10 nm, and tends to show negligible dependence on the transverse electric field for extremely thin T/sub Si/ (<6 nm) and 2) a V/sub th/ shift of /spl sim/150 mV occurs over the studied T/sub Si/ range, accompanied by enhancement of weak inversion capacitance in thin body devices. Simulations were performed to provide insight into the experimental observations.     

Moore’s crystal ball: Device physics and technology past the 15 nm generation

This paper will discuss advanced CMOS transistor architectures for the 15 nm node and beyond. Transistor architectures such as ultra-thin body (UTB), FinFET (and related architectures such as Trigate, Omega-FET, Pi-FET), and nanowire device architectures will be compared and contrasted. Key technology challenges (such as mobility, resistance and capacitance) shared by all the architectures will be discussed in relation to recent research results. The impact of new transistor architectures on the progression of Moore’s Law will be summarized.     

A novel nanoscaled device concept: quasi-SOI MOSFET to eliminate the potential weaknesses of UTB SOI MOSFET

For the first time, a novel device concept of a quasi-silicon-on-insulator (SOI) MOSFET is proposed to eliminate the potential weaknesses of ultrathin body (UTB) SOI MOSFET for CMOS scaling toward the 35-nm gate length, and beyond. A scheme for fabrication of a quasi-SOI MOSFET is presented. The key characteristics of quasi-SOI are investigated by an extensive simulation study comparing them with UTB SOI MOSFET. The short-channel effects can be effectively suppressed by the insulator surrounding the source/drain regions, and the suppression capability can be even better than the UTB SOI MOSFET, due to the reduction of the electric flux in the buried layer. The self-heating effect, speed performance, and electronic characteristics of quasi-SOI MOSFET with the physical channel length of 35 nm are comprehensively studied. When compared to the UTB SOI MOSFET, the proposed device structure has better scaling capability. Finally, the design guideline and the optimal regions of quasi-SOI MOSFET are discussed.     

Device Design and Optimization Methodology for Leakage and Variability Reduction in Sub-45-nm FD/SOI SRAM

Ultrathin-body fully depleted silicon-on-insulator (UTB FD/SOI) devices have emerged as a possible candidate in sub-45-nm technologies and beyond. This paper analyzes leakage and stability of FD/SOI 6T SRAM cell and presents a device design and optimization strategy for low-power and stable SRAM applications. We show that large variability and asymmetry in threshold-voltage distribution due to random dopant fluctuation (RDF) significantly increase leakage spread and degrade stability of FD/SOI SRAM cell. We propose to optimize FD devices using thinner buried oxide (BOX) structure and lower body doping combined with negative back-bias or workfunction engineering in reducing the RDF effect. Our analysis shows that thinner BOX and cooptimization of body doping and back biasing are efficient in designing low-power and stable FD/SOI SRAM cell in sub-45-nm nodes.     

超薄体MOSFET的结构优化

对U TB器件的各结构参数进行了优化,给出了UTB器件设计的指导方向.在U TB器件的设计中,有三个重要参数,即器件的源漏提升高度、锗硅栅(Gex Si1 - x)中Ge含量的摩尔百分比和硅膜的厚度,并对这三个结构参数对器件性能的影响进行了模拟分析,给出了器件各结构参数的优化方向,找出了可行Ge含量的摩尔百分比和可行硅膜厚度之间的设计容区.通过模拟分析发现,只要合理选择器件的结构参数,就能得到性能优良的U TB器件     

PD SOI MOSFET低频噪声研究进展

随着器件尺寸的不断减小,PD SOI器件的低频噪声特性对电路稳定性的影响越来越大.研究了PD SOI器件低频过冲噪声现象,分析了此类器件在发生浮体效应、栅致浮体效应以及前背栅耦合效应时低频过冲噪声的产生机理及影响因素.最后指出,可以通过添加体接触或将PD SOI器件改进为双栅结构,达到有效抑制低频过冲噪声的目的.     

Ultrathin-body strained-Si and SiGe heterostructure-on-insulator MOSFETs

The combination of channel mobility-enhancement techniques such as strain engineering with nonclassical MOS device architectures, such as ultrathin-body (UTB) or double-gate structures, offers the promise of maximizing current drive while maintaining the electrostatic control required for aggressive device scaling in future technology nodes. The tradeoff between transport enhancement and OFF-state leakage current is compared experimentally for UTB MOSFETs in two types of materials: 1) strained Si directly on insulator (SSDOI) and 2) strained Si/strained Si/sub 1-z/Ge/sub z/ (z=0.46-0.55)/strained Si heterostructure-on-insulator (HOI). SSDOI of moderate strain level (e.g. /spl sim/ 0.8%) yields high electron-mobility enhancements for all electron densities, while high strain levels (e.g. /spl sim/ 1.6%) are required to obtain hole-mobility enhancements at high inversion charge densities. HOI is demonstrated to have similar electron-mobility characteristics to SSDOI, while hole mobilities are improved and can be maintained at high inversion charge densities. Hole mobility in strained channels with thickness below 10 nm is studied and compared for SSDOI and HOI. As the channel thickness is reduced, mobility decreases, as in unstrained silicon-on-insulator (SOI), though hole-mobility enhancements are demonstrated into the ultrathin-channel regime. Increased OFF-state leakage currents are observed in HOI compared to SSDOI and SOI. For a 4-nm-thick buried SiGe layer, leakage is reduced relative to devices with thicker SiGe channels.     

Hole transport in UTB MOSFETs in strained-Si directly on insulator with strained-Si thickness less than 5 nm

Hole transport is studied in ultrathin body (UTB) MOSFETs in strained-Si directly on insulator (SSDOI) with a Si thickness down to 1.4 nm. In these Ge-free SSDOI substrates, the Si is strained in biaxial tension with strain levels equivalent to strained-Si on relaxed SiGe, with Ge contents of 30 and 40% Ge. The hole mobility in SSDOI decreases slowly for Si thicknesses above 4 nm, but drops rapidly below that thickness. Relative to silicon-on-insulator control devices of equal thickness, SSDOI displays significant hole mobility enhancement for Si film thicknesses above 3.5 nm. Peak hole mobility is improved by 25% for 40% SSDOI relative to 30% SSDOI fabricated by the same method, demonstrating the benefits of strain engineering for 3.1-nm-thick UTB MOSFETs.     

Comprehensive study on low-frequency noise characteristics insurface channel SOI CMOSFETs and device design optimization for RF ICs

Low-frequency (LF) noise, a key figure-of-merit to evaluate device technology for RF systems on a chip, is a significant obstacle for CMOS technology, especially for partially depleted (PD) silicon-on-insulator (SOI) CMOS due to the well-known kink-induced noise overshoot. While the dc kink effect can be suppressed by either using body contact technologies or shifting toward fully depleted (FD) operation, the noise overshoot phenomena still resides at high frequency for either FD SOI or poor body-tied (BT) SOI CMOSFETs. In this paper, floating body-induced excess noise in SOI CMOS technology is addressed, including the impact from floating body effect, pre-dc kink operation, and gate overdrive, followed by the proposal of a universal LF excess noise model. As the physical mechanism behind excess noise is identified, this paper concludes with the suggestion of a device design methodology to optimize LF noise in SOI CMOSFET technology     

Self-align recessed source drain ultrathin body SOI MOSFET

In this letter, a self-aligned recessed source/drain (ReS/D) ultrathin body (UTB) silicon-on-insulator (SOI) MOS technology is proposed and demonstrated. The thick diffusion regions of ReS/D are placed on a recessed trench, which is patterned on the buried oxide and go under the SOI film. The new structure reduces the parasitic S/D resistance without increasing the gate-to-drain Miller capacitance, which is the major advantage over the elevated S/D structure. Fabrication details and experimental results are presented. The scalability of the UTB MOSFETs and the larger design window due to reduced parasitics are demonstrated.     

基于UTB-SOI技术的双辅助触发SCR ESD防护器件研究

为了提高FDSOI ESD防护器件的二次击穿电流,基于UTB-SOI技术,提出了一种SOI gg-NMOS和寄生体硅PNP晶体管双辅助触发SCR器件。通过gg-NMOS源区的电子注入和寄生PNP晶体管的开启,共同辅助触发主泄放路径SCR,快速泄放ESD电流。TCAD仿真结果表明,新结构能够泄放较高的二次击穿电流,具有可调节的触发电压。