Q-band (26?40 GHz) GaAs FET single-stage amplifier

The high-frequency S-parameters of a 0.3 ?m-gate-length GaAs FET have been measured and compared with the device equivalent circuit model. From the data a Q-band single-stage low noise (3.1 dB) amplifier was designed.     

Analytical modeling and design criteria for traveling-wave FETamplifiers

The theoretical modeling and design of a traveling-wave FET are described. The device shows the capability of wide-bandwidth performance and high gain and could be useful in power applications. The proposed analytical model considers the full mode effects of the three-coupled transmission lines and an accurate analysis of the FET model in the traveling-wave amplifier. Starting from electrode dimensions and active zone doping, such a model allows one to calculate the scattering parameters. Thus, it is possible to analyze the device as a six port network in a circuit analysis program     

A universal large/small signal 3-terminal FET model using anonquasistatic charge-based approach

Introduces a charge-based nonquasistatic large/small signal FET model that is extracted from measured small signal S-parameter and DC data and can be applied to an arbitrary three-terminal FET structure. The model is based on general physical principles, and provides consistent topologies for both large and small signal simulations to frequencies above f_t and over a wide range of node voltages. The procedure for extracting model elements includes deembedding linear parasitic elements and extracting bicubic, B-spline functions, which represent large signal model elements. The spline coefficients are calculated using a constrained least squares fit to a set of small signal parameters and/or DC currents that have been measured at a number of node voltage values. Advantages of this approach include fast parameter extraction for new FET structures, accuracy, computational efficiency, charge conservation, and the requirement of only a single model for all simulation modes. The model can also be used to interface device simulators (e.g., PISCES) with circuit simulators for accurate predictive modeling     

A design procedure for monolithic matrix amplifier

A procedure for the design of monolithic matrix amplifier is proposed. A simplified expression for small signal gain based on unilateral field-effect transistor (FET) model is derived. In particular, the Design-Oriented FET model previously published is adopted. The introduction of a set of design charts allows the designer a fast and accurate prediction of low frequency gain and 3-dB cutoff frequency of a given matrix amplifier. Good agreement with experimental data and simulations confirms the validity of the proposed design method     

Modeling and characterization of an 80 V silicon LDMOSFET foremerging RFIC applications

This paper describes the design and optimization of an 80 V silicon RF LDMOSFET used in a power amplifier for base station applications. The transistor was prototyped using the doping profiles extracted from an experimental device and extensive two-dimensional (2-D) simulations were performed to characterize the DC and RF performance of the device. A good match between the measured and simulated data is reported. A simple circuit model was developed which accurately predicts the DC and RF characteristics in circuit simulators. It is shown through 2-D simulations that the LDD region in the LDMOSFET can be modeled as a JFET. A methodology for the accurate extraction of model parameters for the circuit model is discussed. It is shown that the DC and RF performances of the circuit model closely match the measured data. Advanced mixed device and circuit simulations were used to obtain S-parameters of the device which provide new insights into device physics and also the basis for statistical process control studies     

A novel temperature-dependent large-signal model of heterojunction bipolar transistor with a unified approach for self-heating and ambient temperature effects

A large-signal modeling of power heterojunction bipolar transistor (HBT) is demonstrated for an accurate simulation of self-heating and ambient temperature effects and nonlinear behaviors such as output power, gain expansion, intermodulation distortion (IMD), and adjacent channel power ratio (ACPR). The physical relationship between the device current and the rate of change in the built-in potential with respect to the device temperature has been utilized for a fully electrothermal modeling. To enable an immediate use for a circuit design, the model extraction was done for in-situ output-stage device from two-stage power amplifier (PA) circuit. In each parameter extraction step, measurement data obtained under a consistent environment, which are current-voltage (I-V) at various temperatures and small-signal S-parameters under various bias conditions, have been carefully examined and utilized to relate the meaning of each parameter to the physical principle of the device. Measurements and simulations are compared for the verification of the model under dc condition at various temperatures.     

S 频段pHEMT 双通道低噪声放大器芯片的设计

采用GaAs 0.13μmp HEMT MMIC流片工艺设计和制作了一种S频段双通道低噪声放大器芯片,芯片内部集成了两个低噪声放大器通道、一级单刀双掷(SPDT)开关和一个晶体管-晶体管逻辑(TTL)电平转换电路。低噪声放大器电路采用一级共源共栅场效应管(Cascode FET)结构实现,使其具有比单管更高的增益,简化了芯片拓扑,降低了芯片设计难度。经流片测试,在1.9~2.1GHz的工作频带内,芯片噪声系数优于1.4dB,增益大于22.5dB,输入驻波优于1.8,输出驻波优于1.4,输出1dB压缩点(P1dB)为10dBm。大量芯片样本在片测试统计数据表明该低噪声放大器成品率大于90%,性能指标优于目前同类商业芯片指标。     

General noise considerations for gigabit-rate NMOSFET front-end design for optical-fiber communication systems

Receiver design noise considerations for FET front ends for fiber-optics amplifiers as presented by Smith and Personick are revisited. The MOSFET noise model used is simple yet more accurate than that used previously. The device equivalent circuit for noise is derived from first principles. We are thus able to optimize the amplifier sensitivity with respect to hot-carrier channel thermal noise in terms of the FET drain-to-source voltage and the effective channel length. The importance of drain-source overlap capacitance in determining amplifier sensitivity, which has hitherto not been formulated, is also quantified. It is thus concluded that in spite of hot-carrier noise effects, fine-line NMOS amplifiers designed for gigabit-rate applications will continue to see sensitivity improvement for effective channel lengths down into the quarter-micrometer range. Investigation in the subquarter-micrometer range is in progress.     

A neural network modeling approach to circuit optimization andstatistical design

The trend of using accurate models such as physics-based FET models, coupled with the demand for yield optimization results in a computationally challenging task. This paper presents a new approach to microwave circuit optimization and statistical design featuring neural network models at either device or circuit levels. At the device level, the neural network represents a physics-oriented FET model yet without the need to solve device physics equations repeatedly during optimization. At the circuit level, the neural network speeds up optimization by replacing repeated circuit simulations. This method is faster than direct optimization of original device and circuit models. Compared to existing polynomial or table look-up models used in analysis and optimization, the proposed approach has the capability to handle high-dimensional and highly nonlinear problems     

低噪声1.21.8GHz致冷FET放大器

本文介绍了低噪声1.21.8 GHz致冷FET放大器的研制工作。在20K环境温度下,带宽1.21.7GHz范围内,放大器噪声温度低于10K,最佳为4K。增益约30dB。设计了一个噪声温度自动测试系统。另外对输入电缆的噪声和总测量误差作了分析。测试总误差为2K。     

A functional GaAs FET noise model

It is the purpose of this paper to develop a theory upon which the design of low noise FET amplifiers can be based. This is not a fundamenta model of the noise mechanisms in GaAs FET's, but rather, an endeavor to relate physically measurable device capacitances and resistances to the device noise figure and optimum noise source impedance. I will be shown that the noise performance of an FET can be adequately described by two uncorrelated noise sources. One, at the input of the FET, is the thermal noise generated in the various resis, tances in the gate-source loop. This noise source is frequency dependent and it can be calculated from the equivalent circuit of the FET. The second noise source, in the Output of the FET, is frequency independent, and not recognizably related to any measured parameters. This output nise is a function of drain current and voltage. The decomposition of the FET noise into two uncorrelated sources simplifies the design of broad-band low noise amplifiers. Once the equivalent circuit of a device and its noise figure at one frequency are known, the optimum noise source impedance and noise figure over a broad range of frequencies may be calculated. For the device designer this model also may be helpful in balancing input-output noise tradeoffs.     

Self-Consistent GaAs FET Models for Amplifier Design and Device Diagnostics

A procedure has been developed for producing accurate and unique small-signal equivalent circuit models for carrier-mounted GaAs FET's. The procedure utilizes zero drain-source bias S parmeter tests to determine accurate values of carrier parasitics, and dc measurements to evaluate the FET's gate, source, and drain resistances. Subsequent S-parameter measurements at full bias are then used to resolve the FET into an equivalent circuit model that has only 8 unknown elements out of a possible 16. A technique for evaluating the frequency range of accurate data is presented and the FET model shown is useful well above the maximum frequency of measurement. Examples of device diagnostics are presented for RCA flip-chip mounted GaAs FET's.     

A low-noise 1.2–1.8 GHz cooled GaAs FET amplifier

A low-noise 1.2–1.8 GHz cooled GaAs FET amplifier with mixer bias circuit is reported. The amplifier noise temperature obtained at an ambient temperature of 20 K in the frequency range of 1.2–1.7 GHz is 10K. The lowest noise temperature is 4K. The gain is about 30 dB. An automatic measuring instrument for noise temperature was designed. The noise effect of the input cable and the error analysis of the total measurement were made. The total measurement error is 2 K.     

Modeling the bias and temperature dependence of a C-class MESFETamplifier

In this paper, a complete bias and temperature-dependent large-signal model for a MESFET is determined from experimental S-parameters and dc measurements. This model is used in the analysis of the performance of a C-class amplifier at 4 GHz over a -50° to 100°C temperature range and for different bias conditions. The dependencies of the elements of the equivalent circuit, as well as the amplifier gain on the temperature and the operating point, are evaluated. The gain optimization and the analysis as a function of temperature of the MESFET amplifier are done by using the describing function technique. Optimum bias device conditions in the C-class are obtained for maximum gain and also the flattest gain versus input power rate. A comparison between theoretical and measured results over temperature and bias ranges is shown. Experimental results show an excellent agreement with the theoretical analysis     

Statistical BSIM model for MOSFET 1/f noise

A statistical model for MOSFET 1/f noise implemented as an extension to BSIM and integrated into a process design kit is presented. Excellent model to hardware correlation is shown on measured noise statistics from over 200 devices. The statistical model enables circuit designers to run Monte Carlo and corner noise simulations, and captures the device area and bias dependence of noise variance.     

GaAs converter IC's for C-band DBS receivers

GaAs downconverter Monolithic Microwave Integrated Circuits (MMICs) for use in C-band direct broadcast satellite (DBS) receivers were developed. The IC consists of four (4) RF functional blocks and a dc bias block. The RF section includes a low noise amplifier, IF amplifier, mixer, and local oscillator. The dc section incorporates an internal dc bias generation circuit to compensate for device parameter fluctuations in wafer processing. The IC makes it easy to design a complete out-door converter unit with only the addition of two low noise FETs, a band pass filter, and an external dielectric resonator. This IC is realized on a small chip of only 1.1 mm×1.6 mm. The gate length of the FET is 0.5 μm. The active layers of the FETs and resistors are formed by an ion-implantation technique. This IC has a 3.0-dB noise figure and a 43-dB conversion gain at 80-mA total current consumption. To realize compact size and low cost, these ICs are offered in 12-pin QFP plastic packages     

An approach to distributed amplifier based on a design-oriented FETmodel

A Design-Oriented FET model in conjunction with an appropriate design procedure for distributed amplifiers is presented. The advantage of including the effects caused by FET parasitics in a newly defined simple unilateral FET circuit to be utilized in the conventional distributed amplifier design procedure allows an accurate prediction of the low-frequency gain and the 3-dB cutoff frequency. The simplicity of this formulation and a set of generalized design charts provide an interesting opportunity to designers. Comparisons among different experimental data from literature and the results obtained by this theory confirm the validity of the Design-Oriented FET model and the effectiveness of the given graphical design method     

A monolithic DC temperature compensation bias scheme for multistageHEMT integrated circuits

This work benchmarks the first demonstration of a multistage monolithic HEMT IC design which incorporates a DC temperature compensated current-mirror bias scheme. This is believed to be the first demonstrated monolithic HEMT bias scheme of its kind. The active bias approach has been applied to a 2-18 GHz five-section low noise HEMT distributed amplifier which achieves a nominal gain of 12.5 dB and a noise figure <2.5 dB across a 2-18 GHz band, The regulated current-mirror scheme achieves better than 0.2% current regulation over a 0-125°C temperature range, The RF gain response was also measured over the same temperature range and showed less than 0.75 dB gain degradation. This results in a -0.006 dB/°C temperature coefficient which is strictly due to HEMT device G_m variation with temperature. The regulated current-mirror circuit can be employed as a stand-alone V_gs-voltage reference circuit which fan be monolithically applied to the gate bias terminal of existing HEMT ICs for providing temperature compensated performance, This monolithic bias approach provides a practical solution to DC bias regulation and temperature compensation for HEMT MMICs which can improve the performance, reliability, and cost of integrated microwave assemblies (IMAs) used in space-flight military applications