Interconnection and packaging of solid-state circuits

The growing interaction between the technologies used to interconnect and package solid-state circuits, the circuit design process, and the performance of such circuits in a system or subsystem is reviewed. The nature of this interaction is discussed at all levels of interconnection and packaging for silicon integrated circuits, and examples of novel developments which present further opportunities to the circuit designer are given. Particular attention is given to the emerging multichip module packaging concept, which offers a similar level of circuit complexity and integration to wafer-scale integration     

A wafer-scale 3-D circuit integration technology

The rationale and development of a wafer-scale three-dimensional (3-D) integrated circuit technology are described. The essential elements of the 3-D technology are integrated circuit fabrication on silicon-on-insulator wafers, precision wafer-wafer alignment using an in-house-developed alignment system, low-temperature wafer-wafer bonding to transfer and stack active circuit layers, and interconnection of the circuit layers with dense-vertical connections with sub-/spl Omega/ 3-D via resistances. The 3-D integration process is described as well as the properties of the four enabling technologies. The wafer-scale 3-D technology imposes constraints on the placement of the first lithographic level in a wafer-stepper process. Control of wafer distortion and wafer bow is required to achieve submicrometer vertical vias. Three-tier digital and analog 3-D circuits were designed and fabricated. The performance characteristics of a 3-D ring oscillator, a 1024 /spl times/ 1024 visible imager with an 8-/spl mu/m pixel pitch, and a 64 /spl times/ 64 Geiger-mode laser radar chip are described.     

A wafer-scale 170000-gate FFT processor with built-in test circuits

The wafer-scale 170000-gate fast Fourier transform (FFT) processor described consists of individual repeatable building blocks, each of which contains a processing element (PE) and interconnection wiring. The PE consists of a multiplier accumulator and its built-in self-test circuits. The wafer system is reconfigured by connected active blocks after block self-diagnosis. Blocks are connected using a programmable contact-hole mask. The processor performs parallel 16-bit, eight-point complex FFTs and is implemented with 725 I/O pads in triple-metal 2.3-μm p-well CMOS technology on a 4-in. wafer. It is mounted by controlled-collapse bonding facedown on a 11.8×11.8-cm² substrate     

Use of unidirectional data flow in bit-level systolic array chips

We show how the architecture of two recently reported bit-level systolic array circuits?a single-bit coefficient correlator and a multibit convolver?may be modified to incorporate unidirectional data flow. This feature has some important advantages in terms of chip cascadability, fault tolerance and possible wafer-scale integration.     

System-in-a-package integration of SAW RF Rx filter stacked on a transceiver chip

Demands for mobile phones with smaller form factor and lower cost have driven enhanced integration of electronics components. However, surface acoustic wave (SAW) filters must be fabricated on piezoelectric substrates, and so they are difficult to monolithically integrate on semiconductor chips. This paper reports on a compact wafer-scale packaged SAW filter stacked over a transceiver chip in a quad flat-pack no-lead (QFN) package. An integrated passive device (IPD) provided redistribution and matching between the SAW filter output and the transceiver input. Both extended global system for mobile communications (EGSM) and DCS filters were evaluated. Results demonstrated that conventional packaging techniques could be used to successfully assemble stacked SAW on transceiver modules without damage. SAW compact models based on the coupling of modes model were developed to facilitate system design. Electromagnetic simulations of coupling between SAW filters and inductors integrated on the transceiver suggested that design care is needed to avoid interactions, especially if an IPD is not used as a spacer. With appropriate design, stacked SAW filter on transceiver offers viable module integration.     

Wafer-scale 3D integration of InGaAs photodiode arrays with Si readout circuits by oxide bonding and through-oxide vias

A new wafer-scale three dimensional (3D) integration technique, originally developed for Si, is applied to hybridize InP-based photodiode arrays with Si readout circuits. The infrared (IR) photodiodes consisted of an InGaAs absorption layer grown on the InP substrate and were fabricated in the same processing line as silicon-on-insulator (SOI) readout circuits to allow 3D integration in the Si fabrication facility. The finished 150-mm-diameter InP wafer was directly bonded to the SOI wafer and interconnected to the Si readout circuits by through-oxide vias (TOV). A 32 × 32 array with 6-μm pixel size was demonstrated. The 3D integration of InP with Si wafers achieved the smallest pixel size, which is less than a half of that can be achieved using conventional flip-chip bump bonding technique.     

A self-learning digital neural network using wafer-scale LSI

A large-scale, dual-network architecture using wafer-scale integration (WSI) technology is proposed. By using 0.8 μm CMOS technology, up to 144 self-learning digital neurons were integrated on each of eight 5 in silicon wafers. Neural functions and the back-propagation (BP) algorithm were mapped to digital circuits. The complete hardware system packaged more than 1000 neurons within a 30 cm cube. The dual-network architecture allowed high-speed learning at more than 2 gigaconnections updated per second (GCUPS). The high fault tolerance of the neural network and proposed defect-handling techniques overcame the yield problem of WSI. This hardware can be connected to a host workstation and used to simulating a wide range of artificial neural networks. Signature verification and stock price prediction have already been demonstrated with this hardware     

Pressure Contact Micro-Springs in Small Pitch Flip-Chip Packages

This work investigates electrical pressure contacts based on a micro-spring with orders of magnitude smaller pitch and force than conventional pressure contacts. The springs are beams which curl out of the surface and can be used for wafer-scale testing and packaging. They are fabricated with standard wafer-scale thin film techniques and have been previously demonstrated on active silicon integrated circuits. Single springs and their electrical contacts are characterized with force versus compression and compression versus resistance measurements. Flip-chip packages with hundreds of micro-springs were assembled with 20-mum pad pitch and 40-mum spring pitch. Each spring operates with a force of approximately 0.01 g and contacts a gold pad. These packages are shown to have stable resistance values during both in-situ thermocycle (0degC to 125degC) and humidity testing (60degC at 95%RH). Spring electrical contacts inside the package are shown not to degrade during environmental testing through measurements of four-wire resistance and electrical isolation structures. High-speed glitch measurements are performed to confirm that the pressure contact does not have intermittent opens during thermocycling. These results suggest that a low-force solder-free pressure spring contact is a viable technology for next generation flip-chip packaging     

Laser-patterned interconnect for thin-film hybrid wafer-scale circuits

High-performance electronic systems are often constrained by conventional packaging and interconnection technologies. A new technique is described for electrically connecting integrated circuit chips to a silicon wafer interconnection substrate, enabling future fabrication of hybrid wafer-scale circuits to be performed exclusively with thin-film interconnection technology. Thin-film wiring is fabricated down beveled edges of the chips and patterned using discretionary laser etching techniques. Interconnections on a 25-µm pitch (1600 wires around a 1-cm square chip) were achieved with this approach. Functioning hybrid memory modules have been fabricated to demonstrate feasibility of the technology.     

Practical Aspects of Phase-Shifter and Driver Design for a Tactical Multifunction Phased-Array RADAR System

Three microwave garnet phase-shifter designs are used in the AEGIS weapons system. The microwave design is straight-forward except that the toroid assembly is potted with silicone rubber to increase its power-handling capability and the magnetizing wires are shielded with a spiral-wrapped wire to prevent the propagation of higher order modes. The driver circuit uses a new "flux-feedback" concept for improved accuracy and employs monolithic circuits, hybrid circuits, and discrete components. Mechanical and electrical design of the interfaces with mating components are important cost considerations and the chosen designs are described in detail. Several techniques for improving production yield are discussed and a table of production statistics is provided. Performance histograms and data averages as a function of time and operating frequency are also presented.     

数字IC可测性设计和自动测试生成技术

描述了一种自动局部扫描可测性设计方法，该方法在电路内部提供附加逻辑，把时序元件串成一条扫描通路，辅以适当的控制信号，使时序元件和组合元件分离开，从而达到可测试的目的，介绍了一种改进的ＰＯＤＥＭ测试生成算法和一种基于模拟的测试生成方法，该方法能较好处理时序电路的测试生成问题。     

Towards foundry approach for silicon photonics: silicon photonics platform ePIXfab

Fabless access to wafer-scale silicon photonics technology is moving silicon photonics closer to becoming a mainstream technology and opens up new exciting areas for research at the same time. It is only by using wafer-scale technology that this emerging field will be able to realise its promise: to become a disruptive technology. At the basis of the rationale for silicon photonics is a complex of photonic functions integrated on a single chip, coupled to a stable, high-yield volume fabrication technology base. ePIXfab is a service platform offering R oriented access to state-of-the-art 200 mm wafer-scale CMOS technology optimised for silicon photonics purposes.     

窄脉冲激光探测电路分析与设计

光电检测电路的设计对激光探测系统的性能有重要的影响。针对窄脉冲激光的时域特性,对窄脉冲激光电路设计进行了详细的分析,包括光电二极管的偏置电压对检测电路的影响、光电流转换方式对信号带宽影响等。为提高探测系统信噪比,对放大电路、补偿电路的带宽设计提出优化方法,给出窄脉冲激光探测器的前级放大电路参数设计的依据,并对探测电路优化及设计方法进行了详细论述,为光电检测电路的设计提供了有效的设计方法。     

Transient analysis of microwave active circuits based ontime-domain characteristic models

A modular method is presented to speed up transient simulation of microwave active circuits which consist of linear components and active devices that are often nonlinear. Firstly, the linear components and active devices are individually characterized by time-domain characteristic models (TDCM's) and lumped equivalent circuits, respectively, to reduce the computer memory. Then, based on deconvolution, the TDCM's of linear components are synthesized from the terminal voltages and currents of step voltage excitation, which are simulated by the finite-difference time-domain (FDTD) method. Finally, transient analysis of a one-dimensional (1-D) discrete-time system is applied to obtain the terminal responses of the microwave active circuits, in which a larger sampled step is chosen to reduce the simulation time. This method is employed to two realistic circuits to validate its efficiency and accuracy. The results are in good agreement with the time-consuming direct FDTD simulation of entire circuits     

Fast Switching and Fair Control of Congested Flow in Broadband Networks

A new switching architecture is proposed based on the tradeoffs of modern VLSI technology-inexpensive memory and 2-dimensional layout structures. Today, it is economically feasible to preallocate buffer space individually to each virtual circuit in every node, so that "congestion" ceases to have negative effects. On the contrary, when some low-priority circuits offer more traffic than the network can carry, full utilization of the link bandwidth is achieved. In this context, the allocation of bandwidth can be done automatically and in a "fair" way, if packets are multiplexed by circularly scanning all virtual circuits and transmitting one packet from each "ready" circuit. This multiplexing algorithm equally distributes all the available link BW to all the VC's that can use it (other than equal distribution is also possible), while it also guarantees an upper bound for the total packet delay through noncongested VC's (VC's that use less than their share of BW). We present methods for hardware implementation of such fast circular scans, and propose a structure for the switching nodes of such networks, consisting of a cross-bar arrangement like a systolic array that performs merge sorting. It is ideally suited for physical layout on printed-circuit boards or with wafer-scale integration.     

Applications of SPICE for modeling miniaturized biomedical sensor systems

This paper proposes a model for a miniaturized signal conditioning system for biopotential and ion-selective electrode arrays. The system consists of three main components: sensors, interconnections, and signal conditioning chip. The model for this system is based on SPICE. Transmission-line based equivalent circuits are used to represent the sensors, lumped resistance-capacitance circuits describe the interconnections, and a model for the signal conditioning chip is extracted from its layout. A system for measurements of biopotentials and ionic activities can be miniaturized and optimized for cardiovascular applications based on the development of an integrated SPICE system model of its electrochemical, interconnection, and electronic components.     

Chemical Vapor Deposition Syntheses of Wafer-Scale 2D Transition Metal Dichalcogenide Films toward Next-Generation Integrated Circuits Related Applications

2D semiconducting transition metal dichalcogenides (TMDCs), most with a formula of MX₂ (M=Mo, W; X=S, Se, etc.), have emerged as promising channel materials for next-generation integrated circuits, considering their dangling-bond-free surfaces, moderate bandgaps, relatively high carrier mobilities, etc. Wafer-scale preparation of 2D MX₂ films holds fundamental significance for realizing their applications. Chemical vapor deposition (CVD) is recognized as the most promising method for preparing electronic-grade 2D MX₂ films. This review hereby summarizes the recent progress in CVD syntheses of wafer-scale 2D MX₂ films and their applications in logic operations, data storage, and image capturing/processing related fields. The first part focuses on the wafer-scale syntheses of 2D MX₂ films through designing homogeneous metal precursor supply routes (e.g., precoating soluble precursor, feeding gaseous precursor, designing independent multisource supply or face-to-face metal precursor supply routes). The second part highlights the epitaxial growth of monolayer MX₂ single crystals on single-crystal Au substrates and well-designed sapphire substrates. The third part introduces various functional device/circuit related applications of CVD-derived 2D MX₂ wafers. Finally, challenges and prospects are discussed from the viewpoints of the controlled synthesis, reliable characterization, and damage-free transfer of 2D MX₂, as well as the fabrication and integration of high-performance devices.     

Static analysis of microstrip discontinuities using the excesscharge density in the spectral domain

Galerkin's method in the spectral domain is applied to solve for the excess charge density existing on the strips of open-end and symmetric gap discontinuities in multilayered anisotropic substrates. The excess charge density is used to determine the capacitance components of the equivalent circuits, of these discontinuities. Numerical results are provided and a comparison with previous results is carried out     

A New RF CMOS Gilbert Mixer With Improved Noise Figure and Linearity

The noise figure of an RF CMOS mixer is strongly affected by flicker noise. The noise figure can be improved using pMOS switch circuits, which insert current at the on/off crossing instants of the local oscillator switch stage because the circuits reduce the flicker noise injection. When it is applied to a conventional Gilbert mixer, the injection efficiency and linearity are degraded by the nonlinear parasitic capacitances of the pMOS switch circuits and the leakage through the parasitic path. We propose the pMOS switch circuits with an inductor, which tunes out the parasitic components at 2f_o and closes out the leakage path. The mixer fabricated in 0.13-mum CMOS at 2.4-GHz center frequency has provided improved characteristics for linearity and noise figure.     

GaAs HBT's for microwave integrated circuits

The status of the microwave GaAs heterojunction bipolar transistor (HBT) technology is reviewed. Microwave circuits for advanced military and commercial systems continue to increase their dependence on the performance, functionality, and cost of active components fabricated using solid-state technology. The performance advantages provided by GaAs HBT's, for several critical circuit applications, have stimulated a worldwide development activity. Progress in HBT device technology and microwave circuit applications has been extremely rapid because of the broad availability of III-V compound semiconductor epitaxial materials and prior experience with GaAs field-effect transistors (FET's) and monolithic microwave integrated circuits (MMIC's). The great flexibility of HBT's in microwave circuits makes them prime candidates for applications in complex multifunctional microwave/digital IC's in next-generation systems