小型化、一体化浮动板脉冲调制器的研究

脉冲调制器是雷达发射机中的关键部分,对雷达整机性能影响重大。本文针对机载雷达发射机对脉冲调制器体积小、一体化的要求,提出了一种小型化、一体化的浮动板脉冲调制器的设计方法。该方法统一调制器的设计思想,合理布局,结构紧凑,实现了调制器的小型化、一体化设计,提高了调制器的可靠性、可维修性。     

一种固态调制器的设计分析

按某气象雷达对发射系统的具体要求,在满足磁控管正常工作条件的情况下,给出了调制器的技术指标,形成了调制器实现的功能框图,并介绍了其各个部分的原理和功能。调制器的设计采用3只串联可控硅作为放电开关(固态调制器);其最大工作电压可达3 kV,实际工作有40%的冗余,有利于提高调制器的可靠性;高压电源采用回扫充电方式的开关电源,它使充电、放电分时进行,可以抗调制器连通,减少电源纹波对调制器指标的影响;1μs矩形脉冲采用双线PFN形成,并给出了严格的理论分析,得到了可靠的调制器设计参数。双线PFN的充电电压和输出电压相等,在调制器输出电压相同的情况下,双线PFN的充电电压比单线PFN减小一半,可以有效地减少串联SCR的数量,给使用和维护带来了方便。调制器监控是通过PLC(Programed Logic Controller)编程实现的。PLC具有很强的抗干扰性能,并有标准的422串行接口,有利于外部连接。调制器对所有的故障信号和状态信号实时监控,把故障信号与加高压信号互锁,保证人、机安全。该调制器具有体积小、重量轻的特点,便于安装、使用。结果证明文中的逻辑分析和参数选择是合理的,满足工程设计要求。目前该调制器已在多部气象雷达发射机中应用,工作安全、可靠,对今后这方面的相关工程设计具有一定的借鉴作用。     

180 kW全固态高压脉冲调制器的设计

为克服以真空电子管作为脉冲开关的传统调制器的缺点,介绍了一种以半导体器件作为脉冲开关的全固态高压脉冲调制器的设计工作。该调制器用于取代传统调制器来驱动速调管,输出脉冲功率180 kW(15 kV,12A)。分析了它的串联开关拓扑结构后讨论了开关器件的工艺和参数选择、均压网络对系统暂态和稳态能量的控制I、GBT驱动电路高压隔离与精确同步的解决方案以及系统控制策略的实现等关键技术。还开展了模拟打火条件下的快速过流保护试验并给出了试验波形。利用SABER软件对调制器电路的仿真和与实际测试波形的对比结果证明:这种固态调制器能够可靠工作。     

基于PLL重配置技术的正交调制器设计

为了在同一硬件平台上实现多种符号速率和多种通信体制,基于FPGA内部PLL可重配置技术和DDS专用芯片,提出了一种在不同通信体制下实现调制符号率逐比特可变的正交调制器设计方法,并在以EP4SE230为核心的处理平台上进行了硬件实现。通过改变调制器参数并采用矢量信号分析仪对调制信号进行测量,结果显示正交调制器信号的幅频特性和EVM均满足系统要求。采用这种方法实现的调制器具有很强的灵活性,符合数字通信软件无线电的趋势。     

大屏幕激光扫描显示系统光强调制技术研究

利用声光调制器对经过准直和聚焦的三单色激光束分别进行调制。本系统配备必要装置搭建实验平台,提出了通过查询电路实现实时声光调制器(AOM)调制非线性的方法,并且实验证明了该校正方法的可行性。     

多位∑-△调制器在数据采集系统中应用

通过对过采样∑-Δ调制器的原理分析和性能仿真,表明该调制器具有良好的噪声整形特性;在对高速信号的采集过程中,多位系统比1位系统有着更大的优越性。文中应用该技术设计一个可变换采样精度的数据采集系统。     

多位∑-Δ调制器在数据采集系统中应用

通过对过采样∑-Δ调制器的原理分析和性能仿真,表明该调制器具有良好的噪声整形特性;在对高速信号的采集过程中,多位系统比1位系统有着更大的优越性.文中应用该技术设计一个可变换采样精度的数据采集系统.     

一种通用全数字中频调制器的设计与实现

本文提出了一种基于现场可编程门阵列(FPGlA)实现通用企数字中频正交扩频调制器的方案,针对方案中的关键技术DcU(数字上变频),做出了分析和总结,并提出了具体实现方案.整个设计在一片人规模可编程逻辑器件FPGA芯片上,实现了高度集成化、小型化,使整个调制器具有可编程的特点,易于根据实际要求进行功能上的扩展和缩减.在此基础上针对整个系统在FPGA上实现时的性能优化,提出了改进方案.同时,通过ISE与MATLAB的联合仿真,分析方案的仿真结果,达到了设计要求.     

多位∑—△调制器在数据采集系统中应用

通过对过采样∑-△调制器的原理分析和性能仿真，表明该调制器具有良好的噪声整形特性；在对高速信号的采集过程中，多位系统比1位系统有着更大的优越性。文中应用该技术设计一个可变换采样精度的数据采集系统。     

基于SOPC的DSP系统设计基本电路模块

介绍片上可编程系统(SOPC)的概念,给出了基于SOPC利用MATLAB/DSP Builder幅度调制器的设计实例和借助QuartusⅡ软件实现的仿真波形.     

Design and implementation of a digitally controlled single‐inductor dual‐output (SIDO) buck converter

This paper describes design and implementation of a digitally controlled single‐inductor dual‐output (SIDO) buck converter operating in discontinuous conduction mode. This converter adopts time‐multiplexing control in providing two independent output voltages using only an inductor. The design issues of the digital controller are discussed, including static and dynamic characteristics. Implementation of the controller, a modified hybrid digital pulse width modulator and a single look‐up table are developed. The digital controller was implemented on a field‐programmable gate array‐based control board. Experimental results demonstrating system validity are presented for a SIDO buck converter with nominal 3.6 V input voltage, and the outputs are regulated at 1.8 and 2.2 V. Copyright © 2012 John Wiley & Sons, Ltd.     

A single‐bit continuous‐time delta‐sigma modulator using clock‐jitter and inter‐symbol‐interference suppression technique

This paper presents a technique for mitigating two well‐known DAC non‐idealities in continuous‐time delta‐sigma modulators (CTDSMs), particularly in wide‐band and low over‐sampling‐ratio (OSR) cases. This technique employs a special digital‐to‐analog convertor (DAC) waveform, called modified return‐to‐zero (MRZ), to reduce the time uncertainty effect because of the jittered clock at the sampling time instances and eliminate the effect of inter‐symbol‐interference (ISI) which degrades the modulator performance, especially when non‐return‐to‐zero (NRZ) DAC waveform is chosen in the modulator design. A third‐order single‐bit CTDSM is designed based on the proposed technique and step‐by‐step design procedure at circuit and system levels, considering clock jitter and ISI, is explained. Circuit simulations in 180‐nm CMOS technology show that in the presence of circuit non‐idealities which generate jitter and asymmetrical rise and fall times in the DAC current pulse, signal‐to‐noise‐distortion‐ratio (SNDR) of the proposed modulator is higher than the conventional modulator with NRZ waveform by about 10 dB. In these simulations, clock jitter standard deviation is 0.3% of the sampling period (T_S) and the difference between fall/rise times in the DAC current pulse is 4%T_S. Simulated at 600‐MHz sampling frequency (f_S) with an oversampling ratio (OSR) of 24, SNDR figure of merit (FOM_SNDR) of the proposed modulator in 180‐nm CMOS is 300 fj/conversion. Copyright © 2016 John Wiley & Sons, Ltd.     

A 6th‐order 75 dB‐DR 10.7 MHz 3.3 V CMOS bandpass ΣΔ modulator sampled at 37.05 MHz

This paper describes the design and the implementation of a 6th‐order bandpass ΣΔ modulator to be used for IF digitizing at 10.7 MHz of a broadcasting FM radio signal. The modulator is sampled at 37.05 MHz. This sampling frequency value allows to optimize both modulator and overall receiver channel performance. The modulator has been implemented in a standard double‐poly 0.35 µm CMOS technology using switched capacitor (SC) technique and consumes 116 mW from a single 3.3 V power supply. The modulator features 75 dB dynamic range and 66 dB peak‐SNR within a 200 kHz bandwidth (FM bandwidth). Third‐order intermodulation products are suppressed by –78dBc. Copyright © 2004 John Wiley & Sons, Ltd.     

A 15-MHz bandwidth double sampling MASH25b-15b sigma-delta modulator with DEM for multibit DACs

A high SNDR discrete-time (DT) 2-1 MASH sigma-delta modulator (SDM) for 15-MHz bandwidth was presented. Cascade of integrators with feedforward (CIFF) scheme, combined with the optimized gain coefficients, was adopted to avoid of the integrators. Double sampling technique was employed to relax the OPA settling requirements by halving the clock frequency and therefore reduce the power consumption. Five-bit flash quantizer was adopted in both stages to improve the overall signal-to-noise and distortion ratio (SNDR) performance, and third-order dynamic element matching (DEM) was analyzed and applied for the multibit DACs to suppress the element mismatch noise. Fabricated in a mature 0.18-μm CMOS technology, the occupied area of the modulator was 0.24 mm² and dissipation power 25.4 mW from a 1.8-V voltage supply. As a sampling rate of 240 MHz for the input sampling and DAC and 480 MHz for the flash ADC, a SNDR of 90.2 dB over 15-MHz signal bandwidth and the corresponding effective number of bits (ENOB) of 14.69 bit were achieved. The spurious-free dynamic range (SFDR) was 98 dB with DEM turned on for a 3.75 MHz at −2.5-dBFS input signal, and the figure of merit (FOM) was 30.7 fJ/conv. for 15-MHz bandwidth. A 15-MHz bandwidth multibit MASH2-1 discrete-time sigma-delta modulator was proposed. Double sampling technique was employed to relax the OPA settling requirements by halving the clock frequency and therefore reduce the power consumption. High-order DEM was analyzed and applied for the multibit DACs to suppress the element mismatch noise. Fabricated by a 0.18-μm CMOS process, the modulator achieved a SNDR of 90.2 dB and the corresponding ENOB 14.69 bit over 15-MHz signal bandwidth. The proposed modulator was very suitable for wideband applications including wireless communication systems, high-frequency biomedical imaging or sensing systems, and so on.     

An adaptive digital processor for power efficiency enhancement in hybrid supply modulators

A novel digital envelope modulator for envelope tracking radio frequency power amplifier is presented in this paper. The proposed modulator consists of a parallel combination of linear class AB and switching class D power amplifiers that are controlled digitally. In the previous analog architectures, the requirements needed for the AB operational amplifier such as high‐current driving capability, high bandwidth and large output swing is usually obtainable at high overall static power dissipation. The digitally controlled power opamp presented here not only provides the aforementioned requirements but also reduces power dissipation compared with previous work. Furthermore, the digital control of the modulator makes it adaptive to the input signal variations in comparison with conventional analog parallel hybrid envelope modulators. The digital processor of the modulator is evaluated with a 45‐nm complementary metal oxide semiconductor technology. The overall power consumption of the digital processor is around 142 mW at 1.5‐GHz clock frequency. As an application, the designed digital class AB is incorporated in a complete envelope modulator architecture. The overall efficiency of the modulator, including the digital processor power consumption, is around 82% at an average 32 dBm output power for a 5‐MHz input signal. Copyright © 2015 John Wiley & Sons, Ltd.     

Redesign of the SNS modulator H-bridge for utilization of press-pack IGBTs

The Power Systems Development group at SLAC has developed an improved design for the H-bridge switch plates of the High Voltage Converter Modulators at the Spallation Neutron Source. This integral modulator component has been identified as the source of numerous modulator faults. This paper presents the design and implementation of the alternative switch plate, which is based upon press-pack IGBTs.     

一种新颖的固态高压线性调制器

介绍了一种新颖的大功率固态高压线性调制器，阐述了其工作原理、设计方法及工作特点，并给出仿真和实验结果。     

A 20-MHz bandwidth, 75-dB dynamic range,continuous-time delta-sigma modulator with reduced nonidealities

This letter presents a 4-bit continuous-time delta-sigma modulator (CT-DSM) fabricated using a 65-nm CMOS process. The circuit is designed for wide-bandwidth applications, such as those related to wireless communications. This CT-DSM has an oversampling ratio of 16 with a 640-MHz sampling frequency. To reduce the clock jitter sensitivity and excess loop delay effect, the first DAC pulse is a nonreturn-to-zero (NRZ)–type pulse, whereas the second DAC pulse is a return-to-zero (RZ)–type pulse; this is accomplished using a current-steering DAC. In order to reduce mismatch without using a data-weighted averaging circuit, the size and layout of the unit current source in the current-steering DAC are considered carefully. The CT-DSM achieves a signal-to-noise ratio (SNR) of 67.3 dB, a signal-to-noise and distortion ratio (SNDR) of 63.4 dB, and a dynamic range of 75 dB for a 20-MHz signal bandwidth.     

High dynamic range pseudo–two-level digital pulse-width modulation for power-efficient RF transmitters

Radio frequency (RF) power amplification based on pulse-width modulation (PWM) has been widely discussed as a potential solution to achieve higher efficiency in RF transmitters. A digitally implemented PWM introduces a large amount of in-band distortion due to spectral aliasing. In this paper, a novel memoryless PWM modulator with a built-in anti-aliasing filter is proposed that effectively reduces the in-band distortion in digital implementation. The spectral characteristics of the proposed PWM modulator as well as the statistical properties of its output PWM signal are analytically studied. The pseudo–two-level output of the proposed modulator provides the capability to compromise between the efficiency, linearity, and complexity of transmitter, based on the given design targets. The proposed PWM method benefits from a simple circuit implementation in both digital and RF sections of the transmitter. Moreover, it preserves the low distortion property at low oversampling ratios of digital baseband. Simulations, as well as measurements, verify the performance of the proposed method.     

A neural-network-based space-vector PWM controller for athree-level voltage-fed inverter induction motor drive

A neural-network-based implementation of space-vector modulation (SVM) of a three-level voltage-fed inverter is proposed in this paper that fully covers the linear undermodulation region. A neural network has the advantage of very fast implementation of an SVM algorithm, particularly when a dedicated application-specific IC chip is used instead of a digital signal processor (DSP). A three-level inverter has a large number of switching states compared to a two-level inverter and, therefore, the SVM algorithm to be implemented in a neural network is considerably more complex. In the proposed scheme, a three-layer feedforward neural network receives the command voltage and angle information at the input and generates symmetrical pulsewidth modulation waves for the three phases with the help of a single timer and simple logic circuits. The artificial-neural-network (ANN)-based modulator distributes switching states such that neutral-point voltage is balanced in an open-loop manner. The frequency and voltage can be varied from zero to full value in the whole undermodulation range. A simulated DSP-based modulator generates the data which are used to train the network by a backpropagation algorithm in the MATLAB Neural Network Toolbox. The performance of an open-loop volts/Hz speed-controlled induction motor drive has been evaluated with the ANN-based modulator and compared with that of a conventional DSP-based modulator, and shows excellent performance. The modulator can be easily applied to a vector-controlled drive, and its performance can be extended to the overmodulation region