Dynamic partitioning of multiprocessor systems

Partitioning of processors on a multiprocessor system involves logically dividing the system into processor partitions. Programs can be executed in the different partitions in parallel. Optimally setting the partition size can significantly improve the throughput of multiprocessor systems. The speedup characteristics of parallel programs can be defined by execution signatures. The execution signature of a parallel program on a multiprocessor system is the rate at which the program executes in the absence of other programs and depends upon the number of allocated processors, the specific architecture, and the specific program implementation. Based on the execution signatures, this paper analyzes simple Markovian models of dynamic partitioning. From the analysis, when there are at most two multiprocessor partitions, the optimal dynamic partition size can be found which maximizes throughput. Compared against other partitioning schemes, the dynamic partitioning scheme is shown to be the best in terms of throughput when thereconfiguration overhead is low. If the reconfiguration overhead is high, dynamic partitioning is to be avoided. An expression for the reconfiguration overhead threshold is derived. A general iterative partitioning technique is presented. It is shown that the technique gives maximum throughput forn partions.     

A comparison of multiprocessor task scheduling algorithms with communication costs

Both parallel and distributed network environment systems play a vital role in the improvement of high performance computing. Of primary concern when analyzing these systems is multiprocessor task scheduling. Therefore, this paper addresses the challenge of multiprocessor task scheduling parallel programs, represented as directed acyclic task graph (DAG), for execution on multiprocessors with communication costs. Moreover, we investigate an alternative paradigm, where genetic algorithms (GAs) have recently received much attention, which is a class of robust stochastic search algorithms for various combinatorial optimization problems. We design the new encoding mechanism with a multi-functional chromosome that uses the priority representation—the so-called priority-based multi-chromosome (PMC). PMC can efficiently represent a task schedule and assign tasks to processors. The proposed priority-based GA has show effective performance in various parallel environments for scheduling methods.     

Chained backplane communication architecture for scalable multiprocessor systems

A scalable backplane topology which allows a practically unlimited number of modules with identical interfaces is presented. Short, buffered, point-to-point connections overcome clock skew problems. Synchronized, pipelined data transfer operations ensure high throughput and reasonably low latency times for fine-grain parallel algorithms. A simple bus interface logic without any special hardware configuration guarantees a cheap implementation with standard FPGAs. The measured performance in our FPGA based prototype with 32 bit wide data bus shows a throughput of 160 Mbytes/s for each module with 75 ns latency time between modules.     

分数阶混沌系统同步及其保密通信

针对参数未知的分数阶Chen混沌系统,研究其同结构同步以及与分数阶Lü混沌系统的异结构同步问题。利用分数阶系统稳定性理论和拉普拉斯变换理论,设计并证明了系统的反馈控制器,给出了一种分数阶混沌保密通信系统。运用分数阶微积分的预估——校正算法进行数值仿真,验证了所提出方法的有效性。     

Reducing communication latency with path multiplexing in opticallyinterconnected multiprocessor systems

Reducing communication latency, which is a performance bottleneck in optically interconnected multiprocessor systems, is of prominent importance. A conventional approach for establishing connections in multiplexed networks uses a set of independent time slots (or virtual channels) along a path for each connection. This approach requires the use of switching devices capable of interchanging time slots, and thus introduces latency in addition to hardware and control complexity. We propose an approach to all-optical time division multiplexed (TDM) communications in multiprocessor systems. The idea is to establish a connection along a path using a set of time slots (or virtual channels) that are dependent on each other, so that no time slot interchanging is required. We compare the proposed approach with the conventional one in terms of the overall communication latency. We found that, despite the possibility that establishing a connection may take a longer time, the proposed approach will result in lower overall communication latency as it eliminates the delays introduced by the time slot interchanging switching devices     

基于双处理器图像采集与处理的同步

OMAP系列是TI公司针对第三代手机而开发的高性能多媒体处理器，集成有一个ARM的内核和一个DSP的内核(TMS320C55x)。本文设计了OMAPl510和OV7640的接口电路。采用非常简单的机制，实现了ARM处理器采集图像与DSP视频编码的同步，该方案可广泛应用在采用双处理器分别进行图像采集和压缩的硬件平台上。     

Kernel-Kernel communication in a shared-memory multiprocessor

In the standard kernel organization on a bus-based multiprocessor, all processors share the code and data of the operating system; explicit synchronization is used to control access to kernel data structures. Distributed-memory multicomputers use an alternative approach, in which each instance of the kernel performs local operations directly and uses remote invocation to perform remote operations. Either approach to interkernel communication can be used in a large-scale shared-memory multiprocessor. In the paper we discuss the issues and architectural features that must be considered when choosing between remote memory access and remote invocation. We focus in particular on experience with the Psyche multiprocessor operating system on the BBN Butterfly Plus. We find that the Butterfly architecture is biased towards the use of remote invocation for kernel operations that perform a significant number of memory references, and that current architectural trends are likely to increase this bias in future machines. This conclusion suggests that straightforward parallelization of existing kernels (e.g. by using semaphores to protect shared data) is unlikely in the future to yield acceptable performance. We note, however, that remote memory access is useful for small, frequently-executed operations, and is likely to remain so.     

Novel control for delay-locked loop in IR-UWB communication systems

Timing synchronization represents a major challenge in carrying out highly efficient ultra-wideband (UWB) communications. The delay-locked loop (DLL) method is widely proposed to maintain the satisfactory synchronization and reduce timing error. In this paper, the structure of DLL is modified by using the internal model control (IMC). This novel approach in the telecommunication systems has a good performance of overcoming disturbance and deviations of model parameters. Then the proposed IMC-DLL structure is developed, and by taking a linear Doppler Effect into account. This development is achieved by using the following two approaches: multi-model approach and moving average filter. Finally, the simulation results confirm that the proposed IMC-DLL system is able to achieve satisfactory and accurate tracking even in the presence of Doppler effect, and they also confirm that the proposed DLL has higher transient response, compared with the classical one.     

Three level partitioning algorithm for circuit simulation on multiprocessor

Circuit partitioning issues for circuit simulation on distributed multiprocessors are discussed in this paper. An efficient three-level partitioning algorithm for large-scale circuit is proposed. Using this algorithm, we can partition a large-scale circuit into r subcircuits of similar size while keeping the interconnect set of nodes to a minimum. This algorithm can be implemented for parallel processing. Some examples are given to show the performance of the algorithm.     

A parallel graph partitioning algorithm for a message-passing multiprocessor

We develop a parallel algorithm for partitioning the vertices of a graph intop2 sets in such a way that few edges connect vertices in different sets. The algorithm is intended for a message-passing multiprocessor system, such as the hypercube, and is based on the Kernighan-Lin algorithm for finding small edge separators on a single processor.⁽¹⁾ We use this parallel partitioning algorithm to find orderings for factoring large sparse symmetric positive definite matrices. These orderings not only reduce fill, but also result in good processor utilization and low communication overhead during the factorization. We provide a complexity analysis of the algorithm, as well as some numerical results from an Intel hypercube and a hypercube simulator.Publication of this report was partially supported by the National Science Foundation under Grant DCR-8451385 and by AT&T Bell Laboratories through their Ph.D scholarship program.     

Sensitivity study of location management area partitioning in cellular communication systems

The problem of finding the appropriate location area (LA) partitioning that minimizes the total signaling cost in cellular radio network location management is important since it maximizes the bandwidth available for revenue-generating services. All of the existing work involves finding the solution for a given fixed set of parameters. However, we feel that the result obtained is generally insufficient to the problem, since values taken by the parameters of a mathematical programming model at the time of its formulation are only estimates of real-life conditions. The optimal solution should instead be treated as a starting point for further sensitivity study of the problem. This is particularly important in helping to identify any vast deviation of the parameters that affect the system performance. Such a study is still lacking for in cellular communication systems, which normally have their design parameters varying or fluctuating due to unpredictable human movements. In this paper, we present the sensitivity study on the static location management design of a GSM cellular communication system which is modeled as a non-linear programming problem. We investigate the sensitiveness of the total signaling cost with one of these parameters: cell crossing rates, call arrival rates, paging and update costs, deviates from the design value. The bounds for these parameters within which the parameters can change but the LA partitioning remains still optimal are presented.     

Comparison of five multiprocessor systems

This paper generalizes the traditional dataflow model of computation and defines the essential problems in multiprocessing: control implementation, program partitioning, scheduling, synchronization, and memory access. The paper assumes that these essential problems are axes of a multiprocessor design space and that the solutions to these problems are values on the axes. Each point in the space represents a multiprocessor including a computational paradigm that a user must follow to achieve high performance and efficiency on the particular machine. Thus, a classification of machines from the user's point of view is introduced naturally. Five well-known multiprocessors are compared using this classification scheme.     

异结构混沌系统同步及其在保密通信中的应用

针对统一混沌系统和Qi混沌系统的模型，根据主动控制思想和Lyapunov稳定性定理，构造主动控制器使得这两个异结构的混沌系统实现同步，并且实现了驱动系统参数已知而响应系统参数未知的异结构混沌系统的白适应同步，并且能较怏的辨析出系统的未知参数．并利用MATLAB进行数字仿真，将同步的异结构混沌系统应用到混沌掩盖和混沌扩频保密通信中．仿真结果表明，异结构混沌系统能够实现稳定的同步，且在混沌掩盖和混沌扩频保密通信中，有用信号均能有效地在接收端恢复出来．     

异结构混沌系统同步及其在保密通信中的应用*

根据主动控制思想和Lyapunov稳定性定理,构造主动控制器使得两个异结构的混沌系统在短时间内实现同步,并证明了混沌同步的鲁棒稳定性;利用MATLAB的Simulink技术进行数字仿真,将同步的异结构混沌系统应用到混沌掩盖和混沌参数调制保密通信中。仿真结果表明,异结构混沌系统能够实现稳定的同步,且在混沌掩盖和混沌参数调制保密通信中,有用信号均能有效地在接收端恢复出来。     

异结构CNN混沌系统同步及其在保密通信中的应用

传统的信号加密方法由于密钥少而极易受到攻击被破坏,混沌系统的良好伪随机性及丰富的系统参数弥补了传统加密的不足,而时滞混沌系统的复杂动力学空间特性使其非常适用于信号加密,利用时滞混沌系统的同步控制可实现理想的保密通信.细胞神经网络比普通的混沌系统具有更复杂的系统结构和更高的系统维数,采用具有不同结构的细胞神经网络混沌系统分别作为同步系统的驱动和响应,通过求得驱动与响应之间的误差系统并将它代入一个合适的Lyapunov-Krasovskii泛函,对该泛函进行稳定性分析,设计出一个有效的同步控制器.数值仿真实验验证了其有效性,利用该同步系统进行信号与数字图像保密通信,获得了较理想的加解密效果.     

Benchmark-problem instances for static scheduling of task graphs with communication delays on homogeneous multiprocessor systems

Scheduling program tasks on processors is at the core of the efficient use of multiprocessor systems. Most task-scheduling problems are known to be NP-Hard and, thus, heuristics are the method of choice in all but the simplest cases. The utilization of acknowledged sets of benchmark-problem instances is essential for the correct comparison and analysis of heuristics. Yet, such sets are not available for several important classes of scheduling problems, including multiprocessor scheduling problem with communication delays (MSPCD) where one is interested in scheduling dependent tasks onto homogeneous multiprocessor systems, with processors connected in an arbitrary way, while explicitly accounting for the time required to transfer data between tasks allocated to different processors. We propose test-problem instances for the MSPCD that are representative in terms of number of processors, type of multiprocessor architecture, number of tasks to be scheduled, and task graph characteristics (task execution times, communication costs, and density of dependencies between tasks). Moreover, we define our task-graph generators in a way appropriate to ensure that the corresponding problem instances obey the theoretical principles recently proposed in the literature.     

不同阶混沌系统同步及其在保密通信中应用

基于Lyapunov稳定性理论,采用主动控制思想研究了不同阶混沌系统广义投影同步问题,实现了混沌系统的广义投影同步,同时将该同步方法应用于保密通信中。数值仿真表明系统可实现广义投影同步,且在保密通信中能够有效恢复出有用信号。     

Simulation of hierarchical multiprocessor database systems

The paper is dedicated to issues concerning simulation and analysis of hierarchical multiprocessor systems oriented to database applications. Requirements for a parallel database system model are given. A survey and comparative analysis of known parallel database system models are presented. A new multiprocessor database system model is introduced. This model allows us to simulate and evaluate arbitrary hierarchical multiprocessor configurations in the context of the OLTP class database applications. Examples of using the database multiprocessor model for simulation study of multiprocessor database systems are presented.