共查询到20条相似文献,搜索用时 890 毫秒
1.
Hae-Seung Lee 《Solid-State Circuits, IEEE Journal of》1994,29(4):509-515
This paper discusses fully digital error correction and self-calibration which correct errors due to capacitor mismatch, charge injection, and comparator offsets in algorithmic A/D converters. The calibration is performed without any additional analog circuitry, and the conversion does not need extra clock cycles. This technique can be applied to algorithmic converter configurations including pipelined, cyclic, or pipelined cyclic configurations. To demonstrate the concept, an experimental 2-stage pipelined cyclic A/D converter is implemented in a standard 1.6-μm CMOS process. The ADC operates at 600 ks/s using 45 mW of power at ±2.5 V supplies. The active die area excluding the external logic circuit is 1 mm2. Maximum DNL of ±0.6 LSB and INL of ±1 LSB at a 12-b resolution have been achieved 相似文献
2.
A single 5 V, 10 b, 50 MHz pipelined CMOS analog-to-digital (A/D) converter with internal sample-and-hold (S/H) circuits was developed. The A/D converter features a newly developed S/H circuit with an 80 dB, 300 MHz operational amplifier, three-stage pipelined 4 b flash A/D converters with digital error correction functions, and double analog signal conversion paths whose operations are interleaved. The new A/D converter was fabricated with 0.8 μm CMOS technology 相似文献
3.
Daisuke Miyazaki Shoji Kawahito 《Analog Integrated Circuits and Signal Processing》2000,25(3):235-244
This paper presents a new scheme of a low-power area-efficient pipelined A/D converter using a single-ended amplifier. The proposed multiply-by-two single-ended amplifier using switched capacitor circuits has smaller DC bias current compared to the conventional fully-differential scheme, and has a small capacitor mismatch sensitivity, allowing us to use a smaller capacitance. The simple high-gain dynamic-biased regulated cascode amplifier also has an excellent switching response. These properties lead to the low-power area-efficient design of high-speed A/D converters. The estimated power dissipation of the 10-b pipelined A/D converter is less than 12 mW at 20 MSample/s. 相似文献
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El-Sankary K. Sawan M. 《Circuits and Systems II: Express Briefs, IEEE Transactions on》2006,53(6):448-452
A digital background calibration technique to compensate for the nonlinearity and gain error in the sub-digital-to-analog converter (SDAC), and the operational amplifier finite dc gain in multibit/stage pipelined analog-to-digital converter (ADC) is proposed. By injecting subtractive calibration voltages in a modified conventional multibit multiplying DAC and performing correlation based successive coefficient measurements, a background calibration is performed. This calibration technique does not need an accurate reference voltage or an increasing in the SDAC resolution. A global gain correction essential for time-interleaved ADCs is presented. Simulation results show that in the presence of realistic capacitor and resistance mismatch and finite op-amp gain, this technique improves the linearity by several bits in single and multi-channel pipelined ADC. 相似文献
6.
The capacitor error-averaging technique, updated with look-ahead decision and digital correction, is used to demonstrate a 14-b 20-Msamples/s pipelined analog-to digital converter (ADC) with no trimming or calibration. The prototype ADC exhibits a differential nonlinearity (DNL) of +0.23/-0.28 least significant bit (LSB), an integral nonlinearity (INL) of +0.95/-1.06 LSB, a spurious-free dynamic range (SFDR) of 91.6 dB, and a signal-to-noise ratio (SNR) of 74.2 dB with a 1-MHz input and a 20-MHz clock. The prototype in 0.5-μm CMOS occupies an area of 4.5×2.4 mm2 and consumes 720 mW at 5 V 相似文献
7.
A modified RSD algorithm has been implemented in a switched-current pipelined A/D converter. The offset insensitivity of the RSD Converter reduces the effect of several nonidealities proper to current copier cells. Moreover, the benefits resulting from the large tolerances inherent to the RSD algorithm and the pipelined architecture result in an improved conversion rate. Measurements on a first prototype give an integral nonlinearity error less than 0.8 LSB for 10-bit accuracy. Power dissipation is 20 mW and silicon area is 2.5 mm2 . The measured sampling rate is 550 kS/s. It is an improvement by a factor of twenty compared to known equivalent CMOS switched-current converters. It is nevertheless still well below the predicted conversion rate of 4.5 MHz, which should be obtained once this A/D converter is integrated into an analog front-end. Full compatibility with standard digital technologies makes this kind of converter attractive for low power, medium-fast converters with 10-bit accuracy 相似文献
8.
A 6-bit 800-MS/s pipelined A/D converter (ADC) achieves SNDR and SFDR of 33.7 dB and 47.5 dB, respectively. Employing voltage-mode open-loop amplifiers in gain stages, global gain control techniques, and two-bank-interleaved architecture, the proposed pipelined A/D converter relaxes stringent design tradeoffs between speed and power. Fabricated in a 0.18-mum CMOS technology, the ADC consumes 105 mW from a 1.8-V power supply while the active area is only 0.5 mm2 相似文献
9.
This paper describes the design and implementation of a fully monolithic 16-b, 1 Msample/s, low-power A/D converter (ADC). An on-chip 32-b custom microcontroller calibrates and corrects the pipeline linearity to within 0.75 LSB integral nonlinearity (INL) and 0.6 LSB differential nonlinearity (DNL). High speed and low power are achieved using a pipelined architecture. Errors resulting from capacitor mismatches, finite op-amp open loop gain, charge injection and comparator offset are removed through self-calibration. Coefficients determined during calibration are stored on chip, digitally correcting the pipeline ADC in real time during normal conversion, Full-scale errors are removed through self-calibration and an-chip multiplication. Linearity errors due to capacitor voltage coefficients are reduced using a curve fit algorithm and on-chip ROM. Digital cross-talk errors resulting from the microcontroller running at a rate of ten times the analog sampling rate have prevented implementations of fully monolithic converters of this performance class in the past. Mismatches in cross-talk due to different digital timing between calibration and correction lead to linearity errors at critical correction points. Experimental analysis and circuit techniques which overcome these problems are presented 相似文献
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A floating-point approach can be used to extend the dynamic range of analog-to-digital (A/D) converters in applications where large signals need not be encoded with a precision greater than that required for small signals. Owing to the nonuniform nature of the quantization in a floating-point A/D converter (FADC), it is possible to sacrifice a large peak signal-to-noise ratio to obtain savings in power dissipation and area while achieving a large dynamic range. A 15-b switched-capacitor pipelined FADC has been designed with a 10-b mantissa and an exponent that provides an additional 5 bits of dynamic range. The increased dynamic range is obtained with a three-stage pipelined variable gain amplifier, while the mantissa is determined by a uniform 10-b pipelined A/D converter. An experimental prototype of the converter has been integrated in a 0.5 μm CMOS technology. It achieves a dynamic range of 90 dB at a conversion rate of 20 MSamples/s with a total power dissipation of 380 mW 相似文献
12.
《Solid-State Circuits, IEEE Journal of》1979,14(3):556-561
A single-chip A/D converter in p-channel MOS enhancement depletion-mode technology is presented, using a single-slope conversion technique. The analog part consists of a constant-current source and a comparator with internal digitally corrected offset. The A/D converter for a 3/SUP 1///SUB 2/-digit DVM can be operated with only two external components (integration capacitor and oscillator capacitor) and is mounted in a DIL 18 package. 相似文献
13.
El-Sankary K. Sawan M. 《Circuits and Systems II: Express Briefs, IEEE Transactions on》2004,51(10):507-510
A new digital background calibration technique to compensate for the capacitor mismatch in pipelined analog-to-digital converter (ADC) is presented. A digital signal from the ADC output is constructed so as to transform the capacitor mismatch to gain error. A simple modification to the conventional multiplying digital-to-analog converter (MDAC) allows the ADC to toggle between different configurations to create a reference signal used to calibrate blindly the ADC in the background. The creation of this signal does not produce any limitation for the ADC in terms of speed or degrading the input dynamic range. Simulation results show the effectiveness of this new method. 相似文献
14.
An 800-MHz low-power direct digital frequency synthesizer with an on-chip D/a converter 总被引:1,自引:0,他引:1
Byung-Do Yang Choi J.-H. Seon-Ho Han Lee-Sup Kim Hyun-Kyu Yu 《Solid-State Circuits, IEEE Journal of》2004,39(5):761-774
An 800-MHz low-power direct digital frequency synthesizer (DDFS) with an on-chip digital-to-analog (D/A) converter is presented. The DDFS consists of a phase accumulator, two phase-to-sine converters, and a D/A converter. The high-speed operation of the DDFS is enabled by applying parallelism to the phase-to-sine converter and by including a D/A converter in a single chip. The on-chip D/A converter saves delay and power consumption due to interchip interconnections. The DDFS considerably reduces power consumption by using several low-power techniques. The pipelined parallel accumulator consumes only 22% power of a conventional pipelined accumulator with the same throughput. The quad line approximation (QLA) and the quantization and error ROM (QE-ROM) minimize the ROM to generate a sine wave. The QLA saves 4 bits of the sine amplitude by approximating the sine function with four lines. The QE-ROM quantizes the ROM data by magnitude and address and then it stores the quantized values and the quantization errors separately. The ROM size for a 9-bit sine output is only 368 bits. A DDFS chip is fabricated in a 0.35-/spl mu/m CMOS process. It consumes only 174 mW at 800 MHz with 3.3 V. The chip core area is 1.47 mm/sup 2/. The spurious-free dynamic range (SFDR) is 55 dBc. 相似文献
15.
A pipelined, 13-bit, 250-ksample/s (ks/s), 5-V, analog-to-digital (A/D) converter has been designed and fabricated in a 3-μm, CMOS technology. Monotonicity is achieved using a reference-feedforward correction technique instead of (self-) calibration of trimming to minimize the overall cost. The prototype converter requires 3400 mil2, and consumes 15 mW 相似文献
16.
A 12-bit 20-Msample/s pipelined analog-to-digital converter with nested digital background calibration 总被引:3,自引:0,他引:3
A 12-bit 20-Msample/s pipelined analog-to-digital converter (ADC) is calibrated in the background using an algorithmic ADC, which is itself calibrated in the foreground. The overall calibration architecture is nested. The calibration overcomes the circuit nonidealities caused by capacitor mismatch and finite operational amplifier (opamp) gain both in the pipelined ADC and the algorithmic ADC. With a 58-kHz sinusoidal input, test results show that the pipelined ADC achieves a peak signal-to-noise-and-distortion ratio (SNDR) of 70.8 dB, a peak spurious-free dynamic range (SFDR) of 93.3 dB, a total harmonic distortion (THD) of -92.9 dB, and a peak integral nonlinearity (INL) of 0.47 least significant bit (LSB). The total power dissipation is 254 mW from 3.3 V. The active area is 7.5 mm/sup 2/ in 0.35-/spl mu/m CMOS. 相似文献
17.
分析了流水线A/D转换器采样电容与反馈电容之间的增益失配,探究了运放有限增益与流水线残差输出及A/D转换器输出的关系,建立了精确的系统模型。通过建立14位流水线A/D转换器Verilog-A的行为级模型,在数字域对流水线A/D转换器输出数字码进行分段平移。在第一级级间增益误差达到±0.012 5时,校正前信噪比仅为62 dB,校正后信噪比提升到85 dB。提出的校正方法可有效补偿由流水线级间增益导致的数字输出不连续和线性度下降。 相似文献
18.
A 1.8 V 12 bit 100 MS/s pipelined analog to digital converter(ADC) in a 0.18μm complementary metal-oxide semiconductor process is presented.The first stage adopts a 3.5 bit structure to relax the capacitor matching requirements.A bootstrapped switch and a scaling down technique are used to improve the ADC's linearity and save power dissipation,respectively.With a 15.5 MHz input signal,the ADC achieves 79.8 dB spurious-free dynamic range and 10.5 bit effective number of bits at 100 MS/s.The power consumpt... 相似文献
19.
Sourja Ray Bang-Sup Song 《Solid-State Circuits, IEEE Journal of》2007,42(3):463-474
Using statistical matching properties of capacitor arrays, a pipelined ADC self-configures the multiplying digital-to-analog converter (MDAC) capacitor array for best matching from many trial combinations of smaller capacitive sub-elements. These sub-elements having opposite error magnitudes are grouped together to form matched elements thus permitting an accurate multi-bit MDAC to be created without using an explicit trimming network. A random search algorithm enables the self-configuration process by quickly regrouping the sub-elements to reduce the spread between the reconstructed elements. The proposed state machine based permutation algorithm allows near unique permutations of the sub-elements and achieves a near unity state repetition ratio with a simple hardware implementation. An analog-to-digital converter (ADC) system is designed with the self-configuration algorithm contained in the same die, and improvement in capacitor matching is demonstrated after the self-configuration process. A 0.18-mum CMOS prototype achieves 13-b linearity and over 80-dB spurious-free dynamic range (SFDR) at 43 MS/s. The chip consumes 268 mW at 1.8 V and occupies 3.6 mm2 相似文献
20.
A 10-b 100-Msample/s pipelined subranging analog-digital converter (ADC) has been achieved. Such technologies as a pipelined subranging scheme, a track-and-hold amplifier (THA) with current-switching sampling gates, a 94-dB dc open-loop gain, a 335-MHz unity-gain frequency op amp, and a carry-look-ahead adder for digital error correction are presented. The 3.4-mm×5.6-mm ADC chip was fabricated using a 0.8-μm BiCMOS process and operates with 950-mW power dissipation from a single -5-V power supply 相似文献