A monostable CMOS RAM with self-refresh mode

A development of a new monostable CMOS RAM (MS/RAM) is described. A size of the MS/RAM cell, consisting of a monostable flip-flop and two interconnecting lines instead of a bistable model and three interconnecting lines, is extremely reduced. The static and dynamic behavior of the MS/RAM cell are discussed. Measurements and a computer simulation for the test device exhibited its superior performance in speed and power consumption with operating simplicity as compared with currently available large-scale memories. The test device with capacity equivalent to 1024-bit array showed an access time less than 60 ns, cycle time less than 120 ns, operating power of 40 mW, and standby power of 50 /spl mu/W in a 10-V operation. The principal advantage of MS/RAM is the static operating mode.     

A composite CMOS gate array with 4K RAM and 128K ROM

A unique gate array structure, called a composite gate array, incorporating a RAM and a ROM along with ordinary gate arrays, is described. The composite gate array consists of a 128K ROM, a 4K RAM, and a 6K gate array, and is developed using 1.6-/spl mu/m CMOS technology. The RAM and ROM are partitioned into four 1K and eight 16K blocks for increasing flexibility of memory configuration. A distributed arrangement of memory blocks is used to permit completely automatic writing using fewer channels. In circuit performance, gate delay time is 1.0 ns, RAM access time is 25 ns, and ROM access time is 30 ns. A communication control processor for personal computer networks is successfully designed to demonstrate the feasibility of the gate array.     

An 8K/spl times/8 bit static MOS RAM fabricated by n-MOS/n-well CMOS technology

A 64 kbit fully static MOS RAM which contains about 402500 elements on the chip area of 5.44/spl times/5.80 mm has been designed. The memory cell is a basic cross-coupled flip-flop with four n-MOSFETs and two polysilicon load resistors. The memory cell size is decreased to 16/spl times/19 /spl mu/m (304 /spl mu/m/SUP 2/) by using advanced n-MOS technology with double-level polysilicon films and photolithography of 2 /spl mu/m dimensions. By applying n-well CMOS technology fabricated on a high-resistivity p-type silicon substrate to peripheral circuits of the RAM, high performance characteristics with high speed access times and low power dissipation are obtained. The RAM is designed for single 5 V operation. Address and chip select access times are typically 80 ns. Power dissipation in the active and standby mode is typically 300 and 75 mW, respectively.     

A 70 ns high density 64K CMOS dynamic RAM

A 64K /spl times/ 1 CMOS dynamic RAM has been developed in a double-poly n-well CMOS technology with device scaling to the HMOS III level. A p-channel memory array with n-well protection reduced the operating soft error rate to less than one FIT. Periphery complexity is simplified due to CMOS circuits resulting in a size of 30,464 mil/SUP 2/ with a redundancy efficiency of 68%. The RAM has a typical access time of 70 ns and a CMOS standby power of 25 /spl mu/W. In addition, a static column design offers 35-ns data cycle time for high-bandwidth application.     

A gallium arsenide SDFL gate array with on-chip RAM

Describes a GaAs gate array with on-chip RAM based on the Schottky diode field-effect transistor logic (SDFL) technology. The array features 432 programmable SDFL cells, 32 programmable interface input-output (I/O) buffers, and four 4/spl times/4 bit static random access memories (RAM) on a 147 mil/spl times/185 mil chip. Each SDFL cell can be programmed as a NOR gate with as many as 8 inputs with a buffered or unbuffered output or as a dual OR-NAND gate with four inputs per side. The interface I/O buffer can be programmed for ECL, TTL, CMOS, and SDFL logic families. Each 4/spl times/4 bit RAM is fully decoded using SDFL circuits (depletion-mode MESFET). Preliminary results demonstrate the feasibility of GaAs SDFL for fast gate array and memory applications.     

A low power resistive load 64 kbit CMOS RAM

A fully asynchronous 8K word/spl times/8 bit CMOS static RAM with high resistive load cells is described. For fabricating the RAM, an advanced double polysilicon 2 /spl mu/m CMOS technology has been developed. Internally clocked dynamic peripheral circuits with address transition detectors are implemented to achieve high speed and low power simultaneously. A new CMOS fault-tolerant circuit technology is also introduced for improving fabrication yield without sacrificing operating speed or standby power. The resulting cell size and die size are 15/spl times/19 /spl mu/m and 4.87/spl times/7.22 mm, respectively. The RAM offers, typically, 70 ns access time, 15 mW operating power, and 10 /spl mu/W standby power.     

A 256K dynamic RAM with page-nibble mode

A 5-V 256K /spl times/ 1 bit NMOS dynamic RAM with page-nibble mode is designed and fabricated using 2-/spl mu/m design rules and folded bit-line configuration. Molybdenum disilicided polysilicon is used as the second-level gate to reduce the word-line signal delay. A large 98 /spl mu/m/SUP 2/ cell with Hi-C structure stores the signal charge of 210 fC and provides this memory with wide operating margin. The device is immune to voltage bumping and uses laser programmable redundancy. Typical RAS/CAS access times are 80 ns/40 ns. An average operating current of 50 mA with 80 mA peak at 230 ns cycle time and standby current of 2 mA are achieved.     

New input/output designs for high speed static CMOS RAM

New input and output schematics and optimum design for cell and array are proposed, and applied to a 256/spl times/4 bit CMOS static RAM. Simplified decoder circuit with effective decoder control circuit has a high speed and a wide timing margin. Simple sense amplifier and compact output circuit bring higher speed and reduction in pattern area. Using p-channel transfer gate for memory cell and array, the switching speed and operational stability are much improved. The device is fabricated by 5 /spl mu/m layout rule Si-gate CMOS technology. An 80 ns access time and 100 ns minimum cycle time are acquired at 5 V supply. Power dissipation is less than 7.5 mW at 1 MHz operation.     

A Hi-CMOSII 8K/spl times/8 bit static RAM

A Hi-CMOSII static RAM with 8K word by 8 bit organization has been developed. The RAM is fabricated using double polysilicon technology and p- and n-channel transistors having a typical gate polysilicon length of 2 /spl mu/m. The device was realized using low-power high-speed-oriented circuit design and a new redundancy circuit that utilizes laser diffusion programmable devices. The new RAM has an address access time of 65 ns, operating power dissipation of 200 mW, and standby dissipation of 10 /spl mu/W.     

Fully boosted 64K dynamic RAM with automatic and self-refresh

A novel high-speed low-power 64K dynamic RAM with enough margin has been attained using a double polysilicon and 3-/spl mu/m process technologies. To obtain a low soft error rate below 1/spl times/10/SUP -6/ errors per device hour without sacrificing the high-speed and low-power operation, some novel approaches are proposed in the circuit and device designs. In particular, fully boosted circuits and the Hi-C cell structure with polysilicon bit line are designed to increase the margin of the single 5-V power supply 64K dynamic RAM. The fabricated device provides a typical access time of 90 ns and an operating power of 190 mW at 25/spl deg/C. Also, the design features of the automatic and self-refresh functions on the same chip are described.     

100-Gb/s multiplexing and demultiplexing IC operations in InP HEMT technology

This paper describes the 100-Gb/s multiplexing operation of a selector IC and demultiplexing operation of a D-type flip-flop (D-FF) using production-level 0.1-/spl mu/m-gate-length InP HEMT IC technology. To boost the operating speed of the selector IC, a selector core circuit directly drives an external 50-/spl Omega/ load, and is included in the output stage. In addition, a test chip containing the selector and a D-FF to confirm error-free operation of these circuits was designed. The fabricated selector IC exhibited clear eye openings at 100 Gb/s, and its error-free operation was confirmed by using the test chip.     

A 20 K GaAs array with 10 K of embedded SRAM

A 20000-gate GaAs array with 10 K of embedded RAM is presented. The array contains eight scannable fully registered 256×256 RAM macros which have a minimum cycle time of 3.5 ns. The RAM features a scan mode, which can be used to configure the registers into a serial shifter. There is also a RAM test mode which allows independent functional and speed testing of all eight RAMs, easing the task of RAM verification for a given user personalization. The RAM array was fabricated using an advanced high-performance GaAs semiconductor E /D MESFET process featuring self-aligned gates and requiring only 12 masks. Introductory discussion of the Vitesse GaAs process, basic GaAs MESFET characteristics, and GaAs circuit design are provided. The gate array portion contains 20736 user-configurable cells with 10-ps gate delays which are tailored for direct-coupled FET logic (DCFL). The I/O can be personalized for ECL, TTL, or GaAs levels. There are 392 pads on the 13.8-mm×7.7-mm die with a maximum of 256 used for signal I/O. The RAM array is packaged in a multilayer ceramic 344-pin leaded chip carrier (LDCC). Typical power dissipation at 80% utilization is 14 W     

A 21-ns 32 K/spl times/8 CMOS static RAM with a selectively pumped p-well array

The design and performance of a 32 K/spl times/8-b CMOS static RAM (SRAM) are presented. The design features a selectively pumped p-well array. Using this array technology, high-impedance polysilicon resistor loads can be used to reduce the array standby current by three orders of magnitude, and the device characteristics can be optimized to achieve high speed in the peripheral circuits. A unique divided-word-line architecture with shared sense amplifiers is used to achieve high-speed read operation. The read speed is further enhanced by a novel quasistatic equalization that minimizes peak current. A high-speed write circuit with a write-to-read transition detection is used to achieve a fast write operation. An advanced 1.2-/spl mu/m double-level-metal CMOS technology was used to fabricate the devices. The access time is 21 ns and the active power is 330 mW at 22 MHz.     

A high speed molybdenum gate MOS RAM

Describes a high speed 16K molybdenum gate (Mo-gate) dynamic MOS RAM using a single transistor cell. New circuit technologies, including a capacitive-coupled sense-refresh amplifier and a dummy sense circuit, enable the achievement of high speed performance in combination with reduced propagation delay in the molybdenum word line due to the low resistivity. The n-channel Mo-gate process was established by developing an evaporation apparatus and by an improved heat treatment to reduce surface charge density. Ultraviolet photolithography for 2 /spl mu/m patterns and HCl oxidation for 400 /spl Aring/ thick gate oxide are used. The 16K word/spl times/1 bit device is fabricated on a 3.2 mm/spl times/4.0 mm chip. Cell size is 16 /spl mu/m/spl times/16 /spl mu/m Access time is less than 65 ns at V/SUB DD/=7 V and V/SUB BB/=-2 V. Power dissipation is 210 mW at 170 ns read-modify-write (RMW) cycle.     

A 35 ns 16K NMOS static RAM

An NMOS 16K/spl times/1 bit fully static MOS RAM with 35 ns access time has been successfully developed. High speed access time was achieved by the combination of an NMOS process with the 2.2 /spl mu/m gate length transistor, high speed sense amplifier, and reduction on delay time at the crossunder. The improvements of row and column decoder circuits result in the low active and standby power dissipation of 275 mW and 22.5 mW, respectively. The soft error rate of the poly load cell was minimized by reducing the collection efficiency of alpha-particle induced electrons.     

A low-power sub 100 ns 256K bit dynamic RAM

A 256K-word /spl times/ 1-bit NMOS dynamic RAM using 2-/spl mu/m design rules and MoSi/SUB 2/ gate technology is described. A marked low-power dissipation of 170 mW (5 V V/SUB cc/, 260-ns cycle time) has been achieved by using a partial activation scheme. Optimized circuits exhibit a typical CAS access time of 34 ns. For the purpose of optimizing circuit parameters, an electron beam tester was successfully applied to observe the internal timing of real chips. Laser repairable redundancy with four spare rows and four spare columns is implemented for yield improvement.     

A GaAs 1K static RAM using tungsten silicide gate self-aligned technology

This paper reports a GaAs 1K static RAM, fabricated using tungsten silicide gate self-aligned technology with full ion implantation. With 2-/spl mu/m gate length, an address access time of 3.6 ns and a minimum write-enable pulse width of 1.6 ns were achieved with a power dissipation of 68 mW. The access time compares favorably to those of currently reported high-speed Si bipolar memories, and the greatly decreased power dissipation is better by one order of magnitude. An address access time of 0.88 ns can be achieved by shortening the gate length to 1 /spl mu/m and adopting a 2-/spl mu/m design rule in the layout.     

1-Mbit virtually static RAM

The 1-Mb RAM utilizes a one-transistor, one-capacitor dynamic memory cell. Since all the refresh-related operations are done on chip, the RAM acts as a virtually static RAM (VSRAM). The refresh operations are merged into the normal operation, called a background refresh, the main feature of the VSRAM. Since the fast operation of the core part of the RAM is crucial to minimize the access-time overhead by the background refresh, 16 divided bit lines and parallel processing techniques are utilized. Novel hot-carrier resistant circuits are applied selectively to bootstrapped nodes for high hot-carrier reliability. N-channel memory cells are embedded in a p-well, which gives a low soft error rate of less than 10 FIT. 1-/spl mu/m NMOSFETs with moderately lightly doped drain structures offer fast 5-V operation with sufficient reliability. An advanced double-level poly-Si and double-level Al twin-well CMOS technology is developed for fast circuit speed and high packing density. The memory cell size is 3.5/spl times/8.4 /spl mu/m/SUP 2/, and the chip size is 5.99/spl times/13.8 mm./SUP 2/. Address access time is typically 62 ns, with 21-mA operating current and 30-/spl mu/A standby current at room temperature.     

A 209 K-transistor ECL gate array with RAM

A 12 K-gate ECL gate array with 36 kbit of dedicated RAM has been developed. An ECL logic cell structure with an extra transistor buried under a V/sub cc/ power bus is proposed to implement both the logic function and a memory cell. The logic part has the capability of implementing configurable RAM with up to 5.8 kbit. By employing 0.6- mu m double-polysilicon self-aligned technology, the intrinsic gate delay is 110 ps at a power consumption of 1.8 mW/gate. The address access times of dedicated RAM and configurable RAM are 3.0 and 1.8 ns, respectively. The gate array is applied to 9 K-gate logic circuitry with 35-kbit table look-aside buffer (TLB) memory using dedicated RAM and a 16-word*18-bit register file using configurable RAM.<>     

An 86 K component bipolar VLSI masterslice with a 290-ps loaded gate delay

A very large-scale integrated (VLSI) bipolar masterslice has been demonstrated. This masterslice has a loaded three-input ECL gate delay of 290 ps and an unloaded gate delay of 164 ps at a power dissipation of 1.5 mW/gate. It is fabricated by using 1.5-/spl mu/m rule super self-aligned process technology (SST), 2-/spl mu/m-wide deep U-groove isolation, and a fine 5-/spl mu/m pitch three-level metallization process. The authors describe its process features, cell design, chip structure, experimental results, and applications.