An auto-calibrated,dual-mode SRAM macro using a hybrid offset-cancelled sense amplifier

A dual-mode power and performance optimized SRAM is presented. Given the fact that the power and speed associated with the cell access time are directly related to the sense amplifier offset a new optimization platform based on the hybrid offset-cancelled current sense amplifier (OCCSA) [1] is presented. It is shown that the speed and power overhead of the offset cancellation can be optimized in a multi-variable auto-calibration loop to achieve the lowest power or the highest performance mode. The flexibility of having two degrees of freedom in OCCSA offers a significant bitline delay reduction with minimum power sacrifice in the high performance mode. The proposed scheme is verified using a macro cell implemented in a 0.18 μm CMOS technology. In the Power Optimized mode, a wide range of offset is applied to a single column test structure and 25% energy consumption reduction is measured compared to the conventional case. For a 32 kb SRAM array, compared to a conventional sense amplification, a 2X reduction in energy consumption is achieved in the Energy Optimized mode. Thanks to the offset cancelling nature of the proposed scheme, a 2X improvement in cell access time is achieved in the Speed Optimized mode.     

A 0.65-ns, 72-kb ECL-CMOS RAM macro for a 1-Mb SRAM

An ultrahigh-speed 72-kb ECL-CMOS RAM macro for a 1-Mb SRAM with 0.65-ns address-access time, 0.80-ns write-pulse width, and 30.24-μm ² memory cells has been developed using 0.3-μm BiCMOS technology. Two key techniques for achieving ultrahigh speed are an ECL decoder/driver circuit with a BiCMOS inverter and a write-pulse generator with a replica memory cell. These circuit techniques can reduce access time and write-pulse width of the 72-kb RAM macro to 71% and 58% of those of RAM macros with conventional circuits. In order to reduce crosstalk noise for CMOS memory-cell arrays driven at extremely high speeds, a twisted bit-line structure with a normally on MOS equalizer is proposed. These techniques are especially useful for realizing ultrahigh-speed, high-density SRAM's, which have been used as cache and control storages in mainframe computers     

Circuit techniques for a 25 ns 16K/spl times/1 SRAM using address-transition detection

The authors describe special circuit techniques that have been used to produce a 25-ns HMOS 16K/spl times/1 SRAM. In particular, a new dynamic row-decoder driver, hold-valid-data output driver, and column-decoder driver have been developed. A new memory clear function, called the bulk-write feature, that writes all data locations to the same data as the data-in pin in one long (/spl sime/700 ns) write cycle was also developed. This 16K/spl times/1 SRAM has a die area of 25.3K mil/SUP 2/ (16.3 mm/SUP 2/), and was fabricated using a 2-/spl mu/m double-polysilicon NMOS technology.     

A 1-V TFT-load SRAM using a two-step word-voltage method

A 1-V SRAM using a TFT load cell was developed. Key circuits for obtaining the low-voltage operation are a two-step word-voltage (TSW) method, a submicroampere boosted-level generator using a multivibrator, and a sense amplifier using low-threshold MOSFETs. An access time of 250 ns and a standby current of 0.23 μA were achieved for a 4-kb test chip using a 10.2-μm² TFT-load cell. This technology is applicable for high-density and single-battery operational SRAMS     

一种基于准浮栅技术的0.6V,2.4GHz CMOS混频器

讨论分析了准浮栅晶体管的工作原理、电气特性及其等效电路.基于准浮栅NMOS晶体管,对Gilbert混频器电路结构进行改进设计,实现了超低压混频器.基于TSMC 0.25μm CMOS工艺的BSIM3V3模型,采用Hspice对混频器进行了仿真,仿真结果显示,该混频器在0.6V的单电源电压下,仍可以对2.4GHz的正弦信号进行混频,转换增益为-21.8dB,三阶输入截止点的值为34.6dB.     

A configurable DRAM macro design for 2112 derivative organizationsto be synthesized using a memory generator

This paper describes a DRAM macro design from which 2112 configurations up to 32 Mb can be synthesized using a memory generator. The memory generator automatically creates the layout of a DRAM macro in accordance with specification inputs such as memory capacity, address count, bank count, and I/O bits count. An expandable floor layout scheme achieves the macro size comparable to that of handicraft-designed DRAM. The memory generator can customize a configurable redundancy scheme for various macro configurations. Unified testing circuits make it possible to test DRAM macros with more than 500 interface pins in a direct-memory-access mode with 33 test pads. Up to four macros on the same chip can be tested with them. Test chips with 4-Mb DRAM and with 20-Mb DRAM fabricated with 0.35-μm technology showed 150-MHz operation     

A new dynamic random access memory cell using a bipolar MOS composite structure

A new dynamic random access memory (RAM) cell which incoperates an n-p-n bipolar junction transistor with an n-channel MOSFET in a composite structure, is proposed and investigated. In this novel cell called the BIMOS cell, the collector-base junction serves as a buried storage capacitor whereas the n-MOSFET as a transfer gate. The fabrication technology is simple and compatible with that of single-polysilicon CMOS IC's and a minimum cell size of 14.875F²with a minimum feature sizeFis realizable. The write, read, and standby operations of the cell are analyzed and simulated. An experimental cell is fabricated and characterized. Dynamic test is successfully performed. The investigation on the cell performance is also made. It has shown that large storage capacitance to bit-line capacitance ratio as well as fairly good packing density, soft-error immunity and leakage characteristics are expected. Furthermore, as compared to the conventional 1-transistor cell the new cell can be scaled down with less processing troubles and better performance improvements. Simple process and good scaled-down properties offer great potential for the proposed new cell to be used in the design of larger dynamic MOS RAM's.     

A 0.2 V, 480 kb Subthreshold SRAM With 1 k Cells Per Bitline for Ultra-Low-Voltage Computing

A 2 muW, 100 kHz, 480 kb subthreshold SRAM operating at 0.2 V is demonstrated in a 130 nm CMOS process. A 10-T SRAM cell allows 1 k cells per bitline by eliminating the data-dependent bitline leakage. A virtual ground replica scheme is proposed for logic "0" level tracking and optimal sensing margin in read buffers. Utilizing the strong reverse short channel effect in the subthreshold region improves cell writability and row decoder performance due to the increased current drivability at a longer channel length. The sizing method leads to an equivalent write wordline voltage boost of 70 mV and a delay improvement of 28% in the row decoder compared to the conventional sizing scheme at 0.2 V. A bitline writeback scheme was used to eliminate the pseudo-write problem in unselected columns.     

A 2-ns cycle, 3.8-ns access 512-kb CMOS ECL SRAM with a fullypipelined architecture

The authors describe a 512 K CMOS static RAM (SRAM) with emitter-coupled-logic (ECL) interfaces which has a 2-ns cycle time and a 3.8-ns access time, both of which are valid for random READ/WRITE operations. The CMOS technology and the physical organization of the chip are briefly discussed, and the pipelined architecture of the chip is described. Detailed measurements of internal chip waveforms demonstrating 2-ns cycle time operation are presented. The impact of wire RC delays on performance is discussed. Circuit examples that demonstrate the implementation of the pipelined architecture are included. Measurements of operating margins, access time, and cycle time are outlined     

A 12-ns ECL I/O 256 K×1-bit SRAM using a 1-μm BiCMOStechnology

An ECL (emitter-coupled-logic) I/O 256K×1-bit SRAM (static random-access memory) has been developed using a 1-μm BiCMOS technology. The double-level-poly, double-level-metal process produces 0.8-μm CMOS effective gate lengths and polysilicon emitter bipolar transistors. A zero-DC-power ECL-to-CMOS translation scheme has been implemented to interface the ECL periphery circuits to the CMOS decode and NMOS matrix. Low-impedance bit-line loads were used to minimize read access time. Minimization of bit-line recovery time after a write cycle is achieved through the use of a bipolar/CMOS write recovery method. Full-die simulations were performed using HSPICE on a CRAY-1     

A 1 Gbit synchronous dynamic random access memory with anindependent subarray-controlled scheme and a hierarchical decodingscheme

A prototype 1 Gbit synchronous DRAM with independent subarray-controlled isolation and hierarchical decoding schemes is demonstrated to alleviate the difficulties encountered in high-density devices with regard to failure analysis and performance optimization. The scheme to isolate memory arrays from “hard” defects and to overcome the dc leakages of “soft” defects with external sources allows monitoring of the leakage current for the defect analysis and testing of the device without being limited by the capabilities of on-chip voltage sources. A hierarchical decoding scheme with a dynamic CMOS series logic predecoder achieves improvements in circuit speed, power, and complexity. As a result, evaluation of the prototype devices can be facilitated, and the optimized circuit schemes achieve enhanced circuit performance. A fully working 1 Gbit synchronous DRAM with a chip size of 570 mm² was fabricated using a 0.16 μm CMOS process and tested for excellent functionality up to 143 MHz     

A 2.5-V active low-pass filter using all-n-p-n Gilbert cells with a1-Vp-p range

This paper describes the design and measured results of an all-n-p-n low-voltage (2.5 V), low-current (1 mA), large-swing (1 V_p-p), low-distortion (-53 dB, 1 V_p-p) active filter using a conventional bipolar process. The transconductors for the filter are composed of Gilbert cell transconductors. Distortion has been improved by feedback circuits without increasing the supply voltage and without using p-n-p transistors. The filter is a gyrator-capacitor type third-order Butterworth low-pass filter with a nominal cutoff frequency of 192 kHz. A voltage scaling technique has been applied directly to the gyrator-capacitor filter. This has improved the signal-to-noise ratio by 3 dB. Simulation results indicated that a fast operation up to tens of MHz is possible with a standard bipolar process, as the signal path is composed only of n-p-n transistors     

A -119.2 dBc/Hz at 1 MHz, 1.5 mW, fully integrated, 2.5-GHz, CMOS VCO using helical inductors

This letter presents an implementation to reduce area occupation in designing voltage-controlled oscillators (VCOs) using a filtering technique. We applied a helical inductor to the noise filter in a 2.5-GHz CMOS VCO to reduce area occupation. Because a helical inductor has less area occupation, a small silicon area was achieved. This VCO operates in the 2.5-GHz band with power consumption of 1.5 mW and phase noise of -119.2 dBc/Hz at 1-MHz. Our VCO displays an excellent performance of phase noise in relation to power consumption.     

负阻负载和复制运放增益增强技术相结合的低电压低功耗高增益端到端输出范围运算放大器

设计了一种低电压低功耗高增益端到端运算放大器.为了提高运放的直流增益,采用了复制运放增益增强技术,这种技术的特点是在提高增益的同时不影响输出摆幅,非常适合低电压场合.该运放采用0.18μm标准CMOS工艺,工作电压为1V.仿真结果表明,在5pF负载电容下所获得运放的直流增益达到65.9dB,增益带宽积为70.28MHz,相位裕度为50°,静态功耗为156.7μW.     

负阻负载和复制运放增益增强技术相结合的低电压低功耗高增益端到端输出范围运算放大器

设计了一种低电压低功耗高增益端到端运算放大器.为了提高运放的直流增益,采用了复制运放增益增强技术,这种技术的特点是在提高增益的同时不影响输出摆幅,非常适合低电压场合.该运放采用0.18μm标准CMOS工艺,工作电压为1V.仿真结果表明,在5pF负载电容下所获得运放的直流增益达到65.9dB,增益带宽积为70.28MHz,相位裕度为50°,静态功耗为156.7μW.     

A 0.5-μm, 3-V 1T1C, 1-Mbit FRAM with a variable referencebit-line voltage scheme using a fatigue-free reference capacitor

A 0.5-μm, 3-V operated, 1TIC, 1-Mbit FRAM with 160-ns access time has been developed. In FRAM, a reference voltage design using a ferroelectric capacitor is difficult because of the degradation due to fatigue, a chip-to-chip variation, and a temperature dependence. A variable reference voltage scheme is generated to solve this problem, boosting a fatigue-free and temperature-independent MOS reference capacitance by a driver. The driver is operated from a compact reference voltage generator that provides 32 equally divided voltages and occupies only half the layout area of a conventional one. During sense operation, memory-cell capacitance C_ferr is larger than reference-cell capacitance C_MOS. A double word-line pulse scheme has also been developed to eliminate a bit-line capacitance imbalance in the bit-line pairs, where a memory cell and a reference cell are separated from the bit-line pairs during sense operation. A six-order improvement in imprint lifetime has been achieved by the new scheme     

A.2.5 GHz-spaced 1080-channel tandem multi/demultiplexer coveringthe. S-, C-, and L-bands using an arrayed-waveguide grating withGaussian passbands as a primary filter

We describe a low-loss 25-GHz-spaced multi/demultiplexer with more than 1000 channels that covers the S-, C-, and L-bands of optical fiber amplifiers. It was achieved by cascading a 2.5-THz-spaced arrayed-waveguide grating (AWG) with Gaussian passbands as a primary filter and ten 25-GHz-spaced 1×200 AWGs as secondary filters in a tandem configuration     

A 1-V, 100-MHz, 10-mW cache using a separated bit-line memoryhierarchy architecture and domino tag comparators

A 1-V 16-KB (L2) 2-KB (L1) four-way set-associative cache was fabricated using a 0.25-μm CMOS technology for future low-power high-speed microprocessors. Effective latency of 6.9 ns and power consumption of 10 mW at 100 MHz are obtained at a supply voltage of 1 V. This performance is achieved by using a new separated bit-line memory hierarchy architecture (SBMHA) that speeds up latency and reduces power consumption, and domino tag comparators (DTC's) that reduce the power dissipation of tag comparisons