用于MEMS结构的光刻胶牺牲层接触平坦化技术

实验研究一种新颖的光刻胶牺牲层的接触平坦化(contact planarization)技术,应用于MEMS结构制作.实验研究了温度与光刻胶流动性的关系,以及牺牲层厚度、施加压力和温度、MEMS结构密度等因素对平坦化效果的影响,在优化条件下,牺牲层的起伏台阶从2μm减小到20～40nm.与化学机械抛光技术相比,接触平坦化无明显凹陷(Dishing)效应,无衬底损伤,同时呈现出良好的局部和总体均匀性.     

气体离化团束对表面的平坦化及清洁化效果

用原子力显微镜测量了气体离化团束照射后表面粗糙度的变化。已经证实气体团束轰击对表面沾污具有很高的清除率，同时却引起较低的损伤。气体离化团束优良的平坦化和清洁化效果可能与照射中多体碰撞、侧向溅射及高能量密度的沉积相关。     

碱性Cu布线抛光液速率特性及平坦化性能的研究

Cu的双大马士革工艺加上化学机械平坦化(CMP)技术是目前制备Cu布线行之有效的方法。CuCMP制程中,抛光液起着至关重要的作用,针对目前国际主流酸性抛光液存在的问题和Cu及其氧化物与氢氧化物不溶于水的难题,研发了多羟多胺碱性Cu布线抛光液,研究了此抛光液随压力、转速及流量变化的特性,同时也研究了其对布线片的平坦化能力。结果表明,抛光液对Cu的去除速率随压力的增大而显著增大,随转速及流量的增加,Cu的去除速率增大缓慢,显著性依次为压力转速>流量。通过对Cu布线抛光实验表明,此抛光液能够实现多种尺寸Cu线条的平坦化。说明研发的碱性抛光液能够实现Cu布线抛光后产物可溶,且不含抑制剂等,能够实现布线片的平坦化。     

微电子材料化学机械平坦化加工中的材料去除率模型

采用有限元数值方法分析微电子材料化学机械平坦化(CMP)工艺过程中材料的变形和去除机理,得到作用在磨料颗粒上的力与名义压力、磨粒含量以及垫板几何和力学特性之间的关系,进而建立起一个材料去除率(MRR)模型。利用该模型预测得到的材料去除率与悬浮液中磨料颗粒含量以及压力间的关系与已有的实验结果相吻合,合理解释了实验观察到的现象。     

低压下碱性铜抛光液对300mm多层铜布线平坦化的研究

随着微电子技术进一步发展,低k介质的引入使得铜的化学机械平坦化(CMP)须在低压下进行。提出了一种新型碱性铜抛光液,其不含常用的腐蚀抑制剂,并研究了其在低压下抛光及平坦化性能。静态条件下,铜的腐蚀速率较低仅为2nm/min。在低压10.34kPa时,铜的平均去除速率可达633.3nm/min,片内非均匀性(WIWNU)为2.44%。平坦化效率较高,8层铜布线平坦化结果表明,60s即可消去约794.6nm的高低差,且抛光后表面粗糙度低(0.178nm),表面状态好,结果表明此抛光液可用于多层铜布线的平坦化。     

H_2O_2在精抛过程中对铜布线平坦化的影响

采用自主研发的碱性铜抛光液,使用前稀释50倍加入不同剂量H2O2配制成碱性铜精抛液。实验结果表明,随着H2O2含量的增加,铜的静态腐蚀速率(CuDR)、抛光速率(CuPR)以及阻挡层Ta/TaN均有小幅度的降低,但在MIT854布线片上精抛实验结果表明,碟形坑随着H2O2含量的增加逐渐降低,加入5%(体积分数)H2O2的精抛液,在粗抛实现初步平坦化后,精抛去除残余铜的过程中,能够实现不同线条尺寸的完全平坦化,碟形坑在工业要求范围内。研究结果表明,H2O2含量的增加对速率影响不明显,但有利于铜布线片的平坦化。此规律对提高CMP全局平坦化具有极重要的作用。     

Challenges in Atomic-Scale Characterization of High-k Dielectrics and Metal Gate Electrodes for Advanced CMOS Gate Stacks

The decreasing feature sizes in complementary metal-oxide semiconductor (CMOS) transistor technology will require the replacement of SiO2 with gate dielectrics that have a high dielectric constant (high-k) because as the SiO2 gate thickness is reduced below 1.4 nm, electron tunnelling effects and high leakage currents occur in SiO2, which present serious obstacles to future device reliability.In recent years significant progress has been made on the screening and selection of high-k gate dielectrics, understanding their physical properties, and their integration into CMOS technology.Now the family of hafnium oxide-based materials has emerged as the leading candidate for high-k gate dielectrics due to their excellent physical properties.It is also realized that the high-k oxides must be implemented in conjunction with metal gate electrodes to get sufficient potential for CMOS continue scaling.In the advanced nanoscale Si-based CMOS devices, the composition and thickness of interfacial layers in the gate stacks determine the critical performance of devices.Therefore, detailed atomicscale understandings of the microstructures and interfacial structures built in the advanced CMOS gate stacks,are highly required.In this paper, several high-resolution electron, ion, and photon-based techniques currently used to characterize the high-k gate dielectrics and interfaces at atomic-scale, are reviewed.Particularly, we critically review the research progress on the characterization of interface behavior and structural evolution in the high-k gate dielectrics by high-resolution transmission electron microscopy (HRTEM) and the related techniques based on scanning transmission electron microscopy (STEM), including high-angle annular darkfield (HAADF) imaging (also known as Z-contrast imaging), electron energy-loss spectroscopy (EELS), and energy dispersive X-ray spectroscopy (EDS), due to that HRTEM and STEM have become essential metrology tools for characterizing the dielectric gate stacks in the present and future generations of CMOS devices.In Section 1 of this review, the working principles of each technique are briefly introduced and their key features are outlined. In Section 2, microstructural characterizations of high-k gate dielectrics at atomic-scale by electron microscopy are critically reviewed by citing some recent results reported on high-k gate dielectrics.In Section 3, metal gate electrodes and the interfacial structures between high-k dielectrics and metal gates are discussed.The electron beam damage effects in high-k gate stacks are also evaluated, and their origins and prevention are described in Section 4.Finally, we end this review with personal perspectives towards the future challenges of atomic-scale material characterization in advanced CMOS gate stacks.     

金属基复合材料研究新进展

新材料的研究、发展及应用是当代高新技术的重要内容之一。金属基复合材料因具有较高的比强度、比刚度,优良的导电导热性,以及高韧性和高抗冲击性而对促进世界各国军用和民用领域的高新科技现代化,起到了至关重要的作用。文章简单综述了金属基复合材料的分类、制备新工艺及应用,并探讨了金属基复合材料的研究方向。     

EAST锂化系统的优化及其对等离子体性能的影响

为提高锂膜在先进实验超导托卡马克 (EAST) 内真空室器壁上的均匀性, 从而提高锂膜对再循环的控制, 对杂质的抑制能力, 优化设计了新型三孔蒸发型坩埚, 并成功的用于锂化壁处理实验。实验表明, 锂膜在内真空室器壁上更加均匀, 坩埚附近没有出现明显的锂膜起皮现象, 下石墨偏滤器得到有效的覆盖。锂膜均匀性的提高, 有效的提升了初次锂化壁处理对控制再循环, 抑制杂质的能力, 同时也延长了锂膜的寿命。为了恢复内真空室第一壁上退化锂膜的性能, 优化设计了一套新型炮间锂化系统。新型炮间锂化系统成功在等离子体放电间隙开展了锂化壁处理, 挡板开启后, 锂蒸气成功注入到内真空室中, 有效地抑制了等离子体放电中的再循环水平、杂质含量及总辐射功率。     

表面强化技术在金属材料中的发展趋势

本文介绍了表面工程及表面强化的概念及分类，概述了其在金属材料中的应用，并阐明了其发展方向及前景。     

应用于等离子体破裂防护的双涡流驱动快速充气阀的研制

为了满足在EAST装置上开展高压气体注入缓解等离子体破裂实验研究需求,在单涡流驱动快速充气阀成功研制的基础上又研制成功了双涡流驱动快速充气阀。该快速充气阀由双涡流线圈驱动,且增加了一套可调节阀芯预紧力的弹簧预紧背压系统,双线圈驱动结构的采用使得阀体的体积更加小巧,同时阀体的开启性能更加优越;弹簧背压预紧系统使用,使得充气阀的工作安全性大为提高。经过平台测定,该充气阀的开启响应时间不大于0.15 ms,而通过选择合适的工作参数可以使快阀的整个开启脉冲周期控制在2 ms以内;而通过调节工作参数(气压和电压),充气阀在2 ms内的充气总量可以很方便的在0~10~(23)粒子数之间调节。该阀的成功研制为EAST装置开展等离子体破裂缓解研究提供了更加有效的杂质气体注入工具,该阀将应用于2014年秋季的EAST物理实验研究。