Design of synthetic biological logic circuits based on evolutionary algorithm

The construction of an artificial biological logic circuit using systematic strategy is recognised as one of the most important topics for the development of synthetic biology. In this study, a real‐structured genetic algorithm (RSGA), which combines general advantages of the traditional real genetic algorithm with those of the structured genetic algorithm, is proposed to deal with the biological logic circuit design problem. A general model with the cis ‐regulatory input function and appropriate promoter activity functions is proposed to synthesise a wide variety of fundamental logic gates such as NOT, Buffer, AND, OR, NAND, NOR and XOR. The results obtained can be extended to synthesise advanced combinational and sequential logic circuits by topologically distinct connections. The resulting optimal design of these logic gates and circuits are established via the RSGA. The in silico computer‐based modelling technology has been verified showing its great advantages in the purpose.Inspec keywords: biocomputing, biological techniques, combinational circuits, genetic algorithms, logic design, logic gates, sequential circuitsOther keywords: in silico computer‐based modelling, RSGA, sequential logic circuits, XOR gates, NOR gates, NAND gates, OR gates, AND gates, Buffer gates, NOT gates, fundamental logic gates, cis‐regulatory input function, real‐structured genetic algorithm, artiflcial biological logic circuit design     

Effect of glitches against masked AES S-box implementation and countermeasure

Masking of gates is one of the most popular techniques to prevent differential power analysis (DPA) of AES algorithm. It has been shown that the logic circuits used in the implementation of cryptographic algorithms leak side-channel information inspite of masking, which can be exploited, in differential power attacks. The phenomenon in CMOS circuits responsible for the leakage of masked circuits is known as glitching. Motivated by this fact, the authors analyse the effect of glitches in CMOS circuits against masked implementation of the AES S-box. The authors explicitly demonstrate that glitches do not affect always. There exists a relation between combinational path delay of the circuit and timing difference of input vectors to the circuit, which has a bearance on the amount of information leaked by the masked gates. A balanced masked S-box circuit is proposed where the inputs are synchronised by sequential components. Detailed SPICE results are shown to support the claim that the modifications indeed reduce the vulnerability of the masked AES S-box against DPA attacks.     

Analysis of Energy Quantization Effects on Single-Electron Transistor Circuits

In this paper, the effects of energy quantization on different single-electron transistor (SET) circuits (logic inverter, current-biased circuits, and hybrid MOS-SET circuits) are analyzed through analytical modeling and Monte Carlo simulations. It is shown that energy quantization mainly increases the Coulomb blockade area and Coulomb blockade oscillation periodicity, and thus, affects the SET circuit performance. A new model for the noise margin of the SET inverter is proposed, which includes the energy quantization effects. Using the noise margin as a metric, the robustness of the SET inverter is studied against the effects of energy quantization. An analytical expression is developed, which explicitly defines the maximum energy quantization (termed as “ quantization threshold”) that an SET inverter can withstand before its noise margin falls below a specified tolerance level. The effects of energy quantization are further studied for the current-biased negative differential resistance (NDR) circuit and hybrid SETMOS circuit. A new model for the conductance of NDR characteristics is also formulated that explains the energy quantization effects.      

数字电路可测性设计的一种故障定位方法

在逻辑函数ReedMuller模式的电路可测性设计方面，文章采用AND门阵列和XOR门树结构来设计电路，提出了一种设计方案，可实现任意逻辑函数的功能，而且所得电路具有通用测试集和完全可故障定位的特点。给出了进行故障定位的方法，并可把它应用于其他相关电路的可测性设计。     

Josephson address control unit IC for a 4-bit microcomputerprototype

The authors describe the design and operation of a Josephson address control unit IC (integrated circuit), which will be used for controlling the instruction sequence of an experimental 4-bit Josephson microcomputer prototype system. The IC is composed of three sets of 7- to 10-bit-wide registers and combinational logic circuits driven by a two-phase monopolar power supply. 593 four-function logic gates have been used in the circuit and fabricated using 2.5-μm NbN/oxide/NbN junction technology with Mo resistors and SiO₂ insulation. The operation of the circuit has been successfully tested for all the instructions which control the program sequence of the computer system     

Simple and universal platform for logic gate operations based on molecular beacon probes

A new platform technology is herein described with which to construct molecular logic gates by employing the hairpin-structured molecular beacon probe as a basic work unit. In this logic gate operation system, single-stranded DNA is used as the input to induce a conformational change in a molecular beacon probe through a sequence-specific interaction. The fluorescent signal resulting from the opening of the molecular beacon probe is then used as the output readout. Importantly, because the logic gates are based on DNA, thus permitting input/output homogeneity to be preserved, their wiring into multi-level circuits can be achieved by combining separately operated logic gates or by designing the DNA output of one gate as the input to the other. With this novel strategy, a complete set of two-input logic gates is successfully constructed at the molecular level, including OR, AND, XOR, INHIBIT, NOR, NAND, XNOR, and IMPLICATION. The logic gates developed herein can be reversibly operated to perform the set-reset function by applying an additional input or a removal strand. Together, these results introduce a new platform technology for logic gate operation that enables the higher-order circuits required for complex communication between various computational elements.     

Fundamental building blocks for molecular biowire based forward error-correcting biosensors

This paper describes the fabrication, characterization and modeling of fundamental logic gates that can be used for designing biosensors with embedded forward error-correction (FEC). The proposed logic gates (AND and OR) are constructed by patterning antibodies at different spatial locations along the substrate of a lateral flow immunosensor assay. The logic gates operate by converting binding events between an antigen and an antibody into a measurable electrical signal using polyaniline nanowires as the transducer. In this study, B.?cereus and E.?coli have been chosen as model pathogens. The functionality of the AND and OR logic gates has been validated using conductance measurements with different pathogen concentrations. Experimental results show that the change in conductance across the gates can be modeled as a log-linear response with respect to varying pathogen concentration. Equivalent circuits models for AND and OR logic gates have been derived based on measured results.     

高性能异或门电路的设计

在分析已发表的典型异或门电路的基础上,提出一种新型高性能的异或门电路,其电路核心部分仅3个晶体管,包括一个改进型互补CMOS反相器和一个NMOS传输门.在TSMC0.18μm CMOS工艺下经HSPICE模拟.结果表明,与已有的异或门电路相比,新设计在速度和功耗延迟积上具有较大的优势.     

Reversible-logic design with online testability

Conventional digital circuits dissipate a significant amount of energy because bits of information are erased during the logic operations. Thus, if logic gates are designed such that the information bits are not destroyed, the power consumption can be reduced dramatically. The information bits are not lost in case of a reversible computation. This has led to the development of reversible gates. This paper proposes three new reversible logic gates; two of the proposed gates can be employed to design online testable reversible logic circuits. Furthermore, they can be used to implement any Boolean logic function. The application of the reversible gates in implementing several benchmark functions has been presented.     

Novel single-electron logic circuits using charge-induced signal transmission (CIST) structures

In this paper, on the basis of the Monte Carlo simulation, we demonstrate a method to realize logical operations by the use of the single-electron charge-induced signal transmission (CIST) circuit which we have proposed previously. First, we propose three new-type signal transmission circuits. Then, we demonstrate through construction of a NAND circuit and a full-adder circuit on the basis of the Monte Carlo simulation that we can construct any logic circuit by the use of these circuits. Since the CIST circuit can perform any logical operation and can transmit the state of the presence or absence of an electron and a hole as a binary signal over long distance during one clock cycle bidirectionally, these CIST circuits are expected to be applied to integrated circuit devices as a new circuit construction method.     

Programmable DNA Nanoindicator‐Based Platform for Large‐Scale Square Root Logic Biocomputing

The prospect of programming molecular computing systems to realize complex autonomous tasks has advanced the design of synthetic biochemical logic circuits. One way to implement digital and analog integrated circuits is to use noncovalent hybridization and strand displacement reactions in cell‐free and enzyme‐free nucleic acid systems. To date, DNA‐based circuits involving tens of logic gates capable of implementing basic and complex logic functions have been demonstrated experimentally. However, most of these circuits are still incapable of realizing complex mathematical operations, such as square root logic operations, which can only be carried out with 4 bit binary numbers. A high‐capacity DNA biocomputing system is demonstrated through the development of a 10 bit square root logic circuit. It can calculate the square root of a 10 bit binary number (within the decimal integer 900) by designing DNA sequences and programming DNA strand displacement reactions. The input signals are optimized through the output feedback to improve performance in more complex logical operations. This study provides a more universal approach for applications in biotechnology and bioengineering.     

Single electron encoded latches and flip-flops

Single electron tunneling (SET) technology offers the ability to control the transport of individual electrons. In this paper, we investigate single electron encoded logic (SEEL) memory circuits, in which the Boolean logic values are encoded as zero or one electron charges. More specifically, we focus on the implementation of SEEL latches and flip-flops. All proposed circuits are verified by means of simulation using the SIMulation Of Nanostructures package. We first present a generic SEEL linear threshold gate implementation, from which we derive a family of Boolean logic gates. Second, we propose Boolean gate-based implementations of the RS latch, the D latch, and D flip-flop. Third, we propose threshold gate-based implementations of the same memory elements. Finally, we discuss the estimated area, delay, and power consumption of the Boolean gate-based and threshold gate-based implementations, and compare them with other SET-based memory elements.     

Multi‐threshold and multi‐input DNA logic design style for profiling the microRNA biomarkers of real cancers

Early detection of cancer is very critical because it can reduce the treatment risk and cost. MicroRNAs (miRNAs) have been introduced in recent years as an efficient class of biomarkers for cancer early detection. Now, real‐time polymerase chain reaction has been used to profile the miRNA expression, which is costly, time consuming and low accuracy. Most recently, DNA logic gates are used to detect the miRNA expression level that is more accurate and faster than previous methods. The DNA‐based logic gates face with serious challenges such as the large complexity and low scalability. In this study, the authors proposed a methodology to design multi‐threshold and multi‐input DNA‐based logic gates in response to specific miRNA inputs in live mammalian cells. The proposed design style can simultaneously recognise multiple miRNAs with different rising and falling thresholds. The design style has been evaluated on the lung cancer biomarkers and the experimental results show the efficiency of the proposed method in terms of accuracy, efficiency and speed.Inspec keywords: DNA, logic design, biocomputing, RNA, molecular biophysics, logic gates, lung, genetics, cellular biophysics, cancer, biology computing, enzymes, biosensorsOther keywords: falling thresholds, specific miRNA inputs, multiinput DNA‐based logic gates, low scalability, DNA‐based logic gates face, miRNA expression level, DNA logic gates, low accuracy, time consuming, real‐time polymerase chain reaction, cancer early detection, treatment risk, cancers, microRNA biomarkers, multiinput DNA logic design style, multithreshold, lung cancer biomarkers     

Carbon-nanotube-based voltage-mode multiple-valued logic design

Multivalued logic has always attracted the attention of digital system and logic designers. However, the high-performance and low-power CMOS process, which has been developed over the last two decades, has traditionally assisted successful circuit implementation of binary logic. Consequently, in spite of its large potential multivalued logic design is seldom a circuit designer's choice. This paper presents a novel method of multiple-valued logic design using carbon-nanotube field-effect transistors (CNFETs). The geometry-dependent threshold voltage of CNFETs has been effectively used to design a ternary logic family. We have developed a SPICE-compatible model of ballistic CNFETs that can account for varying geometries and operating conditions. SPICE simulations have been performed on the proposed logic gates, and the transfer characteristics as well as transient behavior have been extensively studied. Finally, a comparison in terms of power and performance of the ternary logic family vis-a/spl grave/-vis traditional complementary field-effect transistor binary logic family has been presented.     

Quantum flux type logic circuits utilizing Josephson junctiontransmission lines

A quantum-flux-type logic circuit is proposed which is composed of Josephson junction transmission lines, along which localized magnetic flux can propagate. By choosing bias current properly, the duplication of magnetic flux and a variety of logical functions can be obtained without changing the circuit topology. Computer simulation results are presented on AND and OR operations with two and three inputs for the same circuit topology, confirming that these circuits can be used as logic circuits. The simulations demonstrate the high-speed operation and low power consumption of this circuit     

通用逻辑门电路的SET实现及应用

通用逻辑门具有更强的逻辑功能,相比传统逻辑门更适合作为阵列逻辑单元。单电子晶体管（SingleElectronTransistor,SET）被认为是众多纳米电子器件中的强有力竞争者。为了拓展SET的应用,减少逻辑综合所用逻辑门的种类,提出了通用逻辑门的SET电路实现方案,设计出基于sET的通用逻辑门树形结构的全比较器等电路,用Hspicer软件对所设计的电路进行仿真,结果表明,该电路具有正确的逻辑功能,为SET通用逻辑门的进一步研究应用奠定了基础。     

An integration of all refractory Josephson logic LSI circuit

An integration process for the fabrication of an all refractory Josephson LSI logic circuit is described. In this process, niobium nitride and niobium double-layered Josephson junctions were integrated using a reactive ion etching with a 2.5 μm minimum feature. A highly selective and anisotropic RIE process and a planarizing technology have been developed for intagrating a circuit with LSI complexity. For evaluating the process capability, test vehicle circuits with MSI/LSI level complexity have been designed and fabricated using this process. An 8 bit ripple carry adder and a 4×4 bit parallel multiplier have been integrated with Josephson four junction logic ( 4JL ) gates, the largest of which contains more than 2800 Josephson junctions. Both functionality and high-speed performance testings have been successfully performed with these test circuits.     

Highly Flexible Hybrid CMOS Inverter Based on Si Nanomembrane and Molybdenum Disulfide

2D semiconductor materials are being considered for next generation electronic device application such as thin‐film transistors and complementary metal–oxide–semiconductor (CMOS) circuit due to their unique structural and superior electronics properties. Various approaches have already been taken to fabricate 2D complementary logics circuits. However, those CMOS devices mostly demonstrated based on exfoliated 2D materials show the performance of a single device. In this work, the design and fabrication of a complementary inverter is experimentally reported, based on a chemical vapor deposition MoS₂ n‐type transistor and a Si nanomembrane p‐type transistor on the same substrate. The advantages offered by such CMOS configuration allow to fabricate large area wafer scale integration of high performance Si technology with transition‐metal dichalcogenide materials. The fabricated hetero‐CMOS inverters which are composed of two isolated transistors exhibit a novel high performance air‐stable voltage transfer characteristic with different supply voltages, with a maximum voltage gain of ≈16, and sub‐nano watt power consumption. Moreover, the logic gates have been integrated on a plastic substrate and displayed reliable electrical properties paving a realistic path for the fabrication of flexible/transparent CMOS circuits in 2D electronics.     

High-performance logic circuits constructed on single CdS nanowires

A high-performance NOT logic gate (inverter) was constructed by combining two identical n-channel metal-semiconductor field-effect transistors (MESFETs) made on a single CdS nanowire (NW). The inverter has a voltage gain as high as 83, which is the highest reported so far for inverters made on one-dimensional nanomaterials. The MESFETs used in the inverter circuit show excellent transistor performance, such as high on/off current ratio ( approximately 10(7)), low threshold voltage ( approximately -0.4 V), and low subthreshold swing ( approximately 60 mV/dec). With the assembly of three identical NW MESFETs, NOR and NAND gates have been constructed.     

Josephson semiconductor interface circuit

This paper describes an output interface circuit which allows Josephson circuits to communicate with semiconductor circuits. The circuit combines Josephson and GaAs drivers to drive a 50 μ load at a signal level of semiconductor circuits. The output voltage of 2.8 mV (usual for Josephson gates using Nb/AlO_x/Nb junctions) was increased to 1.7 V. The interface circuit has been operated up to 800 MHz.