Passivation Effects of Aluminum on Polycrystalline Silicon Thin-Film Transistor With Metal-Replaced Junctions

Aluminum was detected in the channel of a thin-film transistor after its replacement of the polycrystalline silicon source and drain junctions. The resulting transistor exhibits enhanced field-effect mobility, steeper slope of the pseudosubthreshold region, reduced turn-on voltage extrapolated from the linear regime of operation, higher on-state current, and improved immunity against short-channel effects. These improvements are consistent with a measured reduction in the density of trap states. The reduction can be attributed to the presence of aluminum in the channel     

An Analytical Expression for the Transfer Characteristics of a Polycrystalline Silicon Thin-Film Transistor With an Undoped Channel

An analytical model for the transfer characteristics of a polycrystalline silicon thin-film transistor (TFT) with an undoped channel is developed. While the modeling methodology is general, the analytical form is based on the observation that the trap states in a grain boundary are exponentially dispersed over the energy space defined by the energy gap of the adjacent grains. The dispersion relationship is parameterized by an energy EA. The complex mechanisms governing carrier transport in a TFT are modeled in terms of an effective ldquodriftrdquo mobility mu_eff that also accounts for the thermionic emission of charge carriers across the grain boundaries. A gate bias V _pt can be identified that roughly locates the transition from the ldquopseudo-subthresholdrdquo and the ldquoturn-onrdquo regimes of operations. Techniques for the extraction of EA and the transition voltage V _pt are proposed. A particularly simple expression of mu_eff can be obtained in terms of these and other parameters.     

Reliability of Active-Matrix Organic Light-Emitting-Diode Arrays With Amorphous Silicon Thin-Film Transistor Backplanes on Clear Plastic

We have fabricated active-matrix organic light emitting diode (AMOLED) test arrays on an optically clear high-temperature flexible plastic substrate at process temperatures as high as 285 degC using amorphous silicon thin-film transistors (a-Si TFTs). The substrate transparency allows for the operation of AMOLED pixels as bottom-emission devices, and the improved stability of the a-Si TFTs processed at higher temperatures significantly improves the reliability of the light emission over time.     

CMOS Silicon Receiver Integrated With Ge Detector and Reconfigurable Optical Filter

We demonstrate a complmentary metal–oxide–semiconductor (CMOS)-compatible and widely tunable filter with an integrated germanium detector. The filter uses two stages of sixth-order pole-zero filtering cascaded in a vernier fashion to achieve simultaneous tunability and adjustable passband bandwidth from 25 to 50 GHz tuned over a wavelength range $>$12 nm. The out-of-band crosstalk rejection is $sim$30 dB. The monolithically integrated detector has a bandwidth of 6 GHz. We also demonstrate a modified detector design which showed a bandwidth of 11 GHz/s and responsivity of 0.75 A/W.      

Structural Analysis on Organic Thin-Film Transistor With Device Simulation

A 2-D device simulation for organic thin-film transistors (OTFTs) was carried out to reveal the characteristic difference between staggered and planar structures. Assuming the OTFT with Schottky barrier contact, the staggered-structure TFT has more current flow, bigger field-effect mobility, and lower contact resistance than the planar structure. The simulation results indicate that the source electrode of the staggered structure has better ability to supply the current than that of the planar structure.     

A Novel High-Performance Poly-Silicon Thin-Film Transistor With a Double-Channel Structure

In this letter, a novel double-channel polycrystalline-silicon (poly-Si) thin-film transistor (DCTFT) is proposed and demonstrated. The DCTFT, which includes two channels with a thicker source/drain (S/D) region, a field-induced drain, and an offset structure, reveals better device performance and lower S/D resistance. Our experimental results show that the on-current of the DCTFT is higher than that of the conventional structure, and the leakage current is greatly reduced simultaneously. In addition, the device stability such as the threshold-voltage shift under a high gate bias is also improved by this two-channel and thick-S/D-region structure design. The lower drain electric field of the DCTFT is also a benefit to the device scaling down for better performances.      

Inverted Staggered Poly-Si Thin-Film Transistor With Planarized SOG Gate Insulator

In this letter, we have studied the inverted staggered thin-film transistor (TFT) using a spin-on-glass (SOG) gate insulator and a low-temperature polycrystalline silicon (poly-Si) by Ni-mediated crystallization of amorphous silicon. The p-channel poly-Si TFT exhibited a field-effect mobility of 48.2 cm²/V ldr s, a threshold voltage of -4.2 V, a gate-voltage swing of 1.2 V/dec, and a minimum off-current of < 4 times 10^-13A/ mum at V_ds = -0.1 V. Therefore, the gate planarization technology by SOG can be applicable to low-cost large-area poly-Si active-matrix displays.     

An Analytical Model for the Transfer Characteristics of a Polycrystalline Silicon Thin-Film Transistor With a Double Exponential Grain-Boundary Trap-State Energy Dispersion

For a thin-film transistor (TFT) built on excimer-laser crystallized polycrystalline silicon, the dependence of the effective ldquograin-boundary mobilityrdquo on the gate-to-source voltage can be divided into two subregimes exhibiting different power-law characteristics. An expression for the effective mobility is developed using a procedure previously proposed for a TFT built on polycrystalline silicon exhibiting only single power-law dependence. The additional power-law component is reflected in the model by a pair of measurable and physically meaningful parameters. The procedure for determining these parameters is described and demonstrated. Both the measured and calculated transfer characteristics are reported and compared. The double power-law dependence implies a grain-boundary trap-state energy dispersion characterized by two exponential functions. This is presently verified.     

Low-Temperature Polycrystalline Silicon Thin-Film Flash Memory With Hafnium Silicate

In this paper, we have successfully fabricated poly-Si-oxide-nitride-oxide-silicon (SONOS)-type poly-Si-thin-film transistor (TFT) memories employing hafnium silicate as the trapping layer with low-thermal budget processing (les600degC). It was demonstrated that the fabricated memories exhibited good performance in terms of relatively large memory window, high program/erase speed (1 ms/10 ms), long retention time (>10⁶ s for 20% charge loss), and 2-bit operation. Interestingly, we found that these memories depicted very unique disturbance behaviors, which are obviously distinct from those observed in the conventional SONOS-type Flash memories. We thought these specific characteristics are closely related to the presence of the inherent defects along the grain boundaries. Therefore, the elimination of the traps along the grain boundaries in the channel is an important factor for achieving high performance of the SONOS-type poly-Si-TFT Flash memory     

非晶硅薄膜晶体管室温红外探测器的优化设计

介绍了基于非晶硅薄膜晶体管的室温红外探测器的基本特征及性能指标,对晶体管宽长比对探测器性能的影响进行了理论分析,分析表明,提高晶体管的宽长比可以改善探测器的探测率。为了克服传统微桥结构室温红外探测器成品率低的不足,提出了一种新的热绝缘材料,并将该材料应用到了非制冷红外探测器中,实际制备了探测器单元,对该材料的热绝缘能力进行了验证。     

非晶硅薄膜晶体管室温红外探测器的优化设计

介绍了基于非晶硅薄膜晶体管的室温红外探测器的基本特征及性能指标，对晶体管宽长比对探测器性能的影响进行了理论分析，分析表明，提高晶体管的宽长比可以改善探测器的探测率。为了克服传统微桥结构室温红外探测器成品率低的不足，提出了一种新的热绝缘材料，并将该材料应用到了非制冷红外探测器中，实际制备了探测器单元，对该材料的热绝缘能力进行了验证。     

Reorganized Porous Silicon Bragg Reflectors for Thin-Film Silicon Solar Cells

Stacks of porous silicon layers have been successfully applied to maximize internal reflection at the interface between a silicon substrate and an epitaxially grown layer. The stack is consist of alternating porous layers of high and low porosity, defined by the quarter-wavelength rule. During the hydrogen bake prior to epitaxial growth of the epitaxial layer, the porous silicon stack crystallizes in the form of thin quasi-monocrystalline silicon layers incorporating large voids. Experimental data of the measured external reflectance have been linked to the internal reflectance. An optical-path-length enhancement factor of seven was calculated in the wavelength range of 900–1200 nm. Application on thin-film epitaxial solar cells showed a 12% increase in short-circuit current and efficiency.     

High-Performance Double-Channel Poly-Silicon Thin-Film Transistor With Raised Drain and Reduced Drain Electric Field Structures

In this paper, a high-performance single-gate double-channel polycrystalline-silicon thin-film transistor (DCTFT) is proposed and experimentally demonstrated for the first time. Two thin channels, accompanied with a raised source/drain (S/D) area, an offset structure, a drain field plate, and a field-induced drain region, are used in this device, allowing a lower S/D resistance and a better device performance. Our experimental results show that the on-current of the DCTFT is higher than that of the conventional structure, and the leakage current is greatly reduced simultaneously. In addition, the device stability, such as threshold voltage shift and drain on-current degradation under a high gate bias, is also improved by the design of two channels and the reduced drain electric field structures. The lower drain electric field of the DCTFT is also beneficial to scaling down the device for a better performance.      

A Reduced Mask-Count Technology for Complementary Polycrystalline Silicon Thin-Film Transistors With Self-Aligned Metal Electrodes

The inexpensive glass substrate for building conventional low-temperature polycrystalline silicon (poly-Si) thin-film transistors (TFTs) imposes a ceiling on the TFT processing temperature. This results in a reduced efficiency of dopant activation and a high source/drain series resistance. A technique based on aluminum-induced crystallization of amorphous silicon has been applied to fabricate TFTs with low-resistance self-aligned metal electrodes (SAMEs). While at least two masked implantation steps are typically used for constructing the doped source and drain regions of conventional n- and p-channel TFTs in a complementary metal–oxide–semiconductor circuit technology, it is currently demonstrated that complementary SAME poly-Si TFTs can be constructed using a combination of a masked and a blanket source and drain implantation steps. The decrease in mask count reduces process complexity and cost. Control of ion channeling is the enabling factor behind the successful demonstration of the technology.      

X波段硅微波振荡晶体管

本文报导的X波段硅微波振荡晶体管WZ321型器件,采用了亚微米全干法刻蚀技术、离子注入基区掺杂技术、砷发射区、多层金属化电极、小寄生参量的全密封封装,使器件具有良好的微波性能和可靠性。器件典型的微波参数是在7.5GHz下,振荡输出20mW。     

Silicon-on-Insulator CWDM Power Monitor/Receiver With Integrated Thin-Film InGaAs Photodetectors

In this letter, we demonstrate a compact and cost-effective four-channel demultiplexer with integrated photodetectors for application in coarse wavelength-division-multiplexing systems. The device consists of a silicon-on-insulator planar concave grating (PCG) demultiplexer and heterogeneously integrated InAlAs-InGaAs metal-semiconductor-metal photodetectors, and has a footprint of only 0.1 mm² . The PCG and integrated photodetectors have a responsivity of 0.6 A/W for TE-polarized light. The integrated device has an optical crosstalk of -25 dB.     

Innovative Voltage Driving Pixel Circuit Using Organic Thin-Film Transistor for AMOLEDs

In this work, we propose a novel active-matrix organic light-emitting diode displays (AMOLED) pixel circuit based on organic thin-film transistor (OTFT) architecture, which consisted of four switches, one driving transistor, and a capacitor. The pentacene-based OTFT device possesses a field-effect mobility of 0.1 ${hbox{cm}}^{2} /{hbox{V}}cdot{hbox{s}}$, a threshold voltage of $-{hbox{1.5}}~{hbox{V}}$ , subthreshold slope of 1.8 V/decade and an on/off current ratio ${hbox{10}} ^{6}$. The resultant voltage-driving pixel circuit, named “Complementary Voltage-Induced Coupling Driving” (CVICD), is different from the current-driving scheme and can appropriately operate at low gray level for the low-mobility OTFT circuitry. The current non-uniformity less than 2.9% is achieved for data voltage ranging from 1 to 17 V by SPICE simulation work. In addition, the new external driving method can effectively reduce the complexity of OLED pixel circuitry.      

A Large Bandgap Organic Salt Dopant for Sn-Based Perovskite Thin-Film Transistor

Metal halide perovskite optoelectronic devices have made significant progress over the past few years, but precise control of charge carrier density through doping is essential for optimizing these devices. In this study, the potential of using an organic salt, N,N-dimethylanilinium tetrakis(pentafluorophenyl)borate, as a dopant for Sn-based perovskite devices, is explored. Under optimized conditions, the thin film transistors based on the doped 2D/3D perovskite PEAFASnI₃ demonstrate remarkable improvement in hole mobility, reaching 7.45 cm²V⁻¹s⁻¹ with a low subthreshold swing and the smallest sweep hysteresis (ΔV_hysteresis = 2.27 V) and exceptional bias stability with the lowest contact resistance (2.2 kΩ cm). The bulky chemical structure of the dopant prevents it from penetrating the perovskite lattice and also surface passivation against Sn oxidation due to its hydrophobic nature surface. This improvement is attributed to the bifunctional effect of the dopant, which simultaneously passivates defects and improves crystal orientation. These findings provide new insights into potential molecular dopants that can be used in metal halide perovskite devices.     

A Novel Four-Mask-Step Low-Temperature Polysilicon Thin-Film Transistor With Self-Aligned Raised Source/Drain (SARSD)

In this letter, a novel structure of polycrystalline-silicon thin-film transistors (TFTs) with self-aligned raised source/drain (SARSD) and a thin channel has been developed and investigated. In the proposed structure, a thick SD and a thin active region could be achieved with only four mask steps, which are less than that in conventional raised SD TFTs. The proposed SARSD TFT has a higher on-state current and a lower off-state leakage current. Moreover, the on/off current ratio of the proposed SARSD TFT is also higher than that of a conventional coplanar TFT     

Amorphous Silicon Thin-Film Transistor Backplanes Deposited at 200 °C on Clear Plastic for Lamination to Electrophoretic Displays

The transition of thin-film transistor (TFT) backplanes from rigid plate glass to flexible substrates requires the development of a generic TFT backplane technology on a clear plastic substrate. To be sufficiently stable under bias stress, amorphous-silicon (a-Si:H) TFTs must be deposited at elevated temperatures, therefore the substrate must withstand high temperatures. We fabricated a-Si:H TFT backplanes on a clear plastic substrate at 200degC. The measured stability of the TFTs under gate bias stress was superior to TFTs fabricated at 150degC. The substrate was dimensionally stable within the measurement resolution of 1, allowing for well-aligned 8 times 8 and 32 times 32 arrays of pixels. The operation of the backplane is demonstrated with an electrophoretic display. This result is a step toward the drop-in replacement of glass substrates by plastic foil.