A comparison of MOS inversion layer charge and capacitance formulas

A test is made of a recent proposal by Lewyn and Meindl for approximation of MOS inversion layer charge and substrate capacitance. Included in the test are the charge sheet formula and a new formula derived here which includes the pinning of the depletion layer width in strong inversion. Comparison with numerical calculation shows the Lewyn-Meindl result for charge density is less accurate than the charge sheet result over the entire subthreshold region. Similar inaccuracy is expected in MOS current-voltage curves in the subthreshold region and near pinch-off. The new formula is better than the other two over the entire bias range. A comparison of dc and ac substrate capacitances shows the new result to be better than both of the other formulas. In inversion, however, the percent error in dc capacitance is large. This large percent error corresponds to a small absolute error because the dc capacitance goes to zero in strong inversion. The ac capacitance error in strong inversion is ∼5 percent because of neglect of the ac inversion layer redistribution. Percent error curves for all three formulas are presented as a function of band bending and reverse bias.     

Electron ground state in the semiconductor inversion layer and low frequency MIS capacitance

By varying the total energy and electrostatic energy functionals which represent an approximate self-consistent solution of Schrödinger's and Poisson's equation, the ground state of electrons is determined in a semiconductor inversion layer. It was assumed that all the electrons in the semiconductor inversion layer are in the ground state.The low frequency capacitance metal-insulator-semiconductor (MIS) capacitors is calculated by the proposed theory and the results are compared with classically calculated capacitance. Numerical results are given for a silicon (111) p-type bulk at 77°K.     

Characterization and modelling of carrier distribution and gate capacitance in MOS structure inversion layer

Based on the carrier distribution in three-dimensional semi-classical and twodimensional quantum mechanical cases, the concept of surface layer effective density-of-states (SLEDOS) is proposed. Then a simplified method of calculating the band bending and subband energies is employed to investigate quantum mechanical effects (QMEs) in MOS structure inversion layer. The method is unique compared with published methods in its reversed nature of the iteration procedure. It has high efficiency and good convergence characteristics and gives satisfactorily coincident results with rigorous but more complicated selfconsistent calculations. The method is applicable in both quantum mechanical and semi-classical cases. The subband occupation of inversion layer carrier and the two-dimensional density-of-states in semi-classical and quantum mechanical cases are then calculated. QMEs on inversion layer carrier density and surface potential are analysed on the basis of the method. Gate capacitance in the MOS structure inversion region is formulated for both quantum mechanical and semiclassical cases, and QMEs on gate capacitance are analysed.     

Analysis and characterization of the depletion-mode IGFET

Using simple charge-voltage relationships, a four-terminal model is developed for the depletion-mode IGFET. Various conditions which can coexist at the surface, such as accumulation, depletion, and inversion, are taken into account. The implanted channel is approximated by a box profile. The basic model elements, namely, the source-drain transport current and the various charging currents, are explicitly given in terms of known processing data and implanted channel parameters. Device threshold voltage, drain saturation voltage, and conditions for surface inversion are explicitly given as a function of these parameters.     

Influence of high channel doping on the inversion layer electron mobility in strained silicon n-MOSFETs

In this letter, we investigate the dependence of electron inversion layer mobility on high-channel doping required for sub-50-nm MOSFETs in strained silicon (Si), and we compare it to co-processed unstrained Si. For high vertical effective electric field E/sub eff/, the electron mobility in strained Si displays universal behavior and shows enhancement of 1.5-1.7/spl times/ compared to unstrained Si. For low E/sub eff/, the mobility for strained Si devices decreases toward the unstrained Si data due to Coulomb scattering by channel dopants.     

Analysis and design of the dual-gate inversion layer emitter transistor

The dual-gate inversion layer emitter transistor (DGILET) is a device in which the injection of minority carriers takes place from an inversion layer formed under a MOS gate. Therefore, the device can be switched between MOS and bipolar modes using the gate giving the means to achieve a superior combination of low conduction losses and low switching losses. The structure of the device and operation in both the unipolar and bipolar modes are described in detail. Devices have been fabricated on bulk silicon wafers using junction isolation and experimental results confirm the expected superior performance. In particular, the results confirm predictions that if the inversion layer injector is properly designed, the voltage snapback that occurs during the transition between unipolar and bipolar modes can be completely suppressed. This can be achieved with a compact structure in contrast to the extended structures required in anode-shorted lateral insulated gate bipolar transistor (LIGBTs). An equivalent circuit for the DGILET is presented and the control of the minority carrier injection is also analyzed. Experimental results show that the DGILET can switch at speeds approaching those characteristic of MOSFETs with operating current densities comparable to LIGBTs. The results show that the DGILET offers lower overall losses than an LIGBT at switching frequencies above about 10 kHz.     

Modeling the inversion layer at equilibrium

Recent developments in the modeling of a step junction or a semiconductor surface at equilibrium have yielded a set of approximate-analytic expressions that relate normalized potential to normalized position outside the inversion regime. Here we offer analogous approximate-analytic expressions for the relations between normalized potential, normalized position and normalized electric field within the inversion regime, for a range of variables of practical interest. A real charge density in the inversion layer obtained analytically using these expressions is compared with the value obtained from the charge-sheet model of Brews, and is shown to be appreciably more accurate.     

Modeling the impurity profile in an ion-implanted layer of an IGFET for the calculation of threshold voltages

An extremely simple model for the impurity profile in an ion-implanted channel layer of an IGFET is applied to simulating the substrate bias dependence of its threshold voltage. Excellent agreement is obtained between theory and experiment on n-channel silicon devices.     

M.I.S. capacitance in heavy inversion

The letter deals with a theoretical analysis of the different currents originating in an m.i.s. structure for a heavy inversion region of operation, when a transient low-level electrical perturbation is applied. The expression for the generation-recombination current in the space-charge region is fairly different from that generally used; it is emphasised that the recombination rate is not constant and not equal to ni/2?n in the whole thickness of the transition zone.     

Ultralow-threshold-current lasing in inversion channel lasers

A new regime of semiconductor laser operation was observed in quantum-well inversion channels of double heterostructure optoelectronic switches. The quantum-well active region operated with substantial excess negative charge imbalance due to the proximity of a high-density depleted donor charge sheet. Threshold current densities as low as 15 A/cm² in as-cleaved 400-μm-long devices were measured, and unusual high-frequency operation under low power operation was observed. These qualities may be of great significance for optical interconnections and optoelectronic integrated circuits     

A study of x-ray damage effects on the short channel behavior of IGFET’s

Ionizing particles and radiation may play an important, albeit undesirable role in the processing of VLSI and ULSI circuits in that they can generate bulk charge in the gate insulator of IGFETs. In this regard, there is conflicting information in the literature on the effects of ionizing radiation on short channel phenomena in IGFETs. For example, Peckeraret al. in 1983 claimed that the effective channel length increases when positive coulombic charge is introduced during irradiation, resulting in a decrease in the short channel effect. Schrankleret al. in 1985 claimed in an experimental study, on the other hand, using 28.0 nm thick gate oxides and 0.9–10 μm channel lengths, that the effect is increased,i.e., the short channel effect begins at longer channel lengths. Wilson and Blue in 1982, in a theoretical study concluded that other than a uniform downward shift in theV _T -channel length curve due to the presence of insulator net fixed positive charge, no effect should be observed. Because of these conflicting reports, it was decided to evaluate this behavior using two different background doping levels inn-channel structures, with physical channel lengths ranging between 1.5 and 10 μm, in 0.1 and 0.5 gWcm (100) Si. To further explore the situation, gate oxide (grown at 1000° C in O₂ containing 4.5% HC1) thicknesses were varied from 17.0–35.0 nm, and the absorbed radiation dose using Al-K_α (1.5 keV) x-rays was varied between 2.4 × 10⁶ rad (SiO₂) and 2.4 × 10⁷ rad (SiO₂). For all conditions studied above, a uniform downward shift in the V_T-Channel length curve was observed, essentially corroborating the theoretical conclusions of Wilson and Blue. In addition to the above, the effects of intentionally doping the gate insulator with boron (1.2 × 10¹² B⁺ cm⁻²) implanted at 8 and 10 keV into 25.0 nm and 31.4 nm oxides, respectively, on short channel effects were evaluated for devices grown onp-type 0.5 Ω.cm substrates. Unlike the devices which did not have excess boron intentionally implanted into the gate insulator, it was found that higher concentrations of boron (2.0 × 10¹⁷ cm⁻³ in the insulator via implantation as compared to 4.2 × 10¹⁶ cm⁻³ incorporated in oxides during the oxide growth on 0.5 Ω.cm type (100) Silicon) leads to smaller short channel effects in unirradiated devices. On the other hand, these heavily doped oxides show a distinct worsening of the short channel effect after exposure to 2.4 × 10⁷ rad (SiO₂) using Al-K_α radiation. Thus, while normal devices exhibit little if any short channel improvement, or degradation following irradiation, intentionally doped insulators show an improvement in short channel characteristics prior to irradiation, and a worsening of the short channel effect following irradiation.     

IGFET Analysis through numerical solution of Poisson's equation

Numerical techniques have been used to obtain the field distribution in IGFETs under saturated bias conditions. The numerical solution of Poisson's equation is obtained with fewer simplifying assumptions than are necessary to obtain an analytic solution. The numerical solution is used to calculate the change in channel length as bias values are varied. These changes are used to predict the voltage dependences of drain current, drain conductance and transconductance in saturation. The potential solutions also permit a rough calculation of breakdown voltages. A comparison is made between the theoretical results and measurements on IGFETs of varying dimensions and doping concentrations.     

Inversion-layer capacitance and mobility of very thin gate-Oxide MOSFET's

Inversion-layer capacitance has been experimentally characterized and identified to be the main cause of the second-order thickness-dependence of MOSFET characteristics. Field-dependent channel mobilities of both electrons and holes were independent of gate-oxide thicknesses from 50 to 450 Å, e.g., there is no evidence of the alleged mobility degradation in very thin gate-oxide MOSFET's. Subthreshold slope, insignificantly affected by the inversion-layer capacitance, follows the simple theory down to ∼ 35 Å of oxide thickness. The empirical equations for inversion-layer Capacitance and mobilities versus electric field are proposed.     

Novel hot-electron effects in the channel of MOSFET's observed by capacitance measurements

Capacitance-voltage measurements were performed on small-size MOSFET's with applied drain voltage to obtain information about hot-electron effects. The theoretical analysis shows that hot carriers cause remarkable changes 1) in the vertical and horizontal distribution of the electrons in the inversion layer, 2) in the surface potential drop, 3) in the depletion charge, and 4) in the effective threshold voltage. The influence of these hot-electron effects on the channel current is discussed.     

Different mechanisms affecting the inversion layer transient response

The transient response of the MOS capacitance after the application of a large depleting voltage can be caused by three different mechanisms depending on the distribution of the electric field between the silicon and the oxide. The three different cases were distinguished by measurements of the temperature dependence and the voltage dependence of the relaxation behavior. Relaxation due to thermal generation of carriers prevails at low electric fields, relaxation via oxide states occurs at medium fields, and relaxation by avalanche effects predominates at high fields. From the case where thermal relaxation is predominant the effective lifetime of minority carriers in the depletion region and the surface recombination velocity could be determined. At low temperatures (&sim100°K) where most frequently no relaxation occurs in the dark, light-induced relaxation phenomena were studied. Only light with energies larger than the Si band gap causes relaxation.     

Effects of radiative processing steps on inversion layer mobility and channel hot carrier damage in reoxidized nitrided oxide mosfets

The effects of x-ray irradiation and a subsequent low temperature anneal on the properties of reoxidized nitrided oxide (RNO) MOSFET's were examined. Irradiation was found to degrade conventional SiO₂ MOSFET lifetime under channel hot carrier stress far more strongly than RNO lifetime, particularly for p-channel devices. This is attributed to reduced bulk neutral electron trap generation in RNO. The inversion layer mobility of RNOn-MOSFET's (and, to a lesser degree,p-MOSFET's) was found toincrease after irradiation and anneal. 1/f noise measurements indicate that this change in mobility is due to a reduction in the density of near-interface electron traps.     

Effects of the inversion layer centroid on MOSFET behavior

The effects of the average inversion-layer penetration, the inversion-layer centroid, on the inversion-charge density and the gate-to-channel capacitance have been analyzed. The quantum model has been used, and a variety of data have been obtained by self-consistently solving the Poisson and Schrodinger equations. An empirical expression for the centroid position that is valid for a wide range of electrical and technological variables has been obtained and has been applied to accurately model the inversion-layer density and capacitance     

A mobility model for carriers in the MOS inversion layer

A mobility model for carriers in the MOS inversion layer is proposed. The model assumes that mobility is a function of the gate and drain fields, and the doping density, which conforms to Thornber's scaling law. Two-dimensional computer simulation combined with the present mobility model can predict experimental drain current within an error of ± 5 percent. The present model is applicable and suitable for designing short-channel MOSFET's, especially in the submicrometer range. The "saturation velocity" in the MOS inversion layer is also discussed, based on Thornber's scaling law. The saturation velocity, as determined from the calculated drain current in the same way as experimentalists have done, is 6.6 × 10⁶cm/s. This is close to what has been claimed to be "saturation velocity in the inversion layer," and is about two-thirds of microscopic saturation velocity. This lower saturation velocity originates from the nonuniform field distribution in the test device, and, therefore, the experimentally reported saturation velocity in the MOS inversion layer is inferred to be a macroscopic average, rather than the microscopic drift velocity.