Modeling the equivalent oxide thickness of Surrounding Gate SOI devices with high-κ insulators

In this work, the behavior of the gate insulator capacitance of different Surrounding Gate SOI devices with square and circular cross-sections has been studied. It is shown that the equivalent oxide thickness used for planar devices is not valid for devices with bidimensional confinement. For this kind of devices, new expressions for the gate insulator capacitance and equivalent oxide thickness are obtained using an approximate model of metal–insulator–metal capacitors. These expressions depend not only on the dielectric constant but also on the geometry of the device under consideration since for non-planar devices geometry plays an important role in the behavior of the C–V characteristics. The new expressions are validated by numerical simulations of these Multiple-Gate (MuG) devices that take into account quantum effects.     

RF performance of diamond MISFETs

A cutoff frequency (f_T) of 11 GHz is realized in the hydrogen-terminated surface channel diamond metal-insulator-semiconductor field-effect transistor (MISFET) with 0.7 μm gate length. This value is five times higher than that of 2 μm gate metal-semiconductor (MES) FETs and the maximum value in diamond FETs at present. Utilizing CaF₂ as an insulator in the MIS structure, the gate-source capacitance is reduced to half that of the diamond MESFET because of the gate insulator capacitance being in series to the surface-channel capacitance. This FET also exhibits the highest f _max of 18 GHz and 15 dB of power gain at 2 GHz. The high-frequency equivalent circuits of diamond MISFET are deduced from the S-parameters obtained from RF measurement     

Inversion MOS capacitance extraction for high-leakage dielectricsusing a transmission line equivalent circuit

Accurate measurement of MOS transistor inversion capacitance with a physical silicon dioxide thickness less than 20 Å requires correction for the direct tunneling leakage. This work presents a capacitance model and extraction based on the application of a lossy transmission line model to the MOS transistor. This approach properly accounts for the leakage current distribution along the channel and produces a gate length dependent correction factor for the measured capacitance that overcomes discrepancies produced through use of previously reported discrete element based models. An extraction technique is presented to determine the oxide's tunneling and channel resistance of the transmission line equivalent circuit. This model is confirmed by producing consistent C_0x measurements for several different gate lengths with physical silicon dioxide thickness of 9, 12, and 18 Å     

A comprehensive analytical model for III-V compound MISFET's

A one-dimensional analytical model for III-V compound deep-depletion-mode MISFET's is developed. The model calculates transconductance, drain resistance, and gate capacitance beyond current saturation where these devices are normally operated-a regime not treated by other MISFET models. It is shown that insulator thicknesses less than 50 nm and surface state densities less than 1 × 10¹²eV^-1. cm^-2will be required for optimum MISFET devices. In a comparison of the expected performance differences between GaAs, InP, and InGaAs FET devices with similar geometries, it is shown that InP and InGaAs MISFET's will have lower gate capacitance, a greater cut-off frequency, and up to 2-dB improvement in minimum noise figure compared with a GaAs MESFET. Device characteristics predicted by this model agree with measured values to an accuracy of ±20 percent, which is well within the accuracy with which the modeled input parameters can be measured. This represents a factor of two improvement in accuracy when compared to other MISFET models. The model predicts the characteristics expected for a MESFET device in the limit of zero insulator thickness.     

A 2-D analytical threshold-voltage model for GeOI/GeON MOSFET with high-k gate dielectric

A 2-D analytical threshold-voltage model for ultra-thin-body MOSFET with buried insulator and high-k gate dielectric is established by solving the 2-D Poisson's equation for the gate-dielectric, channel and buried-insulator regions. The validity of the model is confirmed by comparing with experimental data and other models. Using the model, the influences of gate-dielectric permittivity, buried-insulator permittivity, channel thickness, buried-insulator thickness and channel doping concentration on threshold behaviors are investigated. It is found that the threshold behaviors can be improved by using buried insulator with low permittivity, thin channel and high channel doping concentration. However, the threshold performance would be degraded when high-k gate dielectric is used due to enhanced fringing-field effect.     

Partially Depleted Silicon-on-Ferroelectric Insulator Field Effect Transistor- Parametrization & Design Optimization for Minimum Subthreshold Swing

This paper presents the concept of a new field effect transistor based on ferroelectric insulator. The proposed design is named Partially Depleted Silicon-on-Ferroelectric Insulator Field Effect Transistor (PD-SOFFET). The design combines the concepts of negative capacitance in ferroelectric material and silicon-on-insulator (SOI) device. The structure varies from the conventional SOI technology by substituting the buried SiO₂ with a layer of ferroelectric insulator. This new material stack can extract an effective negative capacitance (NC) in the body of the device. The NC effect can provide internal signal boosting. It is demonstrated that the subthreshold swing and the threshold voltage of the proposed device can be lowered by carefully selecting the doping density, the types of the gate oxide and the thicknesses of the ferroelectric film, the silicon layer above the buried insulator and the gate oxide. Lower subthreshold swing is a prime requirement for ultra-low-power design. This paper focuses on studying several parameters to tune the subthreshold swing of the SOFFET device. We have recently introduced the concept of the new transistor, SOFFET, with ferroelectric insulator embedded inside the silicon substrate to lower the subthreshold swing. This paper investigates the impacts of different oxide materials, ferroelectric thicknesses and doping profiles on the negative capacitance inside the body of the proposed PD-SOFFET. It is observed that some emerging gate oxide materials can improve subthreshold flexibility, lower leakage and provide better control over the channel in the proposed device.     

Gate Capacitance‐Dependent Field‐Effect Mobility in Solution‐Processed Oxide Semiconductor Thin‐Film Transistors

Solution‐processed oxide semiconductors (OSs) used as channel layer have been presented as a solution to the demand for flexible, cheap, and transparent thin‐film transistors (TFTs). In order to produce high‐performance and long‐sustainable portable devices with the solution‐processed OS TFTs, the low‐operational voltage driving current is a key issue. Experimentally, increasing the gate‐insulator capacitances by high‐k dielectrics in the OS TFTs has significantly improved the field‐effect mobility of the OS TFTs. But, methodical examinations of how the field‐effect mobility depends on gate capacitance have not been presented yet. Here, a systematic analysis of the field‐effect mobility on the gate capacitances in the solution‐processed OS TFTs is presented, where the multiple‐trapping‐and‐release and hopping percolation mechanism are used to describe the electrical conductivity of the nanocrystalline and amorphous OSs, respectively. An intuitive single‐piece expression showing how the field‐effect mobility depends on gate capacitance is developed based on the aforementioned mechanisms. The field‐effect mobility, depending on the gate capacitances, of the fabricated ZnO and ZnSnO TFTs clearly follows the theoretical prediction. In addition, the way in which the gate insulator properties (e.g., gate capacitance or dielectric constant) affect the field‐effect mobility maximum in the nanocrystalline ZnO and amorphous ZnSnO TFTs are investigated.     

基于等效电容法对SOI器件自加热效应研究

针对目前常规SOI器件高温特性存在的问题,提出了采用等效电容法分析器件自加热效应的新观点,对抑制自加热效应原理进行了新的解析,根据埋层材料的介电常数不同,按等效电容法进行埋层厚度折算。在此基础上,提出了SOI器件的埋层新结构,并从介电常数的角度较好地验证了提出观点的正确性。最后得到,高介电常数等效埋层厚度的减小利于热泄散,高热导率的埋层材料提高了导热能力,在双重因素作用下有效抑制了自加热效应。     

绝缘体上硅FinFET亚阈值摆幅研究

在新型多栅器件栅电容模型的研究中,量子电容随着沟道长度及栅氧化层厚度的不断减小而变得越发不可忽略。推导了基于绝缘体上硅(SOI)工艺技术的鳍式场效应晶体管(FinFET)的量子电容,并通过构建囊括量子电容的内部电容网络模型推导了亚阈值摆幅。采用Matlab软件,仿真验证了量子电容对亚阈值摆幅的影响。提出了亚阈值摆幅的优化方法,为如何选取合适的器件尺寸来优化某个特定设计目标的性能提供了指导。     

Current drive enhancement by using high-permittivity gate insulatorin SOI MOSFET's and its limitation

Speed enhancement effects by using a high-permittivity gate insulator in SOI MOSFETs and its limitation were investigated by a two-dimensional device simulator and circuit simulator. The SOI structure is suitable to have excellent current drive by using a high-permittivity gate insulator. Although the gate capacitance increases as a function of its dielectric constant, the current drive does not increase proportionally due to the inversion capacitance. According to the simulation results of the delay time, when the pulse waveforms driven by a CMOS inverter are propagated through 1 mm-long interconnects, the delay time significantly reduces at a dielectric constant value of around 25 (Ta₂O₅). Thus, it is worthwhile using Ta₂O₅ for gate insulator to achieve high-speed operation. Furthermore, the reduction of source parasitic series resistance is a key issue to realize the highest current drive by using a high-permittivity gate insulator in SOI MOSFET     

A new technique to extract channel mobility in submicron MOSFETsusing inversion charge slope obtained from measured S-parameters

We present a novel method to extract the effective channel mobility directly from measured S-parameters in submicron MOSFETs. This method is based on the slope extraction of the total gate charge versus mask gate length from measured S-parameters. Unlike conventional approaches, the use of a very long channel test device or the extraction of the parasitic capacitance and effective channel length are not required to extract the mobility in short-channel LDD devices, thus making the new method more accurate and simpler. The validity of the method is demonstrated by comparing the result with those using a previously reported method     

Hydrogenated amorphous silicon thin-film transistor with a thingate insulator

Thinning the gate insulator in an hydrogenated amorphous silicon thin-film transistor (a-Si:H TFT) has been studied in a coplanar structure. The threshold voltage decreases with decreasing gate insulator thickness without changing the field effect mobility significantly. The reduction in the threshold voltage is due to the decrease in the charge traps in the SiN_x and in its film thickness. The coplanar a-Si:H TFT with a gate insulator thickness of 35 nm exhibited a field effect mobility of 0.45 cm²/Vs and a threshold voltage of 1.5 V. The thickness of the gate insulator can be decreased in the coplanar a-Si:H TFTs because of the planarized gate insulator     

A capacitance method to determine channel lengths for conventional and LDD MOSFET's

A simple method for determining the channel length and in situ gate-oxide thickness of MOSFETs is described. The method is based on the linear relationship between the intrinsic gate capacitance and effective channel length. Measurements from two gate biases on devices of different channel lengths are sufficient to obtain a full characterization. In contrast to the channel-resistance method, the accuracy of the capacitance method is independent of the source-drain and contact series resistance. It can, therefore, be used for conventional as well as lightly-doped drain (LDD) devices. Channel length and gate-oxide thickness determined by this method are given for conventional and LDD MOSFET's. For conventional MOSFET's, the new method agrees with the traditional effective length measurements to better than 0.1 µm.     

Microwave performance of ion-implanted InP JFETs

These devices have a planar structure with the channel and gate regions formed by the selective implantation of silicon and beryllium into an Fe-doped semi-insulating InP substrate. The nominal gate length is 2 μm with a channel doping of 10¹⁷ cm^-3 and thickness of 0.2 μm. The measured values of f_T and f_max are 10 and 23 GHz, respectively. Examination of the equivalent circuit parameters and their variation with bias led to the following conclusions: (a) a relatively gradual channel profile results in lower than desired transconductance, but also lower gate-to-channel capacitance; (b) although for the present devices, the gate length and transconductance are the primary performance-limiting parameters, the gate contact resistance also reduces the power gain significantly; (c) the output resistance appears lower than that of an equivalent GaAs MESFET, and requires a larger V_DS to reach its maximum value; and (d) a dipole layer forms and decouples the gate from the drain with a strength that falls between that of previously reported GaAs MESFETs and InP MESFETs     

Physical Understanding of Gate-Depletion Phenomena in Poly-Si/HfSiON Stacks Based on C–V Differentiation Analysis

We propose sub-1-A-resolution analysis of gate surface layer In scaled-T_inv (capacitance equivalent thickness at substrate inversion) gate stacks by differentiating their C-V curves. By introducing the universal derivative-of-capacitance curve, gate stacks with different equivalent oxide thickness of gate insulator and substrate-impurity concentration JVSub can be analyzed in one and the same plot. By applying this analysis technique to p+ poly-Si/HfSiON stack, it is found that gate depletion increases due to both lower poly impurity concentration N_poly and high pinning charge density N_ox inside the dielectric. Ultrathin SiN cap insertion onto HfSiON recovers the degradation in N_poly and N_ox leading to suppression of gate depletion and flatband voltage shift.     

Modeling of parasitic capacitances in deep submicrometer conventional and high-K dielectric MOS transistors

In deep submicrometer MOSFETs the device performance is limited by the parasitic capacitance and resistance. Hence a circuit model is needed to treat these effects correctly. In this work, we have developed circuit models for the parasitic capacitances in conventional and high-K gate dielectric MOS transistors by taking into account the presence of source/drain contact plugs. The accuracy of the model is tested by comparing the modeled results with the results obtained from three-dimensional (3-D) Monte-Carlo simulations and two-dimensional (2-D) device simulations over a wide range of channel length and oxide thickness. The model is also used to study the dependence of parasitic capacitance on gate length, gate electrode thickness, gate oxide thickness, gate dielectric constant, and spacer width.     

Dual material gate silicon on insulator junctionless MOSFET for low power mixed signal circuits

In this research paper, demonstrates, the logic performance of n and p channel complementary metal oxide semiconductor (CMOS) circuits implemented with dual material gate silicon on insulator junctionless transistor (DMG SOI JLT). The logic performance of a CMOS circuit is evaluated in terms of static power dissipation, voltage transfer characteristic, propagation delay and noise margin. The gate capacitance is less as compared to gate capacitance of DMG SOI transistor in saturation. The power dissipation for CMOS inverter of DMG SOI JLT is improved by 25% as compared to DMG SOI transistor. The DMG SOI JLT common source amplifier has 1.25 times amplification as that of DMG SOI transistor. The noise margin of DMG SOI JLT CMOS inverter is improved by 23% as compared to the DMG SOI transistor CMOS inverter. The NAND gate static power dissipation of DMG SOI JLT is found improved imperically as compared to DMG SOI transistor for various channel length. The improvement obtained is 53% for 20nm, 46% for 30nm and 34% for 40nm respectively. Static power dissipation of DMG SOI JLT inverter is reduced by 3% as compared to junction transistor inverter at channel length of 30nm.     

Self-aligned p-channel MISFET with a low-temperature-grown GaAsgate insulator

A new p-channel GaAs metal-insulator-semiconductor field-effect transistor (MISFET) using low-temperature-grown (LTG) GaAs as the gate insulator is demonstrated. Neither the GaAs conducting channel nor the gate insulator was doped, and a Be self-aligned implant was used to lower the source and drain series resistance. For a MISFET with a 1.5-μm gate length, the transconductance is 22 mS/mm and the maximum drain current is 120 mA/mm obtained at -8 V of gate bias. The measured unity-current-gain cut-off frequency f_T is 2.0 GHz     

High-speed and low-power interconnect technology forsub-quarter-micron ASIC's

The optimum interconnect structure for high-speed and low-power sub-quarter-micron Application Specified Integrated Circuits (ASIC's) is investigated. High-speed and low-power scaling rules for the interconnect structures are extracted statistically from the wiring data in actual ASIC's. Adopting the scaling rule for a 0.25-μm ASIC enables us to reduce the gate delay by 23% and the gate power by 31% compared to conventional (horizontal only) scaling rule. A low-dielectric-constant interlayer insulator further reduces both the gate delay and power by reducing wiring capacitance. A 0.25-μm interconnect structure was fabricated by adopting the “high-speed and low-power interconnect scaling rule” and using organic spin-on-glass (SOG) as a low-dielectric-constant interlayer insulator. According to equivalent-circuit calculation using the measured interconnect parameters, the gate delay was reduced by 39% and the gate power was reduced by 47% compared to a conventional interconnect structure     

Effect of electron trapping on IGFET characteristics

At large applied voltages, electrons flowing from the source to the drain of a n-channel insulated-gate field-effect transistor (IGFET) may gain sufficient energy from the high-field region near the drain to be emitted into the gate insulator layer near the drain junction. The trapping of these hot electrons in the gate insulator results in transconductance degradation and/or threshold voltage shift. There is also evidence of surface-state generation resulting from hot-electron emission into the SiO₂ layer. The extent of the resultant transconductance degradation and/or threshold shift depends strongly on the electron trapping characteristics of the gate insulator. For devices having SiO₂/Si₃N₄ as gate insulator, electron trapping is completely dominated by the Si₃N₄ layer. In this case, channel hot-electron effect results in threshold shift alone. For devices having SiO₂ as gate insulator, the trapping characteristics depend on its positive oxide-charge concentration. In this case, channel hot-electron effect results in a combination of transconductance degradation and threshold shift.