Design and Analysis of an Ultrahigh-Speed Glitch-Free Fully Differential Charge Pump With Minimum Output Current Variation and Accurate Matching

An ultrahigh-speed fully differential charge pump with minimum current mismatch and variation is proposed in this brief. A mismatch suppression circuit is employed to minimize the mismatch between the charging and discharging currents, which minimizes the steady-state phase error in a phase-locked loop (PLL). A variation suppression circuit is proposed to minimize output current variation with the change of output voltage, which reduces the variation of the bandwidth in a PLL. Techniques are proposed to suppress both low-speed glitches and high-speed glitches in the output current to allow glitch-free operation of the charge pump with ultrafast input pulses. The differential charge pump is designed and simulated under the power supply of 3.3 V in TSMC 0.35-$mu$m CMOS technology to verify the effectiveness of the proposed techniques.     

Efficient algorithm for glitch power reduction [CMOS logiccircuits]

An efficient algorithm is proposed for reducing glitch power dissipation in CMOS logic circuits. The proposed algorithm takes a path balancing approach that is achieved using gate sizing and buffer insertion methods. The gate sizing technique reduces not only glitches but also the effective circuit capacitance. After gate sizing, buffers are inserted into the remaining unbalanced paths which have not been subjected to gate sizing. ILP has been employed to determine the location of inserted buffers. The proposed algorithm has been tested on LGSynth91 benchmark circuits. Experimental results show that 61.5% of glitches are reduced on average     

Model for Transient Fault Susceptibility of Combinational Circuits

Transient faults (TFs) are increasingly affecting microelectronic devices as their size decreases. During the design phase, the robustness of circuits for high reliability applications with respect to this kind of faults is generally validated through simulations. However, traditional electrical level simulators are too slow for the task of simulating the effects of TFs on large circuits. In this paper, we present a new model to estimate accurately the possible propagation of transient fault-due glitches through a CMOS combinational circuit. We will show how the proposed model can be applied in order to estimate the TF susceptibility of a circuit by simply considering the propagation delay of the datapath. Therefore, the proposed model is suitable to be used into a new simulation tool able to provide good accuracy, while significantly speeding up simulations, with respect to electrical level simulation. In particular, our model allows approximately 90% accuracy with respect to HSPICE simulations.     

GlitchLess: Dynamic Power Minimization in FPGAs Through Edge Alignment and Glitch Filtering

This paper describes GlitchLess, a circuit-level technique for reducing power in field-programmable gate arrays (FPGAs) by eliminating unnecessary logic transitions called glitches. This is done by adding programmable delay elements to the logic blocks of the FPGA. After routing a circuit and performing static timing analysis, these delay elements are programmed to align the arrival times of the inputs of each lookup table (LUT), thereby preventing new glitches from being generated. Moreover, the delay elements also behave as filters that eliminate other glitches generated by upstream logic or off-chip circuitry. On average, the proposed implementation eliminates 87% of the glitching, which reduces overall FPGA power by 17%. The added circuitry increases the overall FPGA area by 6% and critical-path delay by less than 1%. Furthermore, since it is applied after routing, the proposed technique requires little or no modifications to the routing architecture or computer-aided design (CAD) flow.      

FPGA器件的竞争与冒险现象及消除方法

现场可编程门阵列(FPGA)由于其内部构成，容易引起竞争冒险现象，从而使电路工作的稳定性大受影响，电路也容易产生误动作，以致产生意想不到的后果。本文详细介绍了冒险现象的产生，并结合实例介绍了消除竞争冒险现象的各种方法。这些方法主要通过改变设计，破坏毛刺产生的条件来减少毛刺的发生。他能够使FPGA设计中毛刺的出现几率减到最小，大大减少了逻辑错误，加强了电路工作的稳定性，有效地抑制了干扰，使设计也更加优化、合理。     

A Unified Detection Scheme for Crosstalk Effects in Interconnection Bus

For very deep sub-micrometer VLSI, crosstalk becomes an important issue in affecting performance and signal integrity of the circuits. Two crosstalk fault effects, namely, glitch and crosstalk-induced delay, in the system-on-chip (SOC) interconnect bus are analyzed and a unified scheme to detect them is proposed and demonstrated in this paper. The crosstalk induced delay is found to be superposition of the induced glitch and the applied signal at the victim line, and this effect is more important in affecting the circuit performance. A pulse detector with an adjustable detection threshold is proposed to detect glitches and consequently the induced delay. Several issues affecting the yield of the proposed testing scheme are discussed and Monte Carlo simulations are conducted to show the feasibility of the scheme.      

A new CAD tool for Single Event Transient Analysis and mitigation on Flash-based FPGAs

Flash-based Field Programmable Gate Array (FPGA) devices are nowadays golden core of many applications especially in space and avionic fields where reliability is an important concern. In particular, for Flash-based FPGAs, when adopted in those applications, the main concern is radiation-induced voltage glitches known as Single Event Transient (SET) in the combinational logic. In this work, a new CAD tool is presented for evaluating the sensitivity of the implemented circuit regarding SET and mitigating this effect. This tool has been applied to EUCLID space mission project including more than ten modules. The experimental results demonstrate the efficiency of the proposed tool.     

Glitch reduction in second-generation SI circuits

A simple method for reducing the glitches of second-generation SI circuits is presented. For a given SI circuit it is sufficient to apply this technique only to the last stage     

Extensible supply voltage control mechanism for low power array structure design

A novel supply voltage switching control mechanism, called D-logic, for reducing power dissipation of array structures is presented. With this D-logic mechanism, the supply voltage levels are successively activated by external clock signal in the direction of signal propagation, which eliminates power dissipated by the glitches. The mechanism is easily incorporated with minimal circuit change in the existing array structure, and the speed of the array structure can be maintained. We have reduced the energy consumption of the multipliers and CORDICs as much as 50% with the proposed D-logic circuitry.     

基于毛刺阻塞原理的低功耗双边沿触发器

当输入信号存在毛刺时,双边沿触发器的功耗通常会显著增大,为了有效降低功耗,提出一种基于毛刺阻塞原理的低功耗双边沿触发器。在该双边沿触发器中,采用了钟控CMOS技术C单元。一方面,C单元能有效阻塞输入信号存在的毛刺,防止触发器锁存错误的逻辑值。另一方面,钟控CMOS技术可以降低晶体管的充放电频率,进而降低电路功耗。相比其他现有双边沿触发器,该双边沿触发器在时钟边沿只翻转一次,大幅度减少了毛刺引起的节点冗余跳变,有效降低了功耗。与其他5种双边沿触发器相比,该双边沿触发器的总功耗平均降低了40.87%~72.60%,在有毛刺的情况下,总功耗平均降低了70.10%~70.29%,仅增加22.95%的平均面积开销和5.97%~6.81%的平均延迟开销。     

Applying Analog Techniques in Digital CMOS Buffers to Improve Speed and Noise Immunity

A digital CMOS buffer circuit with avoltage transfer characteristic (VTC) with lowthreshold voltage detection, hysteresis, andhigh noise immunity is presented. The circuitis capable of restoring slow transition timesand distorted input signals with a minimumdelay penalty, offering at the same time highnoise immunity to glitches induced eitherthrough capacitive coupling or from the powersupply lines. The high noise immunity of theproposed buffer circuit is achieved usingdifferential mode rejection and a differentialredundant circuit architecture.     

A 4-kB 500-MHz 4-T CMOS SRAM using low-V/sub THN/ bitline drivers and high-V/sub THP/ latches

The design and physical implementation of a prototypical 500-MHz CMOS 4-T SRAM is presented in this work. The latch of the proposed SRAM cell is realized by a pair of cross coupled high-V/sub THP/ pMOS transistors, while the bitline drivers are realized by a pair of low-V/sub THN/ nMOS transistors. The wordline voltage compensation circuit and bitline boosting circuit, then, are neither needed to enhance the data retention of memory cells. Built-in self-refreshing paths make the data retention possible without the appearance of any external refreshing mechanism. The advantages of dual threshold voltage transistors can be used to reduce the access time, and maintain data retention at the same time. Besides, a new design of cascaded noise-immune address transition detector is also included to filter out the unwanted chip select glitches when the SRAM is asynchronously operated.     

Dynamic logic CMOS circuits

A structure of dynamic CMOS logic based on the direct interconnection of p-channel logic and n-channel logic dynamic gates is reported. Prevention of glitches and other circuit problems are discussed. Application to a 16-bit parallel-adder design resulted in improved speed as well as important savings in layout area when compared to standard static design.     

Modeling of glitches due to rise/fall asymmetry in current-steering digital-to-analog converters

The current-steering digital-to-analog converter (DAC) is the most common type of DAC for high-speed applications. Glitches present in the DAC output contribute to nonlinear distortion in the DAC transfer characteristics degrading the circuit performance. One source of glitches is asymmetry in the settling behavior when switching on and off a current source. A behavioral-level model of this nonideal behavior is derived in this work. Further, a method with low computational complexity for estimating the influence of the modeled errors in the frequency domain is developed. This method can be utilized by circuit designers to derive circuit requirements for fulfilling a given frequency-domain specification, potentially relaxing the requirements compared with a worst-case analysis. Examples of model utilization are given in terms of an analytical examination and MATLAB simulations. A good agreement between simulated and analytical results is obtained.     

A Programmable 210-μV Offset Rail-to-Rail Gm –C Filter

Low input-referred offset performance and linearity in analog filters are critical design parameters, yet transistor mismatch limitations are a severe hindrance. Programmability is also a feature of growing significance because high performance state-of-the-art systems must adapt on-the-fly to various operating conditions, as is the case in battery-operated electronics where systems traverse through idle, alert, and high performance modes in an effort to conserve energy and extend battery life. This paper presents a continuous and programmable first-order G_m-C filter with sub-millivolt offset performance. Low offset is achieved by auto-zeroing and continuity by ping-ponging between two transconductors, all under the construct of a compact and bandwidth-efficient circuit topology. The proposed G_m-C circuit was fabricated with AMI's 0.5-mum CMOS process technology and achieved an input-referred offset of less than 210 muV, hand-over glitches of less than 40 mV, and 57 dB of linearity over the rail-to-rail input span for a lithium-ion battery supply range of 3 to 4.2 V. The bandwidth and gain of the filter were programmable from 1.1 to 6.5 kHz and 1.27 to 29.1 V/V, respectively, both with better than 3.2% resolution.     

On-Chip Transient Detection Circuit for System-Level ESD Protection in CMOS Integrated Circuits to Meet Electromagnetic Compatibility Regulation

A new on-chip transient detection circuit for system-level electrostatic discharge (ESD) protection is proposed. The circuit performance to detect different positive and negative fast electrical transients has been investigated by the HSPICE simulator and verified in a silicon chip. The experimental results in a 0.13-m CMOS integrated circuit (IC) have confirmed that the proposed on-chip transient detection circuit can be used to detect fast electrical transients during the system-level ESD events. The proposed transient detection circuit can be further combined with the power-on reset circuit to improve the immunity of the CMOS IC products against system-level ESD stress.     

G-vector: A New Model for Glitch Analysis in Logic Circuits

One of the major factors which contribute to the power consumption in CMOS combinational logic circuits is the switching activities in the circuits. Many of such switching activities are due to spurious pulses, called glitches. In this paper, we propose a new model for describing signals that contain glitches, called G-vector. Unlike the previous works in which their primary concern is modeling the propagation of glitches to count the number of glitches in the circuits, our G-vector provides a general, but effective model for generation, propagation and elimination of glitches, enabling us to not only count the number of glitches but also locate the glitches so that such information can be utilized by system tools for the reduction of the number of glitches in the circuits. We provide a set of experimental results to demonstrate the effectiveness of our model.     

Transient hot-electron effect and its impact on circuit reliability

Transient hot-electron effect and its impact on circuit reliability are investigated. The rate of device decay is monitored as a function of the gate pulse transient period. Simulation results reveal that excess charges during a fast turn off time may cause an increase in the maximum substrate current. This, along with our experimental data, identifies that transient excess carrier may cause the enhancement of device degradation under certain stress conditions. The enhancement factor of the degradation is a function of the gate pulse transient time. Correlation between the analysis based upon AC/DC measurement and calculations based upon transient simulation are shown in the paper. Better agreement with experimental data is obtained by using the transient analysis and on chip test/stress structures. The correlation between AC and DC stress data is also shown based on the impact ionization model. A hot-electron design guideline is proposed based on the circuit reliability analysis. This guideline can help improve the circuit reliability without adversely effecting the circuit performance.     

Limitations of looped-line scheme for overcoming wired-or glitch effects

The letter makes some general observations on the occurrence of glitches on wired-OR lines, and points out the limitations of a recently proposed scheme for avoiding their ill-effects. Possible alternatives are discussed, one being an extension of the proposal in question.