Substitute voice production: quantification of PE segment vibrations using a biomechanical model

After total larynx excision due to laryngeal cancer, the tracheoesophageal substitute tissue vibrations at the intersection between the pharynx and the esophagus [pharyngoesophageal segment (PE segment)] serve as voice generator. The quality of the substitute voice significantly depends on the vibratory characteristics of the PE segment. For improving voice rehabilitation, the relationship between the PE dynamics and the resulting substitute voice quality is a matter of particular interest. Precondition for a comprehensive analysis of this relationship is an objective quantification of the PE vibrations. For quantification purposes, a method is proposed, which is based on the reproduction of the tissue vibrations by means of a biomechanical model of the PE segment. An optimization procedure for an automatic determination of appropriate model parameters is suggested to adapt the model dynamics to tissue movements extracted from high-speed (HS) videos. The applicability of the optimization procedure is evaluated with ten synthetic data sets. A mean error of 8.2% for the determination of previously defined model parameters was achieved as well as an overall stability of 7.1%. The application of the model to six HS recordings presented a mean correlation of the vibration patterns of 82%.     

Estimation of the Phonetic Speech Quality Using the Information Theoretic Approach

The problem of estimation of the speech phonetic quality using a short fragment of the voice signal is formulated. The Kullback–Leibler minimum information discrimination principle is used to propose a novel criterion and develop an algorithm. The dynamic properties of the algorithm are analyzed. The algorithm is employed in the analysis of the functional state of speaker using the voice signal. It is demonstrated that the needed duration of the voice signal is several minutes only.     

An on-chip march pattern generator for testing embedded memorycores

In this correspondence, we propose an effective approach to integrate 40 existing march algorithms into an embedded low hardware overhead test pattern generator to test the various kinds of word-oriented memory cores. Each march algorithm is characterized by several sets of up/down address orders, read/write signals, read/write data, and lengths of read/write operations. These characteristics are stored on chip so that any desired march algorithm can be generated with very little external control. An efficient procedure to reduce the memory storage for these characteristics is presented. We use only two programmable cyclic shift registers to generate the various read/write signals and data within the steps of the algorithms. Therefore, the proposed pattern generator is capable of generating any march algorithm with small area overhead     

Research on End-to-End Encryption of TETRA

1Introduction TETRAisanETSI standardizeddigitalradiooperat ingsystembasedontrunkedmobileradiotechnolo gy[1-3].ItistypicallydesignedfortheProfessionalMo bileRadio(PMR)marketandincludessystems,typi callyforMilitaryandPublicSafetyorganizations,as wellasPubli…     

Synchronous quantized subcarrier multiplexing for transport ofvideo, voice, and data

A quantized subcarrier multiplexing approach for the transmission of video, voice, and data information over optical fiber networks is explored. The basis of this technique is to utilize a single high-speed analog-to-digital converter to digitize a composite analog signal. Conventional subcarrier multiplexing methods are used to form the composite from multiple NTSC video, voice, and data signals. The process of synchronous multiplexing, quantization, serialization, transmission, and waveform recovery is explored for an experimental prototype system. Noise performance and the impact on laser linearity requirements are discussed     

Picosecond-Pulse Sequential Waveform Generation (Short Papers)

This short paper describes a novel method of generating a pulse sequence using step-recovery diodes (SRDs) shunting a transmission line. Individual pulses in the train may have rise times less than 60 ps with amplitudes greater than 10 V. The many potential applications of the device include a short RF pulse generator, an FM generator, and a high-speed word generator.     

Enhancement of the noise immunity of a voice-activated robotics control system based on phonetic word decoding method

The problem of protection of a voice-activated robotics control system against the acoustic noise similar to the speaker voice is investigated. A new algorithm for voice signal processing using the phonetic word decoding method and the (R+1) information element is proposed. The results of the experimental study of this algorithm are reported. It is shown that the developed algorithm reduces the false alarm ratio by and an order of magnitude or even more and retains high probability of correct voice recognition.     

声音转换技术的研究与进展

声音转换是一项改变说话人声音特征的技术,可以将一人的语音模式转换为与其特性不同的另一人语音模式.声音转换算法的目标是确定一个什么样的模式转换规则,使转换语音保持第一个说话人原有语音信息内容不变,而具有第二个说话人的声音特点.本文介绍了当前声音转换技术领域的研究状态,主要分析现有声音转换技术中各种转换算法的实现原理,描述声音转换系统性能的各种评估方法,最后给出了对声音转换技术的简要评述和展望.     

高速铁路有效覆盖电平与站间距分析

本文首先对高速铁路的两大覆盖难点进行了介绍,并归纳总结了国内现有高速铁路主流的4种覆盖模式,尤其对高铁专网结构进行了简介。同时,辅以国内某高铁GSM和TD-SCDMA专网海量测试数据为基础,通过载干比、话音质量剖析了有效覆盖电平范围值。其次,对高铁专网分场景下的站间距、有效覆盖电平和成本三因素点进行了综合考评并提出相应站点设计建议。最后,结合高速铁路的两大覆盖难点对未来高铁覆盖模式进行了展望。     

一种快速获取同频数据的防碰撞算法

文章在碰撞二叉树算法(CT)技术的基础上提出一种用于433 MHz频段下的标签防碰撞算法——改进型碰撞二叉树算法(ICT),可以很好地对各类土地的地形分布数量等特征进行测量。该算法根据首次碰撞码字进行前缀生成和标签组区分,在标签快速识别中,对每一个标签使用了一个计数器和一个指针,用来记录阅读器的历史序列,从而使得阅读器不需要传输整个前缀序列。仿真结果表明,ICT算法在当标签ID具有类似的前缀时,表现出优于CT算法的性能。     

A movement pattern generator model using artificial neural networks

Artificial neural networks (ANN's) allow a new approach to biological modeling. The main applications of ANN's have been geared towards the modeling of the association and learning mechanisms of the brain; only a few researchers have explored them for motor control. The fact that ANN's are based on biological systems indicates their potential application for a biological act such as locomotion. Towards this goal, we have developed a "movement pattern generator," using an ANN for generating periodic movement trajectories. This model is based on the concept of "central pattern generators." Jordan's sequential network, which is capable of learning sequences of patterns, was modified and used to generate several bipedal trajectories (or gaits), coded in task space, at different frequencies. The network model successfully learned all of the trajectories presented to it. The model has many attractive properties such as limit cycle behavior, generalization of trajectories and frequencies, phase maintenance, and fault tolerance. The movement pattern generator model is potentially applicable for improved understanding of animal locomotion and for use in legged robots and rehabilitation medicine.     

Novel Secure Pseudorandom Number Generator Based on Duffing Map

The fields of applied sciences and engineering require Pseudorandom Number Generators which exhibit useful statistical properties. In this paper, a novel algorithm for generating pseudorandom numbers has been proposed. This new algorithm is based on Duffing map. The aim of this paper is to generate pseudorandom bit streams based on chaotic map. The main objective is to find its potential to be used in applied sciences and engineering applications. To use this algorithm effectively in practical applications, the strength of this algorithm has been tested using various statistical tests like initial seed value, key sensitivity test, CPU performance test and pseudorandom orbit. The proposed pseudorandom number generator is further analyzed and evaluated with NIST statistical test suite. The results obtained from these experimental and statistical tests demonstrate and prove that the new generator has the potential to be applied successfully in mathematical sciences, applied physics, computer science and electrical engineering etc.     

A numerical pattern synthesis algorithm for arrays

A numerical technique for pattern synthesis in arrays is presented. For a given set of elements, the technique allows one to find a set of array coefficients that steer the main beam in a given direction and yield sidelobes meeting a specified criterion, if such a set of array coefficients exists. If the pattern specifications cannot be met with the given elements, the algorithm finds the best attainable pattern. The advantage of this technique is that it can be used with an arbitrary set of array elements. Different elements in the array can have different element patterns, and the array can have arbitrary nonuniform spacing between elements. The synthesis technique is based on adaptive array theory. The given array elements are assumed to be used as the elements of an adaptive array. The main beam is pointed in the proper direction by choosing the steering vector for that direction, and the sidelobes are controlled by introducing a large number of interfering signals at many angles throughout the sidelobe region. The algorithm iterates on the interference powers until a suitable pattern is obtained     

基于ANSYS的工形压电发电装置有限元分析

针对目前悬臂梁压电发电装置的局限性,设计了一种工形的压电发电装置。运用ANSYS有限元软件建立了工形压电发电装置的有限元模型,并进行了静力分析及模态分析。分析结果表明,该工形压电发电装置的最大应变出现在每个转角折弯处,且每个转角折弯处的应变基本一致。根据压电方程可知,该处将产生最大的发电电压,所以在此粘贴压电片将具有最佳的发电能力。通过建立发电装置的压电耦合分析模型,计算得到在0.1mm的位移载荷作用下,每片压电片上将产生约15.1V的电压。最后,对该工形压电发电装置进行了参数化研究,结果表明,当选择长80 mm、宽15 mm、厚0.4 mm的压电工形板时,发电效果最佳,最大发电电压可达16.5V。     

A Jitter Injection Signal Generation and Extraction System for Embedded Test of High-Speed Data I/O

An instrument for on-chip measurement of transceiver transmission capability is described that is fully realizable in CMOS technology and embeddable within an SoC. The instrument can be used to inject and extract the timing and voltage information associated with signals in high-speed transceiver circuits that are commonly found in data communication applications. At the core of this work is the use of ΣΔ amplitude- and phase-encoding techniques to generate both the voltage and timing (phase) references, or strobes used for high-speed sampling. The same technique is also used for generating the test stimulant for the device-under-test.     

Implementation of scalable power and area efficient high-throughputViterbi decoders

Today's data reconstruction in digital communication systems requires designs of highest throughput rate at low power. The Viterbi algorithm is a key element in such digital signal processing applications. The nonlinear and recursive nature of the Viterbi decoder makes its high-speed implementation challenging. Several promising approaches to achieve either high throughput or low power have been proposed in the past. A combination of these is developed in this paper. Additional new concepts allow building a signal-flow graph suitable for the design of high-speed Viterbi decoders with low power. Using a flexible datapath generator facilitates the essential quantitative optimization from architectural down to physical level to fully exploit the low-power and high-speed potential of a given technology. With parameterizable design entry, this datapath generator establishes the basis of a scalable platform-based design library. Altogether, this allows coverage of the range of today's industrial interest in high throughput rates, from 150 Msymbols/s up to 1.2 Gsymbols/s using conventional CMOS logic. The features of two exemplary Viterbi decoder implementations prove the benefit of this physically oriented design methodology in terms of speed and low power, when compared to other leading edge implementations     

A 500-Mb/s quadruple data rate SDRAM interface using a skewcancellation technique

A quadruple data rate (QDR) synchronous DRAM (SDRAM) interface processing data at 500 Mb/s/pin with a 125-MHz external clock signal is presented. Since the QDR interface has a narrower data timing window, a precise skew control on data signals is required. A salient skew cancellation technique with a shared skew estimator is proposed. The skew cancellation circuit not only reduces the data signal skews on a printed circuit board down to 250 ps, but also aligns the data signals with an external clock signal. The entire interface, fabricated in a 0.35-μm CMOS technology, includes a high-speed data pattern generator and consumes 570 mW of power at 3.0-V supply. The active die area of the chip with the on-chip data pattern generator is 2.4 mm²     

Design of Broadband Planar Arrays Based on the Optimization of Aperiodic Tilings

Antenna arrays based on aperiodic tilings have been shown to exhibit low sidelobe levels and modest bandwidths over which grating lobes are suppressed. In addition, compared to conventional periodic arrays, these arrays are naturally thinned (i.e., mean inter element spacing is greater than ). The generation of these arrays involves placing array elements at the locations of the vertices of an aperiodic tiling. To obtain a realizable design, the entire array is then scaled and truncated to achieve a desired minimum element spacing and aperture size. This paper demonstrates that it is possible to greatly extend the bandwidth of these arrays by incorporating a simple perturbation scheme into the basic array generation process. The implementation of this perturbation scheme is straightforward and it lends itself well to being combined with an optimization technique such as the genetic algorithm. It is successfully used to generate arrays that have large bandwidths (peak sidelobe level dB with no grating lobes) of up to a minimum element spacing of . Moreover, the flexibility of this technique will be further demonstrated by introducing a slight variation of the basic scheme that is capable of generating arrays with extremely wide bandwidths. An example will be presented for an array design that has a bandwidth corresponding to a minimum element spacing of up to .     

基于FPGA的3 GHz宽带信号产生器设计

为适应通信对抗装备的发展,设计了能产生3GHz带宽任意波形的信号产生器。现场可编程门阵列(FPGA)产生数字波形信号,通过高速数/模转换(DAC)芯片输出模拟信号。在FPGA中采用多路并行处理算法,利用内部集成的并串转换器以及专用的复用芯片(MUX),实现DAC数据速率8Gsps,输出信号瞬时带宽3GHz以上。最后测试了信号产生器的技术指标。     

Silicon bipolar IC for PRBS testing generates adjustable bit ratesup to 25 Gbit/s

For the first time, a completely integrated pseudo-random pattern generator providing adjustable bit rates up to at least 25 Gbit/s without additional external multiplexing is presented. The sequence length is 2ⁿ-1. The application of the monolithic Si bipolar IC serves as a single chip measurement instrument for pseudo-random binary sequence (PRBS) generation required for the characterisation and development of high-speed components used in future optical fibre communication systems. Only three external microwave components are needed for operation: a clock generator, a power divider and a phase shifter. The chip is realised in an advanced implanted base silicon bipolar technology