A Semantics-based Translation Method for Automated Verification of SystemC TLM Designs

SystemC has become a de-facto standard language for SoC and ASIP designs. The verification of implementation with SystemC is the key to guarantee the correctness of designs and prevent the errors from propagating to the lower levels. In this project, we attempt translate SystemC programs to formal models and use existing model checkers to implement the verification. The method we proposed is based on a semantic translation method which translates sequential execution statements described as software character to parallel execution ones which are more closely with the implementation of hardware. This kind of conversion is inevitable to verify hardware designs but is overlooked in related works. The main contribution of this work is a translation method which can preserve the semantic consistency while building SMV model for SystemC design. We present the translation rules and implement a prototype tool which supports a subset of SystemC to demonstrate the effectiveness of our method.     

Mining metadata for composability of IPs from SystemC IP library

Exploring the design space when constructing a system is vital to realize a well performing design. Design complexity has made building high-level system models to explore the design space an essential but time-consuming and tedious part of the system design. Reduction in design time and acceleration of design exploration can be provided through reusing IP-cores to construct system models. As a result, it is common to have high-level SoC design flow based on IP libraries promoting reuse. However, the success of these would be dependent on how introspection and reflection capabilities are provided as well as what are the interoperability standard defined. This leads to the important question of what kind of IP metadata must be available to allow CAD tools to effectively manipulate these designs as well as allow for a seamless integration and exchange design information between tools and design flows. In this article, we describe our tools and methodology, which allow introspection of SystemC designs, such that the extracted metadata enables IP composition. We discuss the issues related to extraction of metadata from IPs specified in SystemC and show how our methodology combines C++ and XML parsers and data structures to achieve the above.     

使用SystemC设计片上自演化系统

提出片上自演化系统的概念和基于SystemC的片上自演化系统设计方法,给出片上自演化系统的总体结构,使用SystemC建模搭建自演化系统实验平台.以典型低通切比雪夫滤波器为例,验证了实验平台的有效性.使用SystemC设计自演化系统既可在较高的抽象水平搭建自演化系统模型,加速验证、性能分析和探索系统结构,又可方便地进行软硬件协同设计,并最终达到硬件实现.     

Wishbone总线交易级建模

交易级建模在系统功能建模和验证方面可以增快速度,也可以加速仿真的速度并允许在高层次抽象中研究和确认设计中可供选择的模块.针对Wishbone片上总线协议,依据SystemC中接口方法调用的基本原理和交易级建模的方法,完成了Wishbone总线中共享总线的交易级建模,结果表明SystemC适合在交易级建模系统的行为和通信,交易级建模在仿真速度方面具有优势.     

TAPES—Trace-based architecture performance evaluation with SystemC

The design of today’s System-on-Chip (SoC) architectures faces many challenges in respect to the involved complexity and heterogeneity. An early and systematic exploration of alternatives is mandatory to find a solution that meets all design requirements. Therefore, the experience of system architects has to be supplemented with efficient performance evaluation methods and tools that help in the broad exploration of the solution space. This article describes TAPES (Trace-based Architecture Performance Evaluation with SystemC), an approach that supports system designers in the performance evaluation of SoC architectures. The concept captures the functionality of the architecture in the form of traces for each resource. The trace primitives making up a trace are translated at simulation run-time into transactions and superposed on the system architecture. The method uses SystemC as modeling language, requires low modeling effort and yet provides accurate results within reasonable turnaround times. A concluding application example for the exploration of a network processor architecture demonstrates the effectiveness of the TAPES approach.     

Computational reflection and its application to platform verification

The complexity of modern hardware design has created the need for higher levels of abstraction, where system modeling is used to integrate modules into complex System-on-Chip (SoCs) platforms. SystemC, and its TLM (Transaction Level Modeling) extensions, have been used for this purpose mainly because of their fast prototyping and simulation features, which allow for early design space exploration. This paper proposes an approach to explore and interact with SystemC models by means of an introspection technique known as Computational Reflection. We use reflection to implement a white-box introspection mechanism called ReflexBox. We show that ReflexBox is a fast, non-intrusive technique that can be used to dynamically gather and inject stimuli into any SystemC module, without the need to use a proprietary SystemC implementation, change the SystemC library, instrument or even inspect the module source code. Our approach can be used to support many different verification tasks like platform debugging, performance evaluation and communication analysis. To show ReflexBox effectiveness we used it in three platforms case studies to address tasks like register inspection, performance analysis and signal replaying for testbench reuse. In all cases we assumed no source code availability and measured the impact on the overall platform performance.     

Transaction-level power analysis of VLSI digital systems

The increasing complexity of VLSI digital systems has dramatically supported system-level representations in modeling and design activities. This evolution makes often necessary a compliant rearrangement of the modalities followed in validation and analysis tasks, as in the case of power performances estimation.Nowadays, transaction-level paradigms are having a wider and wider consideration in the research on electronic system-level design techniques. With regard to the available modeling resources, the most relevant framework is probably the transaction-level extension of the SystemC language (SystemC/TLM), which therefore represents the best platform for defining transaction-level design techniques.In this paper we present a macro-modeling power estimation methodology valid for SystemC/TLM prototypes and of general applicability. The present discussion illustrates the implementation modalities of the proposed approach, verifying its effectiveness through a comparison with RTL estimation techniques.     

基于ESL设计方法学的SOC设计

为了缩短产品上市时间并降低设计成本,ESL设计方法学已被越来越多的复杂SoC设计所采纳。本文以图像处理的SoC为例,利用可裁减的TLM2.0建模方法快速搭建系统,进行系统级验证,探索不同架构对系统性能的影响,并进一步生成虚拟原型,进行软件调试。借助于Mentor Graphics公司提供的ESL解决方案,将图像缩放模块的C++描述无误地综合成吞吐率为1pixel/clock的高质量RTL代码,同时生成反映硬件性能的TLM2.0模型,减少了ESL建模的工作量,极大地提高了设计效率,论证了ESL设计方学的可行性。     

基于SystemC的时钟周期精确交易级建模及通信细化

交易级建模通过提高建模抽象层次,加快了系统建模和仿真的速度。针对AMBA AHB协议,采用Sys-temC语言,进行了交易级建模及通信细化。结果表明,由于抽象层次部分结合了BCA(bus cycle-accurate)级描述,使得到的交易级模型包含了更多时间/协议信息,同时保留了速度优势,有利于前期验证和系统开发。而之后进行的通信细化,将抽象通道转化为模块实体和端口,对于最终RTL级实现具有重要意义。     

Performance Analysis of Arbitration Policies for SoC Communication Architectures

As technology scales toward deep submicron, the integration of a large number of IP blocks on the same silicon die is becoming technically feasible, thus enabling large-scale parallel computations, such as those required for multimedia workloads. The communication architecture is becoming the bottleneck for these multiprocessor Systems-on-Chip (SoC), and efficient contention resolution schemes for managing simultaneous access requests to the shared communication resources are required to prevent system performance degradation. The contribution of this work is to analyze the impact on multiprocessor SoC performance of different bus arbitration policies under different communication patterns, showing the distinctive features of each policy and the strong correlation of their effectiveness with the communication requirements of the applications. Beyond traditional arbitration schemes such as round robin and TDMA, another policy is considered that periodically allocates a temporal slot for contention-free bus utilization to a processor which needs fixed predictable bandwidth for the correct execution of its time-critical task. The results are derived on a complete and scalable multiprocessor SoC simulation platform based on SystemC, whose software support includes a complete embedded multiprocessor OS (RTEMS). The communication architecture is AMBA compliant, and we exploit the flexibility of this multi-master commercial standard, which does not specify the arbitration algorithm, to implement the explored contention resolution schemes.     

基于SystemC的片上系统设计

文章提出了基于SystemC的片上系统设计方法.本设计方法引入SystemC,消除了一直存在于系统级设计和硬件设计之间的语言隔阂,基于SystemC进行的系统功能定义能够方便有效地映射为硬件实现部分和软件实现部分,大大地提高了SOC时代集成电路设计效率.     

Platform designer: An approach for modeling multiprocessor platforms based on SystemC

This paper[3.5pc] presents the Platform Designer (PD) framework, a set of SystemC based tools that provide support for modeling, simulation and analysis of multiprocessor SoC platforms (MPSoC), at different abstraction levels. PD provides mechanisms for interconnection specification, process synchronization and communication, thus allowing the modeling of a complete platform, in a unified environment. To do that it uses an extension of the ArchC ADL and acsys, a tool that enables the automatic generation of a SystemC simulator of the platform. The main advantages of this approach are twofold. First, designers have more flexibility since they can integrate and configure different processors to the platform, using a single environment. Second, it enables a faster design space exploration, given that it automatically generates SystemC simulators of whole platforms at distinct abstraction levels. A number of platform variations can be tried out with minor design changes, thus reducing design time. Experimental results show the suitability of the platform simulator for design space exploration. Real applications (with medium complexity) run in the platform in few minutes. Combined with the facility to generate platforms with minor changes, this feature allows an improvement of the design space exploration.     

Design and verification of SystemC transaction-level models

Transaction-level modeling allows exploring several SoC design architectures, leading to better performance and easier verification of the final product. In this paper, we present an approach to design and verify SystemC models at the transaction level. We integrate the verification as part of the design flow where we first model both the design and the properties (written in Property Specification language) in Unifed Modeling Language (UML); then, we translate them into an intermediate format modeled with AsmL [language based on Abstract State Machines (ASM)]. The AsmL model is used to generate a finite state machine of the design, including the properties. Checking the correctness of the properties is performed on the fly while generating the state machine. Finally, we translate the verified design to SystemC and map the properties to a set of assertions (as monitors in C#) that can be reused to validate the design at lower levels by simulation. For existing SystemC designs, we propose to translate the code back to AsmL in order to apply the same verification approach. At the SystemC level, we also present a genetic algorithm to enhance the assertions coverage. We will ensure the soundness of our approach by proving the correctness of the SystemC-to-AsmL and AsmL-to-SystemC transformations. We illustrate our approach on two case studies including the PCI bus standard and a master/slave generic architecture from the SystemC library.     

Fast cycle-approximate MPSoC simulation based on synchronization time-point prediction

In this paper, we propose techniques for fast cycle-approximate multi-processor SoC simulation with timed transaction level models and OS models. Cycle-approximate simulation with an abstract model is widely used for fast validation of a multi-processor SoC in early design stages. However, the performance gain of abstract-level simulation is limited by the overhead of synchronizing multiple concurrent processor/module simulators, which is inevitable in timed simulation. To reduce the synchronization overhead, we adopt the synchronization time-point prediction method, which consists of two phases: static code analysis and dynamic scheduling of synchronizations. In the static analysis phase before simulation, it estimates minimum execution time from every point in the code to the nearest synchronization point. Then, during simulation, it pessimistically predicts the synchronization time-points based on the estimates. The proposed approach targets fast cycle-approximate simulation of a system with delay annotated SW code and transaction level models of HW with dynamic behavior. We present, in this paper, techniques to analyze such abstract models of SW and HW and schedule minimal number synchronizations during cycle-approximate simulation of the models. Experiments show that the approach achieves orders of magnitude higher performance in cycle-approximate multi-processor SoC simulation.     

High-level customization framework for application-specific NoC architectures

Network-on-Chip (NoC) has been recognized as the new paradigm to interconnect and organize a high number of cores. NoCs address global communication issues in System-on-Chips (SoC) involving communication-centric design and implementation of scalable communication structures evolving application-specific NoC design as a key challenge to modern SoC design. In this paper we present a SystemC customization framework and methodology for automatic design and evaluation of regular and irregular NoC architectures. The presented framework also supports application-specific optimization techniques such as priority assignment, node clustering and buffer sizing. Experimental results show that generated regular NoC architectures achieve an average of 5.5 % lower communication-cost compared to other regular NoC designs while irregular NoCs proved to achieve on average 4.5×higher throughput and 40 % network delay reduction compared to regular mesh topologies. In addition, employing a buffer sizing algorithm we achieve a reduction in network’s power consumption by an average of 45 % for both regular and irregular NoC design flow.