CORDIC based fast algorithm for power-of-two point DCT and its efficient VLSI implementation

—In this paper, we present a coordinate rotation digital computer (CORDIC) based fast algorithm for power-of-two point DCT, and develop its corresponding efficient VLSI implementation. The proposed algorithm has some distinguish advantages, such as regular Cooley-Tukey FFT-like data flow, identical post-scaling factor, and arithmetic-sequence rotation angles. By using the trigonometric formula, the number of the CORDIC types is reduced dramatically. This leads to an efficient method for overcoming the problem that lack synchronization among the various rotation angles CORDICs. By fully reusing the uniform processing cell (PE), for 8-point DCT, only four carry save adders (CSAs)-based PEs with two different types are required. Compared with other known architectures, the proposed 8-point DCT architecture has higher modularity, lower hardware complexity, higher throughput and better synchronization.     

Digital-filter functions with fast coefficient implementation: an addendum

Five parallel transfer function formulations for digital filters are given. The coefficients in these allow a simple and very fast multiplication process. These functions provide a maximum bandwidth of about double that of an earlier set.     

Energy efficient reputation mechanism for defending different types of flooding attack

Wireless Networks - Delay tolerant network solves technical challenges in the heterogeneous network that may lack end-to-end connectivity. However, due to the disconnected paths, message delivery...     

New fast computational structures for an efficient implementation of the forward/backward MDCT in MP3 audio coding standard

New fast computational structures identical for an efficient implementation of both the forward and backward modified discrete cosine transform (MDCT) in MPEG-1/2 Layer III (MP3) audio coding standard are described. They are based on a new proposed universal fast rotation-based MDCT computational structure [V. Britanak, New universal rotation-based fast computational structures for an efficient implementation of the DCT-IV/DST-IV and analysis/synthesis MDCT/MDST filter banks, Signal Processing 89 (11) (November 2009) 2213–2232]. New fast computational structures are derived in the form of a linear code and they are particularly suitable for high-performance programmable DSP processors. For the short audio block it is shown that our efficient MDCT implementation in MP3 can be modified to achieve the same minimal multiplicative complexity compared to that of Dai and Wagh [An MDCT hardware accelerator for MP3 audio, in: Proceedings of the IEEE Symposium on Application Specific Processors (SASP’2008), Anaheim, CA, June 2008, pp. 121–125].     

RTOS modeling in SystemC for real-time embedded SW simulation: A POSIX model

SystemC is committed to support the requirements for an integrated, HW/SW co-design flow, thus allowing the development of complex, multiprocessing, Systems-on Chip (MpSoC). To make this possible, efficient modeling and simulation methodologies for Real-Time, Embedded (RT/E) SW in SystemC have to be developed, so that the designer can verify and refine the application SW together with the rest of the elements of the platform. Accurate modeling of the application SW requires an accurate model of the RTOS. Nevertheless, low-level, dynamic timing characteristics of the RTOS such as time-slicing, priority-based preemptive scheduling, interrupts and exceptions do not have a direct implementation in SystemC. In this paper, techniques are proposed to accurately model the detailed RTOS functionality on top of the SystemC execution kernel. The model allows timed-simulation and refinement of the RT/E SW code in SystemC. The simulation technology has been applied to the development of a high-level, POSIX simulation library in SystemC. The library allows the designer a fast, sufficiently accurate, timed simulation of the application SW running on top of POSIX. As most current RTOSs support this standard, the library is portable to different development frameworks. The library provides the required infrastructure for a complete, multiprocessing, HW/SW co-simulation environment at different abstraction levels using SystemC.     

ELDA: an efficient and low-cost protocol for data authentication for IoT

Wireless Networks - While data is being transmitted from device-to-device in any IoT network over un-trusted channel, there will appear the security challenges such as data integrity,...     

Comparison of practical methods for an efficient FPGA implementation of STAP

In this paper, practical methods for an efficient field programmable gate array (FPGA) implementation of space-time adaptive processing (STAP) are investigated and compared. The most important part for calculating the STAP weights is QR decomposition (QRD) which can be implemented using the modified Gram–Schmidt algorithm. Investigations show the method that uses QRD with less computational burden and leads to more effective implementation. Its structure parameterised with vector size to create a trade-off between hardware and performance factors. For this purpose, the modifications on QRD-MGS are performed in order to speed increasing. Then, the calculation of STAP weight vector was implemented. The implementation results show that decreasing vector size decreases the resources utilisation, computational burden and consumption power. However, computation time increases slightly, but the update rate of the STAP weights is maintained. For example, weights in the system with 6 antenna arrays, 10 received pulses and 200 range samples computed in 262 µs by vector size of 17 on the Arria10 FPGA the maximum of which is 155 µs are related to QRD-MGS and 107 µs is related to other parts. Therefore, QRD-MGS is the most important part in calculation of the STAP weight vector and its simplifying led to an efficient implementation.

Abbreviations: Computation time, Field programmable gate array, QR decomposition, Space time adaptive processing     

Comparison of practical methods for an efficient FPGA implementation of STAP

This study investigated and compared the practical methods used for the efficient Field- Programmable Gate Array (FPGA) implementation of space-time adaptive processing (STAP). The most important part of calculating the STAP weights is the QR decomposition (QRD), which can be implemented using the modified Gram-Schmidt (MGS) algorithm. The results show that the method that uses QRD with less computational burden leads to a more effective implementation. Its structure was parameterised with the vector size to create a trade-off between the hardware and performance factors. For this purpose, QRD-MGS algorithm was first modified to increase the speed, and then the STAP weight vector was calculated. The implementation results show that decreasing the vector size decreases the resource utilisation, computational burden and the consumption power. While the computation time increases slightly, the updated rate of the STAP weights is maintained. For example, the STAP weights in a system with 6 antenna arrays, 10 received pulses and 200 range samples computed in 262 µs using a vector size of 17 on the Arria10 FPGA that has a maximum of 155 µs correlates to the QRD-MGS algorithm and 107 µs correlates to the other parts. Therefore, QRD-MGS algorithm is the most important component of the calculation of the STAP weight vector, and its simplification leads to efficient implementation.     

Toward an efficient implementation of the MOCUS algorithm

MOCUS is probably the most famous algorithm to compute minimal cutsets of fault trees. It was proposed by Fussell and Vesely in 1972. It is now the core method of many fault-tree assessment tools. Despite its wide use, textbooks and articles give very few details about how to implement it. This paper describes data structures as well as several improvements and heuristics that make MOCUS very efficient. Experiments on a benchmark of the 1819 event-tree sequences that were generated during a PSA study are reported. Advantages and drawbacks of MOCUS and Binary Decision Diagrams are discussed.     

一种高效的移动互联网网站安全监测方法研究与实现

本文对一种高效的移动互联网网站安全监测方法进行了研究,提出了一种高效率的网站安全综合监测技术方案,并进行了实现,能够集中、统一对网站系统的实时安全状态进行监测,可为网站安全管理及监测工作提供汇总的统计数据,量化工作取得的成绩。可实现对移动互联网网站安全情况进行实时统一监测,准确、及时发现各网站存在的安全漏洞等隐患。     

一组高效LDPC码空间通信方案设计与实现

对基于欧氏几何的QC-LDPC码的数学基础进行了分析与阐述,从原理上分析了此类LDPC码性能优异的原因,并结合CCSDS所推荐的适用于近地通信的（8160,7136）码,建立了此类LDPC码的普适性构造方法.针对航天任务中资源、功耗、码速率的严格要求,设计了一套完备的空间通信编码方案,采用移位寄存累加电路单元（SRAA）,分别设计针对面积优化的串行编码电路和针对速度优化的并行编码电路.使用Xilinx Virtex-4 FPGA测试串行编码速率可达210 Mbps以上,并行编码速率最高可达2 Gbps左右.     

基于信息汇聚平台的快数据应用设计与实现

用户行为信息中蕴含着巨大的价值,如何采集并加工用户行为信息,使之成为新的业务增长点,是运营商面临的重要课题.通过对信息汇聚、采集、加工等关键技术的研究,给出了基于信息汇聚平台的快数据应用的实现方案,能够通过用户开关机、位置变化、语音通话等行为触发用户关怀、企业名片、信息推送等业务,该方案已经广泛用于电信运营商的新兴业务领域,取得了显著的经济效益.     

适用于快速线机器人高效作业的节拍控制系统设计与实现

针对目前彩电行业检测生产线生产节拍冗长、机器人作业效率低的问题,提出了一种基于双移栽生产线的适用于机器人快速作业的节拍控制系统,并重点研究其节拍控制系统的设计与实现.首先,采用单动力的双移栽机构进行拼接柔性组线,使传统的单通道流水线变成了双通道;其次,设计了一种节拍智能控制系统对产品进行智能调度,在解决流水线堵塞问题的同时提高了产品的生产节拍以及检测机器人的作业效率.本文提出的研究方法在创维-RGB电子有限公司深圳工厂智能整机模组一体化L线进行了验证,与传统的检测线相比,结果表明:产线拥堵情况得到了极大的改善,检测段生产节拍提高了22.75％,该方法对于提高生产效率较为显著,亦可推广到制造行业的其他领域.     

The ERPC: an efficient error-resilient technique for encodingpositional information or sparse data

In many source and data compression schemes, information relating to positions of high-energy samples or areas of importance often needs to be relayed to the decoder. The error resilient positional code (ERPC) is an efficient fixed-rate coding scheme for encoding such positional information, or, equivalently, sparse binary data patterns. It has also been designed with good channel error robustness properties, such that the decoded data quality degrades gracefully with worsening channel conditions, without the possibility of catastrophic breakdown or loss of sync. In this work, the coding efficiency of the ERPC is compared to a few other standard schemes. It is found to be efficient and its error extension in terms of the expected number of samples corrupted per bit error is reported and shown to be low and noncatastrophic. The ERPC is applied to an image coding example based on subband coding and vector quantization. It results in an efficient adaptive codec capable of operating in harsh channel conditions, without the aid of error correction or detection techniques     

Clock hierarchies: an abstraction for grouping and controllingmedia streams

Synchronization plays an important role in multimedia systems at various levels of abstraction. We propose a set of powerful abstractions for controlling and synchronizing continuous media streams in distributed environments. The proposed abstractions are based on a very general computation model, that allows media streams to be processed (i.e. produced, consumed or transformed) by arbitrarily structured networks of linked components. Further, compound components can be composed of existing ones to provide higher levels of abstractions. The clock abstraction is provided to control individual media streams, i.e., streams can be started, paused or scaled by issuing the appropriate clock operations. Clock hierarchies are used hierarchically group related streams, where each clock in the hierarchy identities and controls a certain group, or subgroup of streams. Control and synchronization requirements can be expressed in a uniform manner by associating group members with control or synchronisation attributes. An important property of the concept of clock hierarchy is that it can be combined in a natural way with component nesting     

Auxiliary differential equation formulation: an efficient implementation of the perfectly matched layer

An efficient algorithm for implementing the perfectly matched layer (PML) is presented for truncating finite-difference time-domain domains. The algorithm is based on incorporating the auxiliary differential equation method into the PML formulations. Simple, unsplit-field and material independent PML formulations are obtained. Two dimensional numerical examples are included to validate the proposed formulations.     

Design and implementation of a scalable switch architecture for efficient high‐speed data multicasting

This paper presents the design and implementation of a new scalable cell‐based multicast switch fabric for broadband communications. Using distributed control and modular design, the multicast balanced gamma switch features a scalable, high performance architecture for unicast, multicast and combined traffic under both uniform and non‐uniform traffic conditions. The important design characteristic of the switch is that a distributed cell replication function for multicast cells is integrated into the functionality of the switch element with the self‐routing and contention resolution functions. Thus, no dedicated copy network is required. In the paper, we discuss in detail the design issues associated with the multicast functionality of the switch using 0.18 µm CMOS technology and discuss the scalability of the switch in terms of architectural, implementation, and performance scalability. Synthesized results are provided for measures of circuit complexity and timing. Copyright © 2006 John Wiley & Sons, Ltd.     

EPMDA: an efficient privacy-preserving multi-dimensional data aggregation scheme for edge computing-based IoT system

In order to perform multi-dimensional data aggregation operations efficiently in edge computing-based Internet of things (IoT) systems, a new efficient privacy-preserving multi-dimensional data aggregation (EPMDA) scheme is proposed in this paper. EPMDA scheme is characterized by employing the homomorphic Paillier encryption and SM9 signature algorithm. To improve the computation efficiency of the Paillier encryption operation, EPMDA scheme generates a pre-computed modular exponentiation table of each dimensional data,and the Paillier encryption operation can be implemented by using only several modular multiplications. For the multi-dimensional data, the scheme concatenates zeros between two adjacent dimensional data to avoid data overflow in the sum operation of ciphertexts. To enhance security, EPMDA scheme sets random number at the high address of the exponent. Moreover, the scheme utilizes SM9 signature scheme to guarantee device authentication and data integrity. The performance evaluation and comparison show that EPMDA scheme is more efficient than the existing multi-dimensional data aggregation schemes.     

Target software generation: an approach for automatic mapping of SystemC specifications onto real-time operating systems

In this paper we present a new approach for automated target code generation for given real-time operating systems out of SystemC to support platform independent software development. Since SystemC becomes the most important language in electronic system level design, the support of a seamless design flow becomes an important task. During the system design process, SystemC is used to develop a “Golden Reference Model” that provides a well-suited platform for specification, simulation, and verification of embedded systems. Based on the “Golden Reference Model,” an important task of the design process is to map applications, that have been described either in C++ or directly in SystemC, to the specific real-time operating system which is running at the target processor. Since a manual mapping approach is time-consuming and error-prone, the mapping process should be performed automatically. This paper presents a new method for automated generation of code for a specified operating system just by using an abstract XML representation of the RTOS API.