人机结合改善标准单元芯片设计

介绍了一种专用译码电路的芯片设计。该电路采用正向设计方法，共设计主要表现为两个方面；逻辑电路设计和版图设计。简单介绍了电路的逻辑设计；详细描述了采用人机结合的方式，在自动布局布线系统设计的基础上进行人工干预的版图设计方法。     

结盟众力引领SOC时代的到来——SOC芯片设计解决方案研讨会

随着科技的进步,人们生活水平的日益提高,电子信息产品成为连接人们与现代化的必需品。这样就对集成电路设计提出更高要求,功能的多样性,设计的繁杂性,工艺的集成度等。如今,SOC技术已成为21世纪集成电路设计的主流,成为当今超大规模集成电路的发展趋势,在为半导体产业发展带来前所未有的广阔市场和难得的发展机遇的同时,也迎来了更多挑战。SOC系统将原来由许多芯片完成的功能集中到一块芯片中完成。但SOC不是各个芯片功能的简单叠加,而是从整个系统的功能和性能出发,用软硬结合的设计和验证方法,利用IP复用及深亚微米技术,在一个芯片…     

深亚微米芯片设计中相位噪声的讨论

文章以相位噪声（Jitter)为核心讨论芯片设计领域深亚微米效应理论，文章在介绍相位噪声的定义，定量描述，来源以及前人的研究工作耻，提出了建立相位噪声的软件仿真环境及给出相应判据的解决思路，以期指导高速发展的超大规模集成电路设计技术的提升。     

基于ASIC实现蓝牙基带芯片的后端设计

从ASIC设计的原理、流程入手，以蓝牙基带芯片的后端设计为例，介绍用自动布局布线工具实现半定制专用集成电路(ASIC)设计。通过版图规划(F1oorplan)、布局(Place)、布线(Route)、静态分析和优化等过程，讨论了后端设计过程中可能遇到的问题及解决方法。     

深亚微米下系统级芯片的物理设计实例

深亚微米下芯片的物理设计面临很多挑战,特别是对于超大规模的SOC,比如互连延迟(Interconnect delay)、信号完整性(SI)、电压降(IR-Drop)与电迁移(EM)、第三方IP集成,等等.应对这些问题,在后端设计流程上要有新的方法.文章以一块0.18 μm工艺下200万门无线数据传输芯片的物理设计为例,介绍了其中的关键设计步骤和一些解决问题的方案,可为其他类似的设计提供参考.     

片上系统芯片设计与静态时序分析

提出了一种考虑了布线延迟的片上系统设计流程,并运用一个新的、全芯片的、门级静态时序分析工具支持片上系统设计。实例设计表明,该设计方法能使设计者得到更能反映实际版图的延迟值,验证结果更完整、准确,从而大大加快芯片设计的周期。     

0. 6 􀀁m CMOS 雷达天线专用控制芯片设计

雷达系统中天线控制电路完成上位机的初始化和扫描角度控制,要求具有高可靠性和低静态电流,用专用集成电路进行设计具有明显优势.采用Verilog HDL语言描述了系统的逻辑功能,超前进位结构的加/减法器提高了电路的工作速度.利用0.6 μm CMOS工艺完成了天线控制电路的物理实现,芯片面积为1.695 mm×1.631 mm.     

8-VSB发射机的设计与实现

一、概要 韩国广播系统（KBS）研究所设计并实现了符合ATSC的8VSB发射机，ATSC用作我们地球上未来的数字传输标准。该发射机由8VSB激励器和RF级构成。8SVB激励器使用FPGA和DSP芯片进行设计，这些芯片集成到升频器和1KW RF放大器的RF级之中。     

用Topswitch芯片设计的反激式开关电源

Topswitch系列芯片是Power Integration公司生产的开关电源专用集成电路。它将脉宽调制电路(PWM)与高压MOSFET开关管及驱动电路等集成在一起。使用该芯片设计的小功率开关电源。可大大减少外同电路，降低成本，提高可靠性。本文介绍了Topswitch系列芯片的工作原理及用该芯片制作的30W反激式开关电源，并就电路设计中的关键问题做了详解。     

低功耗便携式数字音频广播收音机中AAC LC解码器的设计优化

针对目前数字音频广播(DAB)收音机中DSP软件AAC+解码器功耗大的问题,该文提出了低功耗AAC LC解码器的ASIC设计,以极低的硬件代价完成了最基本的DAB+节目解码,加入DAB解码芯片后巧妙地实现了DAB+和DAB两种不同标准的兼容。该文设计优化了反量化与IMDCT算法,使用了分时工作法,从而实现了低功耗。该设计的系统时钟为16.384 MHz,采用0.18 m CMOS工艺,功耗约为6.5 mW,并与DAB信道解码结合,通过了FPGA开发板上的实时验证,且完成了芯片的版图设计,芯片面积为14 mm2。     

一种有效地综合两种分级设计方法的BBL布局算法

本文提出了一个新的Building Blook(积木块)布局算法。在布局中采用多目标形状的方法,将自底向上(bottom-up)及自顶向下(too-down)两种分级设计方法有效的结合起来,从而综合这两种设计方法的优点,得到令人满意的布局结果。本布局算法已在UNIX操作系统支持下的SUN、VAX-785、HP、GPX上用C语言实现,实验结果表明本布局法优于BEAR系统的布局算法。本布局系统是正在开发的国家 IC CAD三级系统(PANDA系统)的一个子系统。     

一种MP3/AAC解码器ASIC的设计与实现

介绍了MPEG-1 Layer3(简称MP3)和AAC的音频解码器在ASIC上的VLSI实现，部分解码使用了软件来实现。整个ASIC利用USB传输，并为MP3和AAC解码设计了专用的DSP结构。实现的算法中，根据硬件的特点做了很多有效的优化，并用Verilog语言编写。使用中芯国际公司(SMIC)提供的0．18μm工艺库进行了仿真和综合。     

SOC设计:IC产业链设计史上的重大革命

集成电路芯片设计是IC产业链的龙头,而系统芯片(SOC)集中了芯片设计的先进技术。本文论述了SOC芯片的最新设计技术和焦点技术,包括嵌入式CPU,IP模块设计以及芯片的验证和测试等,展望了当前SOC芯片设计的发展趋势。     

智能测量集成电路的设计与仿真

文章以电子体重秤专用集成电路为例,介绍了基于嵌入式MPU的智能测量专用集成电路的设计及硬件仿真。在一块芯片内实现了数据采集、数据处理、数据显示等智能测量系统所需完成的功能,并在所设计的硬件仿真系统中,通过硬件仿真,验证了系统功能的正确性,为目标芯片提供了软件开发平台。并且该设计具有较强的通用性,可用于多种智能测量场合。     

基于IP核的8位微控制器设计

设计能力和工艺集成能力之间差距的不断扩大阻碍了片上系统的有效开发,为此必须提高设计人员的设计能力,降低产品开发周期和成本.利用IP参数化技术,把设计重用方法应用于8位微控制器设计,提出了基于IP核重用的8位微控制器设计方法,重用开发人力消耗节约70%,显著提高了设计效率,并通过实际微控制器系列设计实例阐述了该设计方法的实施和IP核复用策略.     

A System Design Methodology for Analog Feed Forward Artificial Neural Networks

Today Feed Forward Neural Networks (FFNs) use paradigms tied to mathematical frameworks more than to actual electronic devices. This fact makes analog neural integrated circuits heavy to design. Here we propose an alternative model that can use the native computational properties of the basic electronic circuits. A practical framework is described to train analog FFNs in compliance with the model. This is especially useful whenever the weight storage elements cannot be re-programmed on the fly at a high rate. To show how the capability of such framework can be applied to neural systems with non conventional architectures two cases are presented. The first one is a neural signal processor named NESP which has sigmoidal neurons and the other is an innovative architecture named N-LESS.     

FPCS——一种适用于积木块方式的布局及平面规划系统

本文简述了一种分级式的自下而上结群和自上而下分划定位相结合的全定制方式的积木块(building block)布局及平面规划(floorplanning)系统.本方法基于积木块的尺寸、形状、连接状况、引线位置以及芯片引线端等的要求逐级优化组合若干种积木块组,并且根据工艺条件进行了布线区面积估计,以便得到较好的布局结果.如果积木块的尺寸或其长宽比可以改变,则本系统可改变其尺寸及形状从而优化布局结果.由于采用了多种有效的实用方法,并把它们有机地统一在系统中,因此使布局能在基本满足用户要求的条件下,做到和布线结果基本匹配.实验结果表明,这种方法是令人满意的.     

A Novel Design Methodology for High-Performance Programmable Decoder Cores for AA-LDPC Codes

A new parameterized-core-based design methodology targeted for programmable decoders for low-density parity-check (LDPC) codes is proposed. The methodology solves the two major drawbacks of excessive memory overhead and complex on-chip interconnect typical of existing decoder implementations which limit the scalability, degrade the error-correction capability, and restrict the domain of application of LDPC codes. Diverse memory and interconnect optimizations are performed at the code-design, decoding algorithm, decoder architecture, and physical layout levels, with the following features: (1) Architecture-aware (AA)-LDPC code design with embedded structural features that significantly reduce interconnect complexity, (2) faster and memory-efficient turbo-decoding algorithm for LDPC codes, (3) programmable architecture having distributed memory, parallel message processing units, and dynamic/scalable transport networks for routing messages, and (4) a parameterized macro-cell layout library implementing the main components of the architecture with scaling parameters that enable low-level transistor sizing and power-rail scaling for power-delay-area optimization. A 14.3 mm² programmable decoder core for a rate-1/2, length 2048 AA-LDPC code generated using the proposed methodology is presented, which delivers a throughput of 6.4 Gbps at 125 MHz and consumes 787 mW of power.Mohammad M. Mansour received his B.E. degree with distinction in 1996 and his M.S. degree in 1998 all in Computer and Communications Engineering from the American University of Beirut (AUB). In August 2002, he received his M.S. degree in Mathematics from the University of Illinois at Urbana-Champaign (UIUC). Mohammad received his Ph.D. in Electrical Engineering in May 2003 from UIUC. He is currently an Assistant Professor of Electrical Engineering with the ECE department at AUB. From 1998 to 2003, he was a research assistant at the Coordinated Science Laboratory (CSL) at UIUC. In 1997 he was a research assistant at the ECE department at AUB, and in 1996 he was a teaching assistant at the same department. From 1992–1996 he was on the Deans honor list at AUB. He received the Harriri Foundation award twice in 1996 and 1998, the Charli S. Korban award twice in 1996 and 1998, the Makhzoumi Foundation Award in 1998, and the PHI Kappa PHI Honor Society awards in 2000 and 2001. During the summer of 2000, he worked at National Semiconductor Corp., San Francisco, CA, with the wireless research group. His research interests are VLSI architectures and integrated circuit (IC) design for communications and coding theory applications, digital signal processing systems and general purpose computing systems.Naresh R. Shanbhag received the B.Tech from the Indian Institute of Technology, New Delhi, India, in 1988, M.S. from Wright State University and Ph.D. degree from the University of Minnesota, in 1993, all in Electrical Engineering. From July 1993 to August 1995, he worked at AT&T Bell Laboratories at Murray Hill in the Wide-Area Networks Group, where he was responsible of development of VLSI algorithms, architectures and implementation for high-speed data communications applications. In particular, he was the lead chip architect for AT&Ts 51.84 Mb/s transceiver chips over twisted-pair wiring for Asynchronous Transfer Mode (ATM)-LAN and broadband access. Since August 1995, he is with the Department of Electrical and Computer Engineering, and the Coordinated Science Laboratory where he is presently an Associate Professor and Director of the Illinois Center for Integrated Microsystems. At University of Illinois, he founded the VLSI Information Processing Systems (ViPS) Group, whose charter is to explore issues related to low-power, high-performance, and reliable integrated circuit implementations of broadband communications and digital signal processing systems. He has published numerous journal articles/book chapters/conference publications in this area and holds three US patents. He is also a co-author of the research monograph Pipelined Adaptive Digital Filters (Norwell, MA: Kluwer, 1994). Dr. Shanbhag received the 2001 IEEE Transactions Best Paper Award, 1999 Xerox Faculty Research Award, 1999 IEEE Leon K. Kirchmayer Best Paper Award, the 1997 Distinguished Lecturer of IEEE Circuit and Systems Society (97–99), the National Science Foundation CAREER Award in 1996, and the 1994 Darlington Best Paper Award from the IEEE Circuits and Systems society. From 1997–99 and 2000–2002, he served as an Associate Editor for IEEE Transaction on Circuits and Systems: Part II and an Associate Editor for the IEEE Transactions on VLSI, respectively. He was the technical program chair for the 2002 IEEE Workshop on Signal Processing Systems (SiPS02).