Modeling for floating body effects in fully depleted SOI MOSFETs

A model based on SOI MOSFET and BJT device theories is developed to describe the current kink and breakdown phenomena in thin-film SOI MOSFET drain-source current-voltage characteristics operated in strong inversion. The modulation of MOSFET current by raised floating body potential is discussed to provide an insight for understanding the suppression of current kink in fully depleted thin-film SOI devices. The proposed analytical model successfully simulates the drain current-voltage characteristics of thin-film SOI n-MOSFETs fabricated on SIMOX wafers     

Temperature influence on the gate-induced floating body effect parameters in fully depleted SOI nMOSFETs

The temperature influence on the gate-induced floating body effect (GIFBE) in fully depleted (FD) silicon-on-insulator (SOI) nMOSFETs is investigated, based on experimental results and two-dimensional numerical simulations. The GIFBE behavior will be evaluated taking into account the impact of carrier recombination and of the effective electric field mobility degradation on the second peak in the transconductance (gm). This floating body effect is also analyzed as a function of temperature. It is shown that the variation of the studied parameters with temperature results in a “C” shape of the threshold voltage corresponding with the second peak in the gm curve.     

Body-contacted SOI MOSFET structure with fully bulk CMOS compatiblelayout and process

A new SOI MOSFET structure to reduce the floating body effect is proposed and successfully demonstrated. The key idea of the proposed structure is that the field oxide does not consume the silicon film completely, so that the well contact can suppress the body potential increase in SOI MOSFET through the remaining silicon film between the field oxide and buried oxide. The measured results show the suppressed floating body effect as expected. This new structure retains most of the advantages in the propagation delay of the conventional SOI MOSFET without body potential instability. An additional advantage of the proposed structure is that the layout and process are the same as those of bulk CMOS     

Short-channel effect in fully depleted SOI MOSFETs

The short-channel effect in fully depleted silicon-on-insulator MOSFETs has been studied by a two-dimensional analytical model and by computer simulation. The calculated values agree well with the simulation results. It is found that the vertical field through the depleted film strongly influences the lateral field across the source and drain regions. The short-channel effect can be significantly reduced by decreasing the silicon film thickness     

Subthreshold kinks in fully depleted SOI MOSFET's

Measured current-voltage characteristics of scaled, floating-body, fully depleted (FD) SOI MOSFET's that show subthreshold kinks controlled by the back-gate (substrate) bias are presented. The underlying physical mechanism is described, and is distinguished from the well known kink effect in partially depleted devices. The physical insight attained qualifies the meaning of FD/SOI and implies new design issues for low-voltage FD/SOI CMOS     

Low frequency noise in fully depleted SOI PMOSFET's

Low frequency noise of fully depleted PMOSFET's on SOI substrates with various channel dopings was measured as a function of substrate-to-source bias. It was found that the device noise is a strong function of the substrate-to-source bias and a window exists in which the device noise is at its minimum. The position of the minimum noise region depends on the channel doping, and its width depends on the buried oxide thickness. Knowledge of the bias conditions under which the transistor will operate are necessary for proper selection of the channel doping for low noise PMOSFET design     

Analysis of conduction in fully depleted SOI MOSFETs

The conduction characteristics of fully depleted SOI MOSFETs studied by theoretical analysis and computer simulation are discussed. In these devices the ideal inverse subthreshold slope of 59.6 mV/decade is obtained if the interface-state capacitances are much smaller than the gate-oxide and silicon-film capacitances. For above-threshold conduction, with decreasing silicon film thickness the inversion charges penetrate more deeply into the film and the transconductance increases because of the decreasing fraction of surface conduction     

Hot-carrier effects in thin-film fully depleted SOI MOSFET's

Previous conflicting reports concerning fully depleted SOI device hot electron reliability may result from overestimation of channel electric field (E_m). Experimental results using SOI MOSFET's with body contacts indicate that E_m is just a weak function of thin-film SOI thickness (T_si and that E_m can be significantly lower than in a bulk device with drain junction depth (X _j) comparable to SOI's T_si. The theoretical correlation between SOI MOSFET's gate current and substrate current are experimentally confirmed. This provides a means (I_G) of studying E_m in SOI device without body contacts. Thin-film SOI MOSFET's have better prospects for meeting breakdown voltage and hot-electron reliability requirements than previously thought     

A snapback-free and high-speed SOI LIGBT with double trenches and embedded fully NPN structure

A novel 600 V snapback-free high-speed silicon-on-insulator lateral insulated gate bipolar transistor is proposed and investigated by simulation. The proposed device features an embedded NPN structure at the anode side, and double trenches together with an N-type carrier storage (N-CS) layer at the cathode side, named DT-NPN LIGBT. The NPN structure not only acts as an electron barrier to eliminate the snapback effect in the on-state within a smaller cell pitch but also provides an extra electron extracting path during the turn-off stage to decrease the turnoff loss (E_off). The double cathode trenches and N-CS layer hinder the hole from being extracted by the cathode quickly. They then enhance carrier storing effect and lead to a reduced on-state voltage drop (V_on). The latch-up immunity is improved by the double cathode trenches. Hence, the DT-NPN LIGBT obtains a superior tradeoff between the V_on and E_off. Additionally, the DT-NPN LIGBT exhibits an improved blocking capability and weak dependence of breakdown voltage (BV) on the P⁺ anode doping concentration because the NPN structure suppresses triggering the PNP transistor. The proposed LIGBT reduces the E_off by 55% at the same V_on, and improves the BV by 7.3% compared to the conventional LIGBT.     

Reduction of floating substrate effect in thin-film SOI MOSFETs

The presence of a floating substrate in SOI transistors gives rise to a decrease of threshold voltage when drain voltage is increased. When the devices are made in a very thin silicon film, the latter is completely depleted when the device is in the 'on' state, and no part of the film can act as a floating substrate. This brings about a dramatic decrease of the so-called 'kink effect'.     

一种针对具有时间结构的源信号盲源提取算法

从数量繁多的混合信号中提取出具有时间结构的感兴趣源信号是当今信号处理领域的一个研究热点。然而,传统的盲提取算法在提取精度和算法鲁棒性上都存在欠缺。文中针对上述问题提出一种基于非高斯性和时间结构的盲源提取算法,利用固定点学习算法提取出源信号并分析算法的稳定性,仿真结果证实了算法的有效性和先进性。     

Carrier lifetime extraction in fully depleted dual-gate SOI devices

A new method for extracting the carrier recombination lifetime in dual-gate silicon-on-insulator (SOI) structures is proposed. The experiment, model, and numerical simulations indicate that an excess forward current is obtained when carrier recombination occurs in the whole film volume     

Electron mobility in the inversion layers of fully depleted SOI films

The dependences of the electron mobility μ_eff in the inversion layers of fully depleted double–gate silicon-on-insulator (SOI) metal–oxide–semiconductor (MOS) transistors on the density N _e of induced charge carriers and temperature T are investigated at different states of the SOI film (inversion–accumulation) from the side of one of the gates. It is shown that at a high density of induced charge carriers of N _e > 6 × 10¹² cm^–2 the μeff(T) dependences allow the components of mobility μ_eff that are related to scattering at surface phonons and from the film/insulator surface roughness to be distinguished. The μ_eff(N _e ) dependences can be approximated by the power functions μ_eff(N _e) ∝ N _e ^?n . The exponents n in the dependences and the dominant mechanisms of scattering of electrons induced near the interface between the SOI film and buried oxide are determined for different N _e ranges and film states from the surface side.     

Investigation of the novel attributes of a fully depleted dual-material gate SOI MOSFET

The novel features of a fully depleted (FD) dual-material gate (DMG) silicon-on-insulator (SOI) MOSFET are explored theoretically and compared with those of a compatible SOI MOSFET. The two-dimensional numerical simulation studies demonstrate the novel features as threshold voltage roll-up and simultaneous transconductance enhancement and suppression of short-channel effects offered by the FD DMG SOI MOSFET. Moreover, these unique features can be controlled by engineering the workfunction and length of the gate material. This work illustrates the benefits of high-performance FD DMG SOI MOS devices over their single material gate counterparts and provides an incentive for further experimental exploration.     

High-temperature and self-heating effects in fully depleted SOI MOSFETs

In this paper, the high-temperature and self-heating effects in the fully depleted enhancement lightly doped SOI n-MOSFETs are investigated over a wide range of temperatures from 300 to 600 °K by using the SILVACO¹ TCAD tools. In particular, we have studied their current-voltage characteristics (I_D-V_GS and I_D-V_DS), threshold voltages and propagation delays. Simulation results show that there exists a biasing point where the drain current and the transconductance are temperature independent. Such a point is known as the zero temperature coefficient (ZTC) bias point. The drain current ZTC bias points are identified in both the linear and saturation regions whereas the transconductance ZTC bias point exists only in the saturation region. We have observed that decreasing the film thickness could reduce the threshold voltage sensitivity of the SOI MOSFET with temperature and that the drain current decreases with increasing temperature. We have also noted that due to the self-heating effects, the drain current decreases with increasing drain bias exhibiting a negative conductance and that the self-heating effects reduced at a higher operating temperature. Self-heating effects are more pronounced for higher gate biases and thinner silicon films whereas the bulk device shows negligible self-heating effects.     

Scaling rules for SOI MOSFETs operating in the fully inverted mode

Two-dimensional device simulation was performed on silicon-on-insulator (SOI) metal-oxide-semiconductor field-effect-transistors (MOSFETs) with various gate length L_g various top Si layer thickness t_Si and various buried oxide (BOX) layer thickness t_BOX. As a result, it was found that when t_BOX is large, short channel effect (SCE) cannot be suppressed in a fully depleted (FD) MOSFET only by the simple scaling rule maintaining the ratio of L_g to top Si layer t_Si more than four. It was also found that the scaling rule breaks down more seriously in a fully inverted (FI) MOSFET. It was confirmed that electric field from the drain region penetrates easily into thick BOX layer, which causes drain-induced barrier lowering (DIBL) at the top Si/BOX interface in deep sub-micron gates SOI MOSFETs. Consequently, it was concluded that the DIBL can be suppressed efficiently by reducing t_BOX even in a FI MOSFET.     

A silicon/indium arsenide source structure to suppress the parasitic bipolar-induced breakdown effect in SOI MOSFETs

We introduce Silicon/indium arsenide (Si/InAs) source submicron-device structure in order to minimize the impact of floating body effect on both the drain breakdown voltage and single transistor latch in ultra thin SOI MOSFETs. The potential barrier of valence band between source and body reduces by applying the Indium Arsenide (InAs) layer at the source region. Therefore, we can improve the drain breakdown by suppressing the parasitic NPN bipolar device and the hole accumulation in the body. As confirmed by 2D simulation results, the proposed structure provides the excellent performance compared with a conventional SOI MOSFET thus improving the reliability of this structure in VLSI applications.     

AC floating body effects and the resultant analog circuit issues insubmicron floating body and body-grounded SOI MOSFET's

We report the extensive study on ac floating body effects of different SOI MOSFET technologies. Besides the severe kink and resultant noise overshoot and degraded-distortion in partially depleted (PD) floating body SOI MOSFET's, we have investigated the residue ac floating body effects in fully depleted (FD) floating body SOI MOSFET's, and the different body contacts on PD SOI technologies. It is important to note that there is a universal correlation between ac kink effect and Lorentzian-like noise overshoot regardless of whether the body is floating or grounded. In addition, it was found that third-order harmonic distortion is very sensitive to floating body induced kink or deviation on output conductance due to the finite voltage drop of body resistance. These results provide device design guidelines for SOI MOSFET technologies to achieve comparable low-frequency noise and linearity with Bulk MOSFET's     

具有部分界面等电势浮空埋层的高压SOI PLDMOS

A novel silicon-on-insulator（SOI） high-voltage pLDMOS is presented with a partial interface equipotential floating buried layer（FBL） and its analytical model is analyzed in this paper.The surface heavily doped p-top layers,interface floating buried N⁺/P⁺ layers,and three-step field plates are designed carefully in the FBL SOI pLDMOS to optimize the electric field distribution of the drift region and reduce the specific resistance.On the condition of ESIMOX（epoxy separated by implanted oxygen）,it has been shown that the breakdown voltage of the FBL SOI pLDMOS is increased from—232 V of the conventional SOI to—425 V and the specific resistance R_on,sp is reduced from 0.88 to 0.2424Ω·cm².     

Design of a 128-mb SOI DRAM using the floating body cell (FBC)

A 128-Mb SOI DRAM has been developed featuring the floating body cell (FBC). To keep the cell data state from being degraded by the word-line (WL) disturb due to the charge pumping and to reduce the refresh busy rate, a sense amplifier (S/A) is arranged for every bit-line (BL) and replenishes data "1" cells' bodies with holes which are lost by the disturb in every read and write cycle. The power is reduced by operating the S/As asymmetrically between the selected and the unselected thanks to that the number of holes to be replenished in the unselected S/As for charge pumping is two order of magnitude smaller than that required for writing the data "1". The multi-pair averaging of dummy cells generates a very accurate reference current for distinguishing the data "1" and "0" and a Monte Carlo simulation shows that it achieves a sensing scheme robust enough to realize all good parts of the DRAM with a reasonable amount of redundancy. The cell's feature of quasi-nondestructive read-out is also advantageous for making an SRAM interface of the DRAM or hiding refresh from uses without sacrificing the access time.