基于切比雪夫-迹迭代的大规模MIMO系统软输出信号检测

在多用户大规模多输入多输出(MIMO)系统信号检测算法中,最小均方误差(MMSE)算法可取得近似最优性能,但MMSE算法中高维矩阵求逆的复杂度过高,导致在实际应用中难以快速有效地实现.同时,对于高阶正交幅度调制(HQAM),如果符号向比特的解映射采用硬判决,将会导致后续信道译码的性能明显下降.因此,该文针对采用格雷编码...     

大规模MIMO系统低复杂度混合迭代信号检测

在大规模MIMO系统上行链路信号检测算法中,最小均方误差(MMSE)算法能获得接近最优的线性检测性能.但是,传统的MMSE检测算法涉及高维矩阵求逆运算,由于复杂度过高而使其在实际应用中难以快速有效地实现.基于最速下降(steepest descent,SD)算法和高斯一赛德尔(Gauss-Seidel,GS)迭代的方法提出了一种低复杂度的混合迭代算法,利用SD算法为复杂度相对较低的GS迭代算法提供有效的搜索方向,以加快算法收敛的速度.同时,给出了一种用于信道译码的比特似然比(LLR)近似计算方法.仿真结果表明,通过几次迭代,给出的算法能够快速收敛并接近MMSE检测性能,并将算法复杂度降低一个数量级,保持在O(K2).     

基于LDPC编码的MIM0系统迭代接收机研究

研究了基于LDPC编码无线MIMO通信系统中的软输出最小均方误差干扰抵消迭代(MMSE PIC)检测算法.针对初次迭代检测时PIC输出的后验比特对数似然比(LLR)不可靠的问题,利用MMSE滤波器输出的高斯近似表示,给出了基于后验概率估计的迭代干扰抵消检测算法,以提高检测器输出的编码比特对数似然比的可靠性.仿真结果表明...     

A Low-power and Low-complexity Baseband Processor for MIMO-OFDM WLAN Systems

This paper presents an energy-efficient design and the implementation results of a high speed two transmitter—two receiver multi-input multi-output orthogonal frequency division multiplexing (MIMO-OFDM) wireless LAN baseband processor. The proposed processor includes a bit-parallel processing physical layer convergence procedure (PLCP) processor which lowers system clock frequency. A cost-efficient MIMO spatial multiplexing (SM) symbol detector is also proposed in a physical medium dependent (PMD) processor. The proposed symbol detection algorithm is based on a sorted QR decomposition (SQRD) scheme followed by a maximum-likelihood (ML) test. The proposed algorithm shows enhanced performance compared to the conventional algorithms such as SQRD and ordered successive interference cancellation (OSIC) algorithms. The proposed baseband processor supports a maximum data rate of 130 Mbps at a 40 MHz operation frequency. The power consumptions of the PLCP processor are 27 mW and 93 mW for TX and RX modes, respectively, which are reduced by 70% compared with that of a common bit-serial architecture. The complexity of the symbol detector in the PMD processor is reduced by 18% compared with that of the conventional hardware architecture.     

Improving energy efficiency using a link adaptation algorithm dedicated for 100 Gbps wireless communication

This paper presents a link adaptation algorithm dedicated for 100 Gbps wireless transmission. Interleaved Reed-Solomon codes are selected as forward error correction (FEC) algorithms. The redundancy of the codes is selected according to the channel bit error rate (BER). The uncomplicated FEC scheme allows implementing a complete data link layer processor in an FPGA (field programmable gate array). In our case, we use the Virtex7 FPGA to validate the functionality of our implementation. The proposed FPGA-processor achieves 169 Gbps throughput. Moreover, the implementation is synthesized into 40 nm CMOS technology and the described link adaptation algorithm allows reducing consumed energy per bit to values below 1 pJ/bit at BER <1e−4. With higher BER, the energy increases up to ∼13 pJ/bit.     

LTE系统中turbo接收机的设计

LTE系统采用了OFDM、MIMO等关键技术。传统的V-BLAST、QR算法在进行信号检测时,需要进行硬判决,造成了性能的下降。为此,本文提出了应用于LTE系统的turbo接收机,对其每个组成模块进行详细描述。由于在信号检测时以软信息的方式进行处理,避免了信息的损失。仿真结果表明,该turbo接收机能够极大地降低误比特率,提升性能。     

Exploration of Soft-Output MIMO Detector Implementations on Massive Parallel Processors

Emerging Software Defined Radio (SDR) baseband platforms are based on multiple processors with massive parallelism. Although the computational power of these platforms would theoretically enable SDR solutions with advanced wireless signal processing, existing work implements still rather basic algorithms. For instance, current Multiple-Input Multiple-Output (MIMO) detector implementations are typically based on simple linear hard-output and not on advanced near-Maximum Likelihood (ML) soft-output detection. However, only the latter enables to exploit the full potential of MIMO technology. In this work, we explore the feasibility of advanced soft-output near-ML MIMO detectors on massive parallel processors. Although such detectors are considered to be very challenging due to their high computational complexity, we combine architecture-friendly algorithm design, application specific instructions and instruction-level/data-level parallelism explorations to make SDR solutions feasible. We show that, by applying the proposed combination of techniques, it is possible to obtain SDR implementations which can deliver data rates that are sufficient for future wireless systems. For example, a 2 × 4 Coarse Grain Array (CGA) processor with 16-way Single Instruction Multiple Data (SIMD) can deliver 192/368 Mbps throughput for 2 × 2 64/16-QAM transmissions. Finally, we estimate the area and power consumption of the programmable solution and compare it against a traditional Application Specific Integrated Circuit (ASIC) approach. This enables us to draw conclusions from the cost perspective.     

A New Signal Detection Method for Spatially Multiplexed MIMO Systems and Its VLSI Implementation

This brief proposes a new signal detection method called QR ordered successive interference cancellation (OSIC) with candidates (QOC) method for spatially multiplexed multiple-input–multiple-output (MIMO) systems. By using the OSIC algorithm and the maximum-likelihood (ML) metric, the proposed method achieves near-ML performance without requiring a large number of candidates. Although the proposed method can be used for both hard and soft decoding systems, it is particularly useful for soft decoding systems since the log-likelihood-ratio (LLR) values for all the bits can efficiently be computed without using LLR estimation. The proposed method is also suitable for very large scale integration (VLSI) implementation since it leads to a fixed throughput system. A QOC detector for a $4 times 4$ 16-quadrature-amplitude-modulation (16-QAM) MIMO system has been designed and synthesized with a 0.13-$muhbox{m}$ complimentary metal–oxide–semiconductor (CMOS) technology. The implementation results show that the proposed detector reduces the hardware complexity by 73% relative to a K-best detector.      

Symbol detection in spatial multiplexing system using particle swarm optimization meta-heuristics

Symbol detection in multi-input multi-output (MIMO) communication systems using different particle swarm optimization (PSO) algorithms is presented. This approach is particularly attractive as particle swarm intelligence is well suited for real-time applications, where low complexity and fast convergence is of absolute importance. While an optimal maximum likelihood (ML) detection using an exhaustive search method is prohibitively complex, PSO-assisted MIMO detection algorithms give near-optimal bit error rate (BER) performance with a significant reduction in ML complexity. The simulation results show that the proposed detectors give an acceptable BER performance and computational complexity trade-off in comparison with ML detection. These detection techniques show promising results for MIMO systems using high-order modulation schemes and more transmitting antennas where conventional ML detector becomes computationally non-practical to use. Hence, the proposed detectors are best suited for high-speed multi-antenna wireless communication systems. Copyright © 2008 John Wiley & Sons, Ltd.     

一种基于LLR软判决的LTE解映射简化算法

针对目前LTE解映射算法复杂度高的缺陷,提出了一种基于LLR软判决的LTE解映射简化算法SLLR。该算法旨在通过使用对数似然比进行软判决,以简化指数计算与对数计算为主,降低LTE解映射过程中计算的复杂度。通过对标准算法与简化算法的QAM调制方式产生的误码率、误块率进行仿真和比较,结果表明该SLLR简化算法性能良好,适用于LTE通信系统。     

基于软输出固定复杂度球形译码的高效迭代检测算法

该文在软输出固定复杂度球形译码(SFSD)算法的基础上,提出一种低复杂度高性能的MIMO迭代检测方法。该算法利用迭代过程中译码器的反馈信息更新SFSD检测算法的软输出,获得明显的迭代增益,并利用多级比特映射星座图的特点大大降低分支度量的运算次数。针对SFSD算法预处理复杂度较高的问题,该文将检测顺序调整和QR分解两个预处理步骤相结合,从而减少了矩阵求逆运算。在长期演进方案(LTE)下行链路环境中的仿真结果表明,该文提出的算法性能十分接近最优的最大后验概率(MAP)检测,并且实现复杂度相对于MAP有显著的下降。     

Base on the Public Scientific Quality Improvement Research on Risk Early Warning of Online Shopping

LTE-A network offers data rates up to 1 Gbps which is 10?×?faster than LTE catering to growing demand of users. LTE improves user experience by reducing latency and increasing bandwidth efficiency. The emerging services and key enhancements such as Further Enhancement of Downlink Multiple-Input Multiple-Output (MIMO), Heterogeneous Networks, and Carrier Aggregation (CA) in LTE-A has improved performance of LTE-A networks. Scheduling optimization still remains one of the biggest challenges in high speed data transmission network. Scheduling in LTE-A networks are performed at various levels; User Equipment (UE), Serving Gateway (SGW), Air Interface and eNodeB. Remote Radio Head (RRH) is an extremely specialized device installed at antenna of eNodeB for optical to electrical signal conversion, amplification of signals and Uplink and Downlink Scheduling. Resource scheduling at Antenna of eNodeB module is constituted as a significant research optimization area. This paper proposes a soft computing based scheduler for RRH. Results of proposed technique are evaluated on Fairness Index, Throughput, Spectral Efficiency and Rank Indicator Distribution. The proposed algorithm aims to improve performance of scheduling. From experimental results, it is observed that proposed model succeeds to achieve significantly better performance as compared to state-of-art algorithms.

     

Implementation of a High Throughput Soft MIMO Detector on GPU

Multiple-input multiple-output (MIMO) significantly increases the throughput of a communication system by employing multiple antennas at the transmitter and the receiver. To extract maximum performance from a MIMO system, a computationally intensive search based detector is needed. To meet the challenge of MIMO detection, typical suboptimal MIMO detectors are ASIC or FPGA designs. We aim to show that a MIMO detector on Graphic processor unit (GPU), a low-cost parallel programmable co-processor, can achieve high throughput and can serve as an alternative to ASIC/FPGA designs. However, careful architecture aware software design is needed to leverage the performance offered by GPU. We propose a novel soft MIMO detection algorithm, multi-pass trellis traversal (MTT), and show that we can achieve ASIC/FPGA-like performance and handle different configurations in software on GPU. The proposed design can be used to accelerate wireless physical layer simulations and to offload MIMO detection processing in wireless testbed platforms.     

Turbo-MIMO系统中一种基于部分后验概率的软检测算法

迭代树搜索(ITS)是一种有效的基于M-算法的软MIMO检测方案。然而ITS会遇到某些比特的对数似然比(LLR)无法确定的情况,虽可采用赋常数值方法(称为clipping)解决,但这会影响系统性能。为此,该文提出一种新的基于M-算法的软检测方案。该方案在树的每一级递推计算部分符号序列的后验概率,并基于此近似计算从第1级到该级的所有比特LLR,再采用M-算法保留部分符号序列延伸至下一级。该算法可确保每比特都可计算LLR,且能得到可靠性高的LLR值。考虑到某些比特LLR会多次计算,文中给出了算法的低复杂度实现。另外,该文还给出了一种计算符号序列后验概率的简单方法。最后,仿真结果表明所提算法相比ITS具有更好的性能,并使性能与复杂度达到较好的折中。     

Efficient detection in uniform linear and planar arrays MIMO systems under spatial correlated channels

In this paper, the efficiency of various multiple‐input multiple‐output (MIMO) detectors was analyzed from the perspective of highly correlated channels, where MIMO systems have a lack of performance, besides in some cases, an increasing complexity. Considering this hard but a useful scenario, various MIMO detection schemes were accurately evaluated concerning complexity and bit error rate performance. Specifically, successive interference cancellation, lattice reduction, and the combination of them were associated with conventional linear MIMO detection techniques. To demonstrate effectiveness, a wide range of the number of antennas and modulation formats have been considered aiming to verify the potential of such MIMO detection techniques according to their performance‐complexity trade‐off. We have also studied the correlation effect when both transmit and receiver sides are equipped with uniform linear array and uniform planar array antenna configurations. The performance of different detectors is carefully compared when both antenna array configurations are deployed considering a different number of antennas and modulation order, especially under near‐massive MIMO condition. We have also discussed the relationship between the array factor and the bit error rate performance of both antenna array structures.     

面向LTE-A终端软基带的矢量处理器设计

面向移动终端处理器的低功耗、低成本、高效率、灵活升级的需求,本文在对LTE-A基带算法并行性分析的基础上,提出了一种基于超长指令字（Very Long Instruction Word,VLIW）和单指令多数据（Single Instruction Multiple Data,SIMD）混合结构的矢量处理器作为终端软基带解决方案.该矢量处理器采用变长的VLIW指令字,共有7条矢量数据通路,每条通路可执行16个16bit的定点运算;采用分组的系数存储器提高灵活性,受限访问的寄存器组降低电路面积;同时设计了SHUF和ISHUF指令专门用于快速傅里叶变换（FFT）和雏特比（vIT-ERBI）译码算法的矢量化实现.最后本文实现和分析了FFT和VITERBI译码算法.     

IEEE 802.11ac MIMO Transceiver Baseband Processing on a VLIW Processor

Wireless standards are evolving rapidly due to the exponential growth in the number of portable devices along with the applications with high data rate requirements. Adaptable software based signal processing implementations for these devices can make the deployment of the constantly evolving standards faster and less expensive. The flagship technology from the IEEE WLAN family, the IEEE 802.11ac, aims at achieving very high throughputs in local area connectivity scenarios. This article presents a software based implementation for the Multiple Input and Multiple Output (MIMO) transmitter and receiver baseband processing conforming to the IEEE 802.11ac standard which can achieve transmission bit rates beyond 1Gbps. This work focuses on the Physical layer frequency domain processing. Various configurations, including 2×2 and 4×4 MIMO are considered for the implementation. To utilize the available data and instruction level parallelism, a DSP core with vector extensions is selected as the implementation platform. Then, the feasibility of the presented software-based solution is assessed by studying the number of clock cycles and power consumption of the different scenarios implemented on this core. Such Software Defined Radio based approaches can potentially offer more flexibility, high energy efficiency, reduced design efforts and thus shorter time-to-market cycles in comparison with the conventional fixed-function hardware methods.     

MMSE准则下近似最优MIMO分组并行检测算法

在采用多天线高阶QAM的MIMO通信系统中,现有基于信道分组并行检测算法虽然接近最优检测性能但以牺牲计算效率为代价.针对这一问题,本文提出一种MMSE准则下基于信道分组的并行检测算法,不但有效降低计算复杂度,而且仍保证检测性能.该算法采用MMSE准则下格归约算法改进分组后条件较好子信道矩阵特性,并在消除参考信号基础上利用改进的子信道矩阵对剩余信号以非线性方式进行检测.仿真结果表明:对4×4和6×6MIMO系统,该算法检测性能达到最优,对于8×8 MIMO系统,比最优算法所需信噪比提高约1dB.复杂度分析表明:相比现有信道分组检测算法,相同检测性能下该算法在6×6 MIMO系统中复杂度降低90%以上,在8×8 MIMO系统中复杂度降低98%以上.     

Probabilistically bounded soft sphere detection for MIMO-OFDM receivers: algorithm and system architecture

Iterative soft detection and channel decoding for MIMO OFDM downlink receivers is studied in this work. Proposed inner soft sphere detection employs a variable upper bound for number of candidates per transmit antenna and utilizes the breath-first candidate-search algorithm. Upper bounds are based on probability distribution of the number of candidates found inside the spherical region formed around the received symbolvector. Detection accuracy of unbounded breadth-first candidatesearch is preserved while significant reduction of the search latency and area cost is achieved. This probabilistically bounded candidate-search algorithm improves error-rate performance of non-probabilistically bounded soft sphere detection algorithms, while providing smaller detection latency with same hardware resources. Prototype architecture of soft sphere detector is synthesized on Xilinx FPGA and for an ASIC design. Using area-cost of a single soft sphere detector, a level of processing parallelism required to achieve targeted high data rates for future wireless systems (for example, 1 Gbps data rate) is determined.     

A 4 Gbps current-mode transmitter for 12-bit 250 MSPS ADC

A 4 Gbps transmitter for a 12-bit 250 MSPS pipelined ADCs is presented. A low power current mode (CM) output driver with reverse scaling technique is proposed. A high speed, low power combined serializer is implemented to convert 12 bit parallel data into a seria1 data stream. The whole transmitter is used in a 12-bit 250 MSPS pipelined ADC for the digital output buffer and fabricated in 180 nm 1. 8 V 1P5M CMOS technology. Test results show that the transmitter provides an eye height greater than 800 mV for data rates of both 2 Gbps and 4 Gbps, the 12-bit 250 MSPS ADC achieves the SNR of 69.92 dBFS and SFDR of 81.17 dB with 20.1 MHz input at full sampling speed. The ADC with the 4 Gbps transmitter consumes the power consumption of 395 mW, where the power consumption of transmitter is 75 mW. The ADC occupies an area of 2.5×3.2 mm², where the active area of the transmitter block is 0.5×1.2 mm².