Novel Radix Finite Field Multiplier for GF(2m)

In this paper, a new High-Radix Finite Field multiplication algorithm for GF(2^m) is proposed for the first time. The proposed multiplication algorithm can operate in a Digit-serial fashion, and hence can give a trade-off between the speed, the area , the input/output pin limitation, and the low power consumption by simply varying the digit size. A detailed example of a new Radix-16 GF(2^m) Digit-Serial multiplication architecture adopting the proposed algorithm illustrates a speed improvement of 75% when compared to conventional Radix-2 bit-serial realization. This is made more significant when it is noted that the speed improvement of 75% was achieved at the expense of only 2.3 times increase in the hardware requirements of the proposed architecture.     

Concurrent Error Detection in a Polynomial Basis Multiplier over GF(2 m )

Eliminating cryptographic computation errors is vital for preventing attacks. A simple approach is to verify the correctness of the cipher before outputting it. The multiplication is the most significant arithmetic operation among the cryptographic computations. Hence, a multiplier with concurrent error detection ability is urgently necessary to avert attacks. Employing the re-computing shifted operand concept, this study presents a semi-systolic array polynomial basis multiplier with concurrent error detection with minimal area overhead. Moreover, the proposed multiplier requires only two extra clock cycles while traditional multipliers using XOR trees consume at least extra XOR gate delays in GF(2^m) fields. Chiou-Yng Lee received the Bachelor’s degree (1986) in medical engineering and the M.S. degree in electronic engineering (1992), both from the Chung Yuan university, Taiwan, and the Ph.D. degree in electrical engineering from Chang Gung University, Taiwan, in 2001. From 1988 to now, he was a research associate with Chunghwa Telecommunication Laboratory in Taiwan. He joined the department of project planning. He taught those related field courses at Ching-Yun Technology University. He is currently as an assistant professor of Department of Computer Information and Network Engineering in Lunghwa University of Science and Technology. His research interests include computations in finite fields, error-control coding, signal processing, and digital transmission system. Besides, he is a member of the IEEE and the IEEE Computer society. He is also an honor member of Phi Tao Phi in 2001. Che Wun Chiou received his B.S. degree in Electronic Engineering from Chung Yuan Christian University in 1982, the M.S. degree and the Ph.D. degree in Electrical Engineering from National Cheng Kung University in 1984 and 1989, respectively. From 1990 to 2000, he was with the Chung Shan Institute of Science and Technology in Taiwan. He joined the Department of Electronic Engineering and the Department of Computer Science and Information Engineering, Ching Yun University in 2000 and 2005, respectively. He is currently as Dean of Division of Continuing Education in Ching Yun University. His current research interests include fault-tolerant computing, computer arithmetic, parallel processing, and cryptography. Jim-Min Lin was born on March 5, 1963 in Taipei, Taiwan. He received the B.S. degree in Engineering Science and the M.S. and the Ph.D. degrees in Electrical Engineering, all from National Cheng Kung University, Tainan, Taiwan, in 1985, 1987, and 1992, respectively. Since February 1993, he has been an Associate Professor at the Department of Information Engineering and Computer Science, Feng Chia University, Taichung City, Taiwan. He is currently as Professor at the Department of Information Engineering and Computer Science, Feng Chia University. His research interests include Operating Systems, Software Integration/Reuse, Embedded Systems, Software Agent Technology, and Testable Design.     

有限域GF(2~m)上乘法器的实现

首先介绍了有限域GF(2m)元素不同的基的表示,在此基础上讨论了有限域中常系数乘法器、串行乘法器及并行乘法器的硬件实现。重点介绍了适合高速RS编译码器实现的对偶基比特并行乘法器,并分析了比特并行对偶基乘法器的硬件时延、占用资源的大小。最后对不同乘法器进行了比较。与"查表法"及正规基并行乘法器相比,对偶基比特并行乘法器在速率和硬件规模上有较大优越性。     

Fault-Tolerant Bit-Parallel Multiplier for Polynomial Basis of GF（2^m）

Novel fault-tolerant architectures for bit-parallel polynomial basis multiplier over GF（2^m）, which can correct the erroneous outputs using linear code, are presented. A parity prediction circuit based on the code generator polynomial that leads lower space overhead has been designed. For bit-parallel architectures, the Moreover, there is incorporation of space overhead only marginal time error-correction is about 11%. overhead due to capability that amounts to 3.5% in case of the bit-parallel multiplier. Unlike the existing concurrent error correction （CEC） multipliers or triple modular redundancy （TMR） techniques for single error correction, the proposed architectures have multiple error-correcting capabilities.     

Error Detecting Dual Basis Bit Parallel Systolic Multiplication Architecture over GF（2^m）

An error tolerant hardware efficient verylarge scale integration （VLSI） architecture for bitparallel systolic multiplication over dual base, which canbe pipelined, is presented. Since this architecture has thefeatures of regularity, modularity and unidirectionaldata flow, this structure is well suited to VLSIimplementations. The length of the largest delay pathand area of this architecture are less compared to the bitparallel systolic multiplication architectures reportedearlier. The architecture is implemented using Austria Micro System＇s 0.35 μm CMOS （complementary metaloxide semiconductor） technology. This architecture canalso operate over both the dual-base and polynomialbase.     

基于FPGA技术的GF(2m)域乘法器的研究和设计

椭圆曲线密码体制以其密钥短、安全强度高的优点获得了广泛的重视和应用,而GF(2m)有限域乘法运算是该密码体制最主要的运算.本文研究了基于FPGA芯片的多项式基乘法器的快速设计方法,并给出了面积与速度的比较和分析.     

A Scalable Structure for a Multiplier and an Inversion Unit in GF(2m)

Elliptic curve cryptography (ECC) offers the highest security per bit among the known public key cryptosystems. The operation of ECC is based on the arithmetic of the finite field. This paper presents the design of a 193‐bit finite field multiplier and an inversion unit based on a normal basis representation in which the inversion and the square operation units are easy to implement. This scalable multiplier can be constructed in a variable structure depending on the performance area trade‐off. We implement it using Verilog HDL and a 0.35 µm CMOS cell library and verify the operation by simulation.     

Design and Implementation of a Polynomial Basis Multiplier Architecture Over GF(2m)

In this paper, the design and circuit implementation of a polynomial basis multiplier architecture over Galois Fields GF(2^m) is presented. The proposed architecture supports field multiplication of two m-term polynomials where m is a positive integer. Circuit implementations based on this parameterized architecture where m is configurable is suitable for applications in error control coding and cryptography. The proposed architecture offers low latency, polynomial basis multiplication where the irreducible polynomial P(x)?=?x ^m ?+?p _kt .?x ^kt ?+?…?+?p ₁.?x?+?1 with m ≥ kt + 4 is dynamically reconfigurable. Results of the complexity analysis show that the proposed architecture requires less logic resources compared to existing sequential polynomial basis multipliers. In terms of timing performance, the proposed architecture has a latency of m/4, which is the lowest among the multipliers found in literature for GF(2^m).     

Subquadratic Space Complexity Multiplier for GF(2n) Using Type 4 Gaussian Normal Bases

Subquadratic space complexity multipliers for optimal normal bases (ONBs) have been proposed for practical applications. However, for the Gaussian normal basis (GNB) of type t > 2 as well as the normal basis (NB), there is no known subquadratic space complexity multiplier. In this paper, we propose the first subquadratic space complexity multipliers for the type 4 GNB. The idea is based on the fact that the finite field GF(2ⁿ) with the type 4 GNB can be embedded into fields with an ONB.     

Architectures for exponentiation in GF(2m)

Several VLSI architectures for performing exponentiation in GF(2 ^m) are presented. Two approaches to the architecture design are taken. In the first, all intermediate products of the exponentiation are computed in a sequential fashion to minimize the silicon area. In the second approach, all values of raised to the 2^ei power, O⩽i⩽m-1, are precomputed and stored so that the intermediate product terms can be calculated in a parallel fashion. For the two approaches, both synchronous and asynchronous implementations are presented using standard and normal bases. The discussion emphasizes the design and performance tradeoffs incurred in developing such architectures     

A Fast VLSI Multiplier for GF(2m)

Multiplication in the finite fieldGF(2^{m}) has particular computational advantages in data encryption systems. This paper presents a new algorithm for performing fast multiplication inGF(2^{m}), which isO(m)in computation time and implementation area. The bit-slice architecture of a serial-in-serial-out modulo multiplier is described and the circuit details given. The design is highly regular, modular, and well-suited for VLSI implementation. The resulting multiplier will have application in algorithms based on arithmetic in large finite fields of characteristic 2, and which require high throughput.     

Improved algorithm for division over GF(2/sup m/)

An improved algorithm for division over GF(2/sup m/) is proposed. It is based on a look-ahead procedure that allows division over GF(2/sup m/) to be performed in any number of clock cycles up to 2/sup m/-1. The hardware complexity of the divider depends on the level of look-ahead chosen and hence the speed of operation required. An example using this divider in solving the key equation for single-error correcting Reed-Solomon codes is also considered.<>     

Generation of m-sequences over GF(q2) from m-sequences over GF(q)

A closed form solution that yields the component shift required for the vector representation of m-sequences over GF(q²) in terms of m-sequences over GF(q²) is presented. Iterative application of this expression then enables the vctor representation of m-sequences over GF(q^2m) in terms of m-sequences over GF(q). These vector m-seqeences can be used directly for the selection of frequencies in frequency hopped spread spectrum communication systems.     

用EMODL实现的高速低功耗流水线乘法器

实现快速、低功耗以及节省面积的乘法器对高性能微处理器 (例如 DSP和 RISC)而言是至关重要的。文中详尽论述了新型的增强型多输出多米诺逻辑 ( EMODL)及其 n-MOS赋值树的尺寸优化方法 ,并用它实现了高速低功耗 2 0× 2 0 bit流水线乘法器。最后 ,通过 HSPICE仿真 ,确认了该乘法器结构的优越性 :流水线等待时间小 ( 2倍于系统时钟 )、运算速度高 ( 10 0 MOPS)以及低功耗 ( 2 3 .94m W)     

Novel Radix Finite Field Multiplier for GF(2m)

In this paper, a new High-Radix Finite Field multiplication algorithm for GF(2^m) is proposed for the first time. The proposed multiplication algorithm can operate in a Digit-serial fashion, and hence can give a trade-off between the speed, the area , the input/output pin limitation, and the low power consumption by simply varying the digit size. A detailed example of a new Radix-16 GF(2^m) Digit-Serial multiplication architecture adopting the proposed algorithm illustrates a speed improvement of 75% when compared to conventional Radix-2 bit-serial realization. This is made more significant when it is noted that the speed improvement of 75% was achieved at the expense of only 2.3 times increase in the hardware requirements of the proposed architecture.     

GF（2^8）上快速乘法器及求逆器的设计

基于多项式乘法理论，采用高层次设计方法，设计并采用ＦＰＧＡ实现了ＧＦ（２＾８）上８位快速乘法器，并利用该乘法器设计了一个计算ＧＦ（２＾８）上任一元素的例数的求逆器，该乘法器与求逆器可以应用于ＲＳ（２５５．２２３）码编／译码器。     

GF（2^m）域高速椭圆曲线加密处理器设计

针对高速椭圆曲线加密应用的要求,设计了一种多项式基表示的有限域GF(2m)上的高速椭圆加密处理器.为提高运算速度,点加和倍点模块并行运算,且分别采用全并行结构实现;为减少资源,初始化和最后的坐标变换求逆模块通过优化分解成一系列乘和加运算,合并在一个模块中用串行结构实现.Xilinx公司的VirtexEXCV2600 FPGA硬件实现结果表明,完成有限域GF(2163)上任意椭圆曲线上的一次点乘的全部运算时间消耗约为31.6μs,适合高速椭圆曲线加密应用的要求.     

基于GF(2~m)上椭圆曲线点乘的实现

给出了椭圆曲线加密算法的点乘实现.在实现模乘运算时,把相乘过程和模约多项武过程结合起来,以改善运算效率.片外双口RAM的使用,加快了数据存取速度,同时通过预留RAM空间,增强了系统的可扩充性.本设计用VerilogHDL语言作为设计工具,在synopsys DC Z-2007 03 solaris9工作平台上,基于chartered 0.35 CMOS的综合库,50MHz约束下综合出结果约为18657门.     

Research on encoding and decoding of non-binary polar codes over GF(2m)

Binary Polar Codes (BPCs) have advantages of high-efficiency and capacity-achieving but suffer from large latency due to the Successive-Cancellation List (SCL) decoding. Non-Binary Polar Codes (NBPCs) have been investigated to obtain the performance gains and reduce latency under the implementation of parallel architectures for multi-bit decoding. However, most of the existing works only focus on the Reed-Solomon matrix-based NBPCs and the probability domain-based non-binary polar decoding, which lack flexible structure and have a large computation amount in the decoding process, while little attention has been paid to general non-binary kernel-based NBPCs and Log-Likelihood Ratio (LLR) based decoding methods. In this paper, we consider a scheme of NBPCs with a general structure over GF(2^m). Specifically, we pursue a detailed Monte-Carlo simulation implementation to determine the construction for proposed NBPCs. For non-binary polar decoding, an SCL decoding based on LLRs is proposed for NBPCs, which can be implemented with non-binary kernels of arbitrary size. Moreover, we propose a Perfect Polarization-Based SCL (PPB-SCL) algorithm based on LLRs to reduce decoding complexity by deriving a new update function of path metric for NBPCs and eliminating the path splitting process at perfect polarized (i.e., highly reliable) positions. Simulation results show that the bit error rate of the proposed NBPCs significantly outperforms that of BPCs. In addition, the proposed PPB-SCL decoding obtains about a 40% complexity reduction of SCL decoding for NBPCs.     

基于GF(2m)的ECC中底层运算的快速实现

椭圆曲线密码系统高速实现的关键是点的数乘与加法,实现点的数乘与加法要在基域中做大量的算术运算,其中最耗时的是域元素的乘法。本文给出了一类有限域GF(2m)中乘法的快速实现方法,该方法简单、高效,容易硬件实现。