Cost/performance perspectives of paging with electronic and electromechanical backing stores

An analysis is made of the cost/performance effectiveness of virtual memory systems employing paging disks or drums and those employing electronic backing stores such as charge coupled devices (CCD), MOS shift registers, or bubbles. The analysis is based on a multiprogrammed job stream and a simplified queuing model employing page-fault rates suitable for a variety of multiprogrammed environments. Smaller memory systems and single job programming are also considered. It is shown that memory access plus page transfer time is a critical parameter, in addition to cost. Curves are generated for a variety of job environments in which the cost/performance effectiveness of two-level memory hierarchies employing electronic backing stores is compared to that of systems employing paging drums. Competitive prices per bit are determined for a number of system environments. The analysis clearly demonstrates that in many problem environments, the electronic backing store will replace the traditional paging drum or disk if the cost per bit is significanfly less than the main memory cost per bit as projected. Disk and tape memories can be expected to continue as the dominant memories for bulk storage in the near future because of their already small and diminishing costs per bit.     

Memory allocation and mapping in high-level synthesis - an integrated approach

With the increasing design complexity and performance requirement, data arrays in behavioral specification are usually mapped to memories in behavioral synthesis. This paper describes a new algorithm that overcomes two limitations of the previous works on the problem of memory-allocation and array-mapping to memories. Specifically, its key features are a tight link to the scheduling effect, which was totally or partially ignored by the existing memory synthesis systems, and supporting nonuniform access speeds among the ports of memories, which greatly diversify the possible (practical) memory configurations. Experimental data on a set of benchmark filter designs are provided to show the effectiveness of the proposed exploration strategy in finding globally best memory configurations.     

Memory binding for performance optimization of control-flow intensive behavioral descriptions

This paper presents a memory binding algorithm for behaviors, used in application-specific integrated circuits (ASICs), that are characterized by the presence of conditionals and deeply nested loops that access memory extensively through arrays. Unlike previous works, this algorithm examines the effects of branch probabilities and allocation constraints. First, we demonstrate, through examples, the importance of incorporating branch probabilities and allocation constraint information when searching for a performance-efficient memory binding. We also show the interdependence of these two factors and how varying one without considering the other may greatly affect the performance of the behavior. Second, we introduce a memory binding algorithm that has the ability to examine numerous bindings by employing an efficient performance estimation procedure. The estimation procedure exploits locality of execution, which is an inherent characteristic of target behaviors. This enables the performance estimation technique to look at the global impact of the different bindings, given the allocation constraints. We tested our algorithm using a number of benchmarks from the parallel computing domain. A series of experiments demonstrates the algorithm's ability to produce bindings that optimize performance, meet memory allocation constraints, and adapt to different resource constraints and branch probabilities. One limitation of our algorithm is that, in its current form, it is not well suited for system-on-a-chip synthesis where there is complex communication between general-purpose microprocessors that use custom-designed arrays. Results show that the algorithm requires 41% fewer memories with a performance loss of only 0.2% when compared to a parallel memory architecture. When compared to the best of a series of random memory bindings, the algorithm improves schedule performance by 22%.     

一种为地面节点充电的多UAV任务分配与路线规划方法

以多个无人机（UAV）为大面积分布的传感器节点无线充电为应用场景，提出了一种分布式快速拍卖算法（DFAMTA）用于为多个UAV分配任务及规划航线。利用该算法，不需集中控制器，每个UAV根据自己的续航能力和获知的节点位置及剩余电量信息，建立包含多个节点的任务集进行投标；中标者的确定在单个任务层面上独立并行进行，大大节省了任务分配的收敛时间。理论证明，DFAMTA算法在最差情况下也能获得最优分配算法50%的性能。仿真验证了算法在收敛时间上的优势以及在改善无线传感器网络系统平均覆盖率方面的优越性。     

基于概率内存分配的内存安全研究

Some unsafe languages, like C and C+ + , let programmers maximize performance but are vulnerable to memory errors which can lead to program crashes and unpredictable behavior. Aiming to solve the problem, traditional memory allocating strategy is improved and a new probabilistic memory allocation technology is presented. By combining random memory allocating algorithm and virtual memory, memory errors are avoided in all probability during software executing. By replacing default memory allocator to manage allocation of heap memory, buffer overflows and dangling pointers are prevented. Experiments show it is better than Die-hard of the following aspects: memory errors prevention, performance in memory allocation set and ability of controlling working set. So probabilistic memory allocation is a valid memory errors prevention technology and it can tolerate memory errors and provide probabilistic memory safety effectively.     

Synthesis of custom interleaved memory systems

This paper presents a novel approach to the synthesis of interleaved memory systems that is especially suited for application-specific processors. Our synthesis system generates the optimized interleaved memories for a specific algorithm and finds the best mapping of arrays in that algorithm onto the memory system to achieve high performance. The design space is four-dimensional (4-D) and comprises the number of memory banks, the type of memory components, the storage scheme, and the range of clock period in the system. Optimal designs are found among the Pareto points (a set of nondominated points in the design space) computed for our memory model under the performance and cost criteria set by the designer. The memory model includes all the components of an interleaved memory system and covers a lookup table-based address generation with data alignment. The synthesis is based on a general periodic storage scheme, which enables efficient handling of irregular and overlapped access patterns. The synthesis process is the exhaustive search of the heavily pruned design space, and the pruning is based on mathematically proven properties of periodic storage schemes. This paper presents the theorems, the synthesis algorithm, and the methods of effective word and bank address generation. Examples are given to illustrate the effectiveness of our method     

Layout-driven memory synthesis for embedded systems-on-chip

Memory-processor integration offers new opportunities for reducing, the energy of a system. In the case of embedded systems, where memory access patterns can typically be profiled at design time, one solution consists of mapping the most frequently accessed addresses onto the on-chip SRAM to guarantee power and performance efficiency. In this work, we propose an algorithm for the automatic partitioning of on-chip SRAMs into multiple banks. Starting from the dynamic execution profile of an embedded application running on a given processor core, we synthesize a multi-banked SRAM architecture optimally fitted to the execution profile. The algorithm computes an optimal solution to the problem under realistic assumptions on the power cost metrics, and with constraints on the number of memory banks. The partitioning algorithm is integrated with the physical design phase into a complete flow that allows the back annotation of layout information to drive the partitioning process. Results, collected on a set of embedded applications for the ARM processor, have shown average energy savings around 34%     

Performance evaluation of a reconfiguration-algorithm for memoryarrays containing clustered faults

Reconfiguration of memory arrays using spare rows and columns is useful for yield-enhancement of memories. This paper presents a reconfiguration algorithm (QRCF) for memories that contain clustered faults. QRCF operates in a branch and bound fashion similar to known optimal algorithms that require exponential time. However, QRCF repairs faults in clusters rather than individually. Since many faults are repaired simultaneously, the execution-time of QRCF does not become prohibitive even for large memories containing many faults. The performance of QRCF is evaluated under a probabilistic model for clustered faults in a memory array. For a special case of the fault model, QRCF solves the reconfiguration problem exactly in polynomial time. In the general case, QRCF produces an optimal solution with high probability. The algorithm is also evaluated through simulation. The performance and execution-time of QRCF on arrays containing clustered faults are compared with other approximation algorithms and with an optimal algorithm. The simulation results show that QRCF outperforms previous approximation algorithms by a wide margin and performs nearly as well as the optimal algorithm with an execution-time that is orders of magnitude less     

一种数字系统综合中存储器规划的改进算法

用ＶＨＤＬ语言描述的数字系统中,经常使用大量的数组对应于真实系统中的存储器,减少存储器的操作时间对于提高整个系统的速度是一个非常有意义的问题,而改进存储器的地址生成技术是解决这个问题的途径之一。文章研究了一些与此相关的新技术＾「１」,但这些新技术的使用将增加一些 余的存储单元,特别是对于多数组问题。为此,提出了一种多启发式组合算法,以求同时达到尽量减小冗余量和提高计算速度的目的。     

Multichannel cooperative sensing for cognitive radio with users owning heterogeneous sensing ability

Multichannel cooperative sensing (MCS) is an effective method for dynamic spectrum access in cognitive radio networks. In contrast to most existing work on MCS that considered secondary users with homogeneous sensing ability, this paper studies the MCS problem for secondary users with heterogeneous sensing ability in terms of sensing accuracy. We further take into account different parameters of primary channels such as bandwidth, probability of being idle in each sensing period, and frequency selective fading at the sensing receiver. The MCS problem is formulated as a weapon target assignment problem, where more sensing resources are assigned to channels that are more valuable. This weapon target assignment problem is transformed to an integer generalized network flow problem with convex flow costs to obtain the lower bound solution, and then solved by the branch and bound algorithm with this bound to yield the exact scheme. To reduce computational complexity, a heuristic scheme is also proposed, which has approximate performance compared with the exact scheme. Finally, extensive simulation results for different scenarios illustrate the performance improvements of the proposed schemes over the existing scheme. Copyright © 2013 John Wiley & Sons, Ltd.     

A 64-kbit block addressed charge-coupled memory

This paper describes the design and performance of a 64-kbit (65 536 bits) block addressed charge-coupled serial memory. By using the offset-mask charge-coupled device (CCD) electrode structure to obtain a small cell size, and an adaptive system approach to utilize nonzero defect memory chips, the system cost per bit of charge-coupled serial memory can be reduced to provide a solid-state replacement of moving magnetic memories and to bridge the gap between high cost random access memories (RAM's) and slow access magnetic memories. The memory chip is organized as 64K words by 1 bit in 16 blocks of 4 kbits. Each 4-kbit block is organized as a serial-parallel-serial (SPS) array. The chip is fully decoded with write/recirculate control and two-dimensional decoding to permit memory matrix organization with X-Y chip select control. All inputs and the ouput are TTL compatible. Operated at a data rate of 1 MHz, the mean access time is about 2 ms and the average power dissipation is 1 µW/bit. The maximum output data rate is 10 MHz, giving a mean access time of about 200 µs, and an average power dissipation of 10 µW/bit. The memory chip is fabricated using an n-channel polysilicon gate process. Using tolerant design rules (8-µm minimum feature size and ±2-µm alignment tolerance) the CCD cell size is 0.4 mil²and the total chip size is 218 × 235 mil². The chip is mounted in a 22-pin 400-mil wide ceramic dual in-line package.     

A Novel Bandwidth Allocation Algorithm for IEEE 802.16 TDD Mode Wireless Access Networks

In this paper, we propose a novel bandwidth allocation algorithm for a two-tier hierarchy in IEEE 802.16 time division duplex mode wireless access networks under symmetric and/or asymmetric uplink and downlink traffic input. We demonstrate the performance of the new bandwidth allocation algorithm in terms of accumulated throughput (cumulative bandwidth) and fairness in both infinite and finite buffer cases compared with others by simulations. The simulation results show that the proposed algorithm not only can provide much better fairness and maintain satisfactory QoS support and high cumulative bandwidth but also in the case of finite buffer depth is less buffer-consuming than the others, meaning that the hardware cost can be reduced by employing the proposed algorithm.     

A 64-kbit block addressed charge-coupled memory

Describes the design and performance of a 64-kbit (65536 bits) block addressed charge-coupled serial memory. By using the offset-mask charge-coupled device (CCD) electrode structure to obtain a small cell size, and an adaptive system approach to utilize nonzero defect memory chips, the system cost per bit of charge-coupled serial memory can be reduced to provide a solid-state replacement of moving magnetic memories and to bridge the gap between high cost random access memories (RAM's) and slow access magnetic memories.     

Benefit-Based Data Caching in Ad Hoc Networks

Data caching can significantly improve the efficiency of information access in a wireless ad hoc network by reducing the access latency and bandwidth usage. However, designing efficient distributed caching algorithms is nontrivial when network nodes have limited memory. In this article, we consider the cache placement problem of minimizing total data access cost in ad hoc networks with multiple data items and nodes with limited memory capacity. The above optimization problem is known to be NP-hard. Defining benefit as the reduction in total access cost, we present a polynomial-time centralized approximation algorithm that provably delivers a solution whose benefit is at least 1/4 (1/2 for uniform-size data items) of the optimal benefit. The approximation algorithm is amenable to localized distributed implementation, which is shown via simulations to perform close to the approximation algorithm. Our distributed algorithm naturally extends to networks with mobile nodes. We simulate our distributed algorithm using a network simulator (ns2) and demonstrate that it significantly outperforms another existing caching technique (by Yin and Cao [33]) in all important performance metrics. The performance differential is particularly large in more challenging scenarios such as higher access frequency and smaller memory.     

自适应喷雾聚焦机会网络路由算法

针对现有喷雾路由算法不能依据实际情况动态调整消息拷贝数,而导致资源浪费的问题,提出一种自适应喷雾聚焦路由算法ADPSF。ADPSF依据节点密度估算消息拷贝数,依据相遇概率历史信息选择中继节点和分配消息副本数。仿真试验表明,ADPSF算法在保证消息交付率和时延的情况下有效降低网络开销。     

Synthesis of application-specific memory designs

This paper discusses the mapping of arrays in a behavior to memories in an implementation. We introduce a novel approach to the design of memory systems, which is based on a variety of array grouping techniques and dimensional transformations, and the binding of array groups to memory components with different dimensions, access times, and number of ports. The results of design actions are computed in terms of memory cost, the number of wires necessary to connect the memory to the data path, and the limit of performance imposed by the memory design on the implementation. Three different procedures can be used to find a suitable memory design. All three procedures are directed by a weighted and constrained system cost function, which enables the expression of the user's design priorities. Compared to related research efforts, our approach improves performance by as much as 19%, reduces memory cost as 40%, and decreases the number of wires required to connect the memory to the data path by up to 57%     

Adaptive resource allocation for multicast orthogonal frequency division multiple access systems with guaranteed BER and rate

In this paper, we propose a resource allocation scheme to minimize transmit power for multicast orthogonal frequency division multiple access systems. The proposed scheme allows users to have different symbol error rate (SER) across subcarriers and guarantees an average bit error rate and transmission rate for all users. We first provide an algorithm to determine the optimal bits and target SER on subcarriers. Because the worst‐case complexity of the optimal algorithm is exponential, we further propose a suboptimal algorithm that separately assigns bit and adjusts SER with a lower complexity. Numerical results show that the proposed algorithm can effectively improve the performance of multicast orthogonal frequency division multiple access systems and that the performance of the suboptimal algorithm is close to that of the optimal one. Copyright © 2012 John Wiley & Sons, Ltd.     

车辆网络多平台卸载智能资源分配算法

为了降低计算任务的时延和系统的成本,移动边缘计算(MEC)被用于车辆网络,以进一步改善车辆服务。该文在考虑计算资源的情况下对车辆网络时延问题进行研究,提出一种多平台卸载智能资源分配算法,对计算资源进行分配,以提高下一代车辆网络的性能。该算法首先使用K临近(KNN)算法对计算任务的卸载平台(云计算、移动边缘计算、本地计算)进行选择,然后在考虑非本地计算资源分配和系统复杂性的情况下,使用强化学习方法,以有效解决使用移动边缘计算的车辆网络中的资源分配问题。仿真结果表明,与任务全部卸载到本地或MEC服务器等基准算法相比,提出的多平台卸载智能资源分配算法实现了时延成本的显著降低,平均可节省系统总成本达80%。     

LTE系统中PDCCH资源分配算法的研究

为了降低LTE系统中PDCCH(physical downlink control channel,物理下行控制信道)的阻塞率,提高控制信道的资源利用率,本文通过研究目前的两种资源分配算法,结合两者优点提出了一种改进后的算法。该算法首先根据CQI(channel quality indicator,信道质量指示)确定CCE(control channel element,控制信道粒子)聚合等级,并进行资源分配,计算可能的聚合等级集合,在首次不成功的情况下,在可能的聚合等级集合中选取下次使用的等级,直到分配成功或遍历所有集合中的等级。仿真结果表明,改进后的算法提高了资源利用率,并相对降低了阻塞率。     

基于云雾混合计算的车联网联合资源分配算法

针对车联网业务的低时延、低功耗需求及海量设备计算卸载引起的网络拥塞问题,该文提出一种在云雾混合网络架构下的联合计算卸载、计算资源和无线资源分配算法(JODRAA)。首先,该算法考虑将云计算与雾计算结合,以最大时延作为约束,建立最小化系统能耗和资源成本的资源优化模型。其次,将原问题转化为标准二次约束二次规划(QCQP)问题,并设计一种低复杂度的联合卸载决策和计算资源分配算法。进一步,针对海量设备计算卸载引起的网络拥塞问题,建立卸载用户接入请求队列的上溢概率估计模型,提出一种基于在线测量的雾节点时频资源配置算法。最后,借助分式规划理论和拉格朗日对偶分解方法得到迭代的带宽和功率分配策略。仿真结果表明,该文算法可以在满足时延需求的前提下,最小化系统能耗和资源成本。