EVE: A Flexible SIMD Coprocessor for Embedded Vision Applications

In this paper we introduce EVE (embedded vision/vector engine), with a FlexSIMD (flexible SIMD) architecture highly optimized for embedded vision. We show how EVE can be used to meet the growing requirements of embedded vision applications in a power- and area-efficient manner. EVE’s SIMD features allow it to accelerate low-level vision functions (such as image filtering, color-space conversion, pyramids, and gradients). With added flexibility of data accesses, EVE can also be used to accelerate many mid-level vision tasks (such as connected components, integral image, histogram, and Hough transform). Our experiments with a silicon implementation of EVE show that it performs many low- and mid-level vision functions with a 3–12x speed advantage over a C64x+DSP, while consuming less power and area. EVE also achieves code size savings of 4–6x over a C64x+DSP for regular loops. Thanks to its flexibility and programmability, we were able to implement two end-to-end vision applications on EVE and achieve more than a 5× application-level speedup over a C64x+. Having EVE as a coprocessor next to a DSP or a general purpose processor, algorithm developers have an option to accelerate the low- and mid-level vision functions on EVE. This gives them more room to innovate and use the DSP for new, more complex, high-level vision algorithms.     

Floating Point CGRA based Ultra-Low Power DSP Accelerator

Journal of Signal Processing Systems - Coarse Grained Reconfigurable Arrays (CGRAs) are emerging as energy efficient accelerators providing a high grade of flexibility in both academia and...     

Energy-Efficient Multiple-Precision Floating-Point Multiplier for Embedded Applications

Floating-point (FP) multipliers are the main energy consumers in many modern embedded digital signal processing (DSP) and multimedia systems. For lossy applications, minimizing the precision of FP multiplication operations under the acceptable accuracy loss is a well-known approach for reducing the energy consumption of FP multipliers. This paper proposes a multiple-precision FP multiplier to efficiently trade the energy consumption with the output quality. The proposed FP multiplier can perform low-precision multiplication that generates 8?, 14?, 20?, or 26-bit mantissa product through an iterative and truncated modified Booth multiplier. Energy saving for low-precision multiplication is achieved by partially suppressing the computation of mantissa multiplier. In addition, the proposed multiplier allows the bitwidth of mantissa in the multiplicand, multiplier, and output product to be dynamically changed when it performs different FP multiplication operations to further reduce energy consumption. Experimental results show that the proposed multiplier can achieve 59 %, 71 %, 73 %, and 82 % energy saving under 0.1 %, 1 %, 5 %, and 11 % accuracy loss, respectively, for the RGB-to-YUV & YUV-to-RGB conversion when compared to the conventional IEEE single-precision multiplier. In addition, the results also exhibit that the proposed multiplier can obtain more energy reduction than previous multiple-precision iterative FP multipliers.     

Carbon Nanotube Optoelectronic Synapse Transistor Arrays with Ultra-Low Power Consumption for Stretchable Neuromorphic Vision Systems

High-performance stretchable optoelectronic synaptic transistor arrays are key units for constructing and mimicking simulated neuromorphic vision systems. In this study, ultra-low power consumption and low-operation-voltage stretchable all-carbon optoelectronic synaptic thin film transistors (TFTs) using sorted semiconducting single-walled carbon nanotubes (sc-SWCNTs) modified with CdSe/ZnS quantum dots as active layers on ionic liquid-based composite elastomer substrates are first reported. The resulting stretchable TFT devices show enhancement-mode characteristics with excellent electrical properties (such as the record on/off ratios up to 10⁵, negligible hysteresis, and small subthreshold swing), excellent mechanical tensile properties (such as the only 12.4% and 6.4% degradations of the carrier mobility after 20% vertical and horizontal strain stretching), and optoelectronic synaptic plasticity (for the recognition of Morse codes) with ultra-low power consumptions (15.38 aJ) at the operating voltage from −1 to 0.2 V. At the same time, the designed nonvolatile conductance of the stretchable SWCNT optoelectronic synapse thin film transistors (SSOSTFTs) stimulated by UV light and the bending angle are first used to simulate stretchable neuromorphic vision systems (including the functions of the crystalline lens and optic cone cells as bionic eyes) for detecting the atmospheric environment with a record accuracy of 95.1% as a bionic eye.     

An Energy-Efficient BTB Lookup Scheme for Embedded Processors

In this brief, we propose an energy-efficient branch target buffer (BTB) lookup scheme for the embedded processors. Unlike the traditional scheme in which the BTB has to be looked up every instruction fetch, in our design, the BTB is only looked up when the instruction is likely to be a taken branch. By dynamically profiling the taken traces during program execution, the new scheme can achieve the goal of one BTB lookup per taken trace. The experimental results show that, by filtering out the redundant lookups, our design can reduce the total processor energy consumption by about 5.24% on average for the MediaBench applications.     

一种皮瓦级超低功耗电压基准源

设计了一种皮安级电源电流的高精度电压基准源.采用一种新型的PVT(工艺、电源、温度)补偿技术,在保证超低功耗的同时,有效抑制了PVT变化对电路性能的影响,提高了基准电压的稳定性和精度.基于标准0.18μm CMOS工艺进行设计,采用Spectre进行仿真.结果 表明,在0.9～1.8V输入电源电压下,输出电压为755....     

高能效系统的功耗优化技术

本本将叙述了各种系统选择方案及其对系统功耗的影响,全面介绍了处理器电源管理功能,并讨论总系统功耗的一些重要促进因素。本文网络版地址：http：//www.eepw.com.cn/article/164395.htm     

一种皮瓦级超低功耗基准电压源

提出一种皮瓦级、超低功耗的新型基准电压源。该电路利用工作在亚阈值区的不同类型MOS管的栅源电压差,获得在不同工艺角下均有良好温度特性的基准电压。同时,加入校准电路来减小工艺偏差对基准电压的影响。采用0.18 μm CMOS工艺,对电路进行设计和仿真。仿真结果表明,该基准电压源的工作电压范围为0.6~2 V,线性灵敏度为0.13 %/V；在TT工艺角、0.6 V电源电压下,电路典型功耗为130 pW；在-40 ℃~110 ℃范围内,校准后,温度系数范围为2.04×10-5/℃~9.38×10-5/℃。该电路适用于射频识别、无线传感器、医用植入式芯片等超低功耗片上系统中。     

Light-Mediated Multi-Level Flexible Copper Iodide Resistive Random Access Memory for Forming-Free,Ultra-Low Power Data Storage Application

This study demonstrates the efficacy of an emerging p-type copper iodide (CuI) semiconductor in a flexible, low-voltage resistive random-access memory (RRAM), which can be readily integrated with metal-oxide n-type counterparts for complementary circuit systems. Herein, CuI RRAM devices are implemented via a room-temperature solid iodination process, exhibiting a consistent On/Off ratio (≈10⁴), excellent endurance of more than ≈10³ cycles, together with a long retention period (> 5 × 10⁴ s). Furthermore, a scheme of light-mediated multi-level data storage is demonstrated using blue light illumination (λ = 455 nm), to exploit possible photonic memristive functionality through notable photo-response of CuI. In addition, the current conduction and resistive switching behaviors are systematically studied via low-temperature measurements from 203 to 343 K, validating thermal stability and the governing key switching mechanism in CuI RRAM devices. The longstanding problem with CuI device longevity is effectively addressed via PMMA encapsulation, resulting in a 15-fold improvement in the lifespan of devices even in air, as compared with non-passivated devices. These findings suggest that flexible optoelectronic systems, combined with reliable, ultra-low power CuI RRAM devices with photo memristive functionality, can leverage the enhancement of multifunctional selectors required in process-in-memories and the synaptic elements of neuromorphic applications.     

Energy-Efficient Power Allocation for Multi-user Single-DF-Relay Networks

Wireless Personal Communications - In wireless relay networks, energy efficiency not only affects the lifetime of mobile terminals, but also is a promising way to realize high-rate green...     

一种并行内建自诊断测试嵌入式SRAM方案

本文提出了具有自诊断功能的位定向MARCH-TB算法和字定向MARCH-TBW算法，并且在这两个算法的基础上提出并行测试结构来实现了嵌入式内存的测试和诊断。实验结果表明，此测试算法具有故障覆盖率高，诊断故障能力强，测试需要的时间少等优点。     

一种超低功耗SAR A/D转换器

基于TSMC 0.18 μm CMOS工艺,设计了一种用于植入式生物传感器的超低功耗逐次逼近型(SAR)A/D转换器。采用改进的单调开关切换方式,实现了超低功耗。采用动态比较器,消除了静态功耗。采用改进的自举开关结构,提高了采样开关在低电源电压下的线性度。后仿真结果表明,该SAR A/D转换器在1 kS/s采样率、0.6 V电源电压的条件下,整体功耗仅为8.7 nW,有效位数达到9.76 位。     

面向植入式射频识别的超低功耗温度传感器

针对应用于动物体温检测的植入式射频识别标签(RFID),设计了一种超低功耗的温度传感器。采用差分延时线结构和差分型电压电流转换器,增大了时间随温度的变化率,提高了温度传感器的分辨率和精度。基于SMIC 0.18 μm CMOS工艺,采用Cadence SpectreVerilog进行仿真。结果表明,在TT、FF和SS工艺角下,当温度范围为35 ℃~45 ℃时,温度传感器的分辨率为0.03 ℃/LSB,误差为±0.2 ℃,功耗为600 nW,测温时间为1 ms。该温度传感器满足应用于动物体温检测的植入式RFID的要求。     

一种适用于超低功耗MCU的振荡器设计

提出并设计了一种新型低速振荡器,利用MCU电路内部的主时钟对低速时钟进行测试并且自校准,在几乎不增加功耗的前提下可以大大提高低速振荡器的精度和稳定性。与常规的低速振荡器相比,该结构具有功耗低、精度高、稳定性好的优点。仿真结果表明,此电路结构符合设计预期。     

用于数字通信接口的稳健且超低功耗的隔离

在线座谈（Online Seminar）是中电网于2000年推出的创新服务,通过＂视频演示＋专家解说＋在线问答＂三位一体相结合的形式,充分发挥网络平台的便捷性,实现了先进半导体技术提供商与系统设计工程师的实时互动交流,其形式和内容都广受电子行业工程师的好评。本刊每期将挑选一些精华内容整理成文,以飨读者。欲了解更多、更详细的内容,敬请登录http：//seminar.eccn.com。     

Ultra-Low Power Truly Random Number Generator for RFID Tag

This paper proposes low power, low voltage Truly Random Number Generators (TRNG) for Electrical Product Code (EPC Generation 2 Radio Frequency Identification (RFID) tag. Design considerations and trade-offs among randomicity, chip area and power consumption are analyzed according to the special requirements of Gen2 RFID tag. The proposed TRNG circuits consist of an analog random seed generator which uses the oscillator sampling mechanism, and Linear Feedback Shift Registers for post digital processing. These TRNG are implemented in SMIC 0.18 μm CMOS process. And their randomicity performances are verified by the FIPS 140-2 standard for security. One of the TRNG circuits outputs a random bit series at a speed of 40 kHz. Its power consumption is 1.04 μW and chip area is 0.05 mm². The other one has a bit rate at 48 kHz. It has a power consumption of 2.6 μW and chip area of 0.018 mm². The features of low power and small chip area in these TRNG circuits provide a good choice to solve the security and privacy problems in RFID systems.     

A Novel Electrically Tunable RF Inductor With Ultra-Low Power Consumption

In this study, we propose for the first time an electrically and continuously tunable RF inductor using grounded metal oxide semiconductor (MOS) transistor as a control device. By adjusting the output resistance of the grounded MOSFET, the ground-return current can lead to a significant variation in series inductance. This proposed inductor structure was implemented in a standard CMOS process and characterized up to 30 GHz, which demonstrates maximum inductance variations of 32% and 58% at 5.8 and 18 GHz, respectively. The dc power consumption of the proposed design is kept within 50 muW over the entire tuning range.     

多载波超密集网络的抗干扰分布式节能功率分配

该文研究多载波超密集网络(UDN)上行链路能效最优功率分配方案,基于非合作博弈论提出一种抗干扰分布式功率分配方案,使每个小区独立优化能效的同时抑制邻小区干扰.由于最大传输功率和QoS约束下的能效函数具有不易解决的非凸特性,且小小区间存在严重干扰.针对以上挑战,该文在最佳响应过程中设计了一种高精度低复杂度的阶梯注水算法,基于该算法利用干扰信道增益提出了一种多用户抗干扰功率分配算法.仿真结果和数值分析表明该算法运算复杂度低,且能在保证系统频谱效率的同时大幅度提升系统能效.     

多载波超密集网络的抗干扰分布式节能功率分配

该文研究多载波超密集网络(UDN)上行链路能效最优功率分配方案,基于非合作博弈论提出一种抗干扰分布式功率分配方案,使每个小区独立优化能效的同时抑制邻小区干扰.由于最大传输功率和QoS约束下的能效函数具有不易解决的非凸特性,且小小区间存在严重干扰.针对以上挑战,该文在最佳响应过程中设计了一种高精度低复杂度的阶梯注水算法,...     

Energy-Efficient Power Allocation for IoT Devices in CR-NOMA Networks

Non-orthogonal multiple access is a promising technique to meet the harsh requirements for the internet of things devices in cognitive radio networks.To improve the energy efficiency(EE)of the unlicensed secondary users(SU),a power allocation(PA)algorithm with polynomial complexity is investigated.We first establish the feasible range of power consumption ratio using Karush-Kuhn-Tucker optimality conditions to support each SU’s minimum quality of service and the effectiveness of successive interference cancellation.Then,we formulate the EE optimization problem considering the total transmit power requirements which leads to a non-convex fractional programming problem.To efficiently solve the problem,we divide it into an inner-layer and outer-layer optimization sub-problems.The inner-layer optimization which is formulated to maximize the sub-carrier PA coefficients can be transformed into the difference of convex programming by using the first-order Taylor expansion.Based on the solution of the inner-layer optimization sub-problem,the concave-convex fractional programming problem of the outer-layer optimization sub-problem may be converted into the Lagrangian relaxation model employing the Dinkelbach algorithm.Simulation results demonstrate that the proposed algorithm has a faster convergence speed than the simulated annealing algorithm,while the average system EE loss is only less than 2%.