EVE: A Flexible SIMD Coprocessor for Embedded Vision Applications

In this paper we introduce EVE (embedded vision/vector engine), with a FlexSIMD (flexible SIMD) architecture highly optimized for embedded vision. We show how EVE can be used to meet the growing requirements of embedded vision applications in a power- and area-efficient manner. EVE’s SIMD features allow it to accelerate low-level vision functions (such as image filtering, color-space conversion, pyramids, and gradients). With added flexibility of data accesses, EVE can also be used to accelerate many mid-level vision tasks (such as connected components, integral image, histogram, and Hough transform). Our experiments with a silicon implementation of EVE show that it performs many low- and mid-level vision functions with a 3–12x speed advantage over a C64x+DSP, while consuming less power and area. EVE also achieves code size savings of 4–6x over a C64x+DSP for regular loops. Thanks to its flexibility and programmability, we were able to implement two end-to-end vision applications on EVE and achieve more than a 5× application-level speedup over a C64x+. Having EVE as a coprocessor next to a DSP or a general purpose processor, algorithm developers have an option to accelerate the low- and mid-level vision functions on EVE. This gives them more room to innovate and use the DSP for new, more complex, high-level vision algorithms.     

Floating Point CGRA based Ultra-Low Power DSP Accelerator

Journal of Signal Processing Systems - Coarse Grained Reconfigurable Arrays (CGRAs) are emerging as energy efficient accelerators providing a high grade of flexibility in both academia and...     

Energy-Efficient Multiple-Precision Floating-Point Multiplier for Embedded Applications

Floating-point (FP) multipliers are the main energy consumers in many modern embedded digital signal processing (DSP) and multimedia systems. For lossy applications, minimizing the precision of FP multiplication operations under the acceptable accuracy loss is a well-known approach for reducing the energy consumption of FP multipliers. This paper proposes a multiple-precision FP multiplier to efficiently trade the energy consumption with the output quality. The proposed FP multiplier can perform low-precision multiplication that generates 8?, 14?, 20?, or 26-bit mantissa product through an iterative and truncated modified Booth multiplier. Energy saving for low-precision multiplication is achieved by partially suppressing the computation of mantissa multiplier. In addition, the proposed multiplier allows the bitwidth of mantissa in the multiplicand, multiplier, and output product to be dynamically changed when it performs different FP multiplication operations to further reduce energy consumption. Experimental results show that the proposed multiplier can achieve 59 %, 71 %, 73 %, and 82 % energy saving under 0.1 %, 1 %, 5 %, and 11 % accuracy loss, respectively, for the RGB-to-YUV & YUV-to-RGB conversion when compared to the conventional IEEE single-precision multiplier. In addition, the results also exhibit that the proposed multiplier can obtain more energy reduction than previous multiple-precision iterative FP multipliers.     

An Energy-Efficient BTB Lookup Scheme for Embedded Processors

In this brief, we propose an energy-efficient branch target buffer (BTB) lookup scheme for the embedded processors. Unlike the traditional scheme in which the BTB has to be looked up every instruction fetch, in our design, the BTB is only looked up when the instruction is likely to be a taken branch. By dynamically profiling the taken traces during program execution, the new scheme can achieve the goal of one BTB lookup per taken trace. The experimental results show that, by filtering out the redundant lookups, our design can reduce the total processor energy consumption by about 5.24% on average for the MediaBench applications.     

高能效系统的功耗优化技术

本本将叙述了各种系统选择方案及其对系统功耗的影响,全面介绍了处理器电源管理功能,并讨论总系统功耗的一些重要促进因素。本文网络版地址：http：//www.eepw.com.cn/article/164395.htm     

Energy-Efficient Power Allocation for Multi-user Single-DF-Relay Networks

Wireless Personal Communications - In wireless relay networks, energy efficiency not only affects the lifetime of mobile terminals, but also is a promising way to realize high-rate green...     

一种并行内建自诊断测试嵌入式SRAM方案

本文提出了具有自诊断功能的位定向MARCH-TB算法和字定向MARCH-TBW算法，并且在这两个算法的基础上提出并行测试结构来实现了嵌入式内存的测试和诊断。实验结果表明，此测试算法具有故障覆盖率高，诊断故障能力强，测试需要的时间少等优点。     

一种适用于超低功耗MCU的振荡器设计

提出并设计了一种新型低速振荡器,利用MCU电路内部的主时钟对低速时钟进行测试并且自校准,在几乎不增加功耗的前提下可以大大提高低速振荡器的精度和稳定性。与常规的低速振荡器相比,该结构具有功耗低、精度高、稳定性好的优点。仿真结果表明,此电路结构符合设计预期。     

用于数字通信接口的稳健且超低功耗的隔离

在线座谈（Online Seminar）是中电网于2000年推出的创新服务,通过＂视频演示＋专家解说＋在线问答＂三位一体相结合的形式,充分发挥网络平台的便捷性,实现了先进半导体技术提供商与系统设计工程师的实时互动交流,其形式和内容都广受电子行业工程师的好评。本刊每期将挑选一些精华内容整理成文,以飨读者。欲了解更多、更详细的内容,敬请登录http：//seminar.eccn.com。     

Ultra-Low Power Truly Random Number Generator for RFID Tag

This paper proposes low power, low voltage Truly Random Number Generators (TRNG) for Electrical Product Code (EPC Generation 2 Radio Frequency Identification (RFID) tag. Design considerations and trade-offs among randomicity, chip area and power consumption are analyzed according to the special requirements of Gen2 RFID tag. The proposed TRNG circuits consist of an analog random seed generator which uses the oscillator sampling mechanism, and Linear Feedback Shift Registers for post digital processing. These TRNG are implemented in SMIC 0.18 μm CMOS process. And their randomicity performances are verified by the FIPS 140-2 standard for security. One of the TRNG circuits outputs a random bit series at a speed of 40 kHz. Its power consumption is 1.04 μW and chip area is 0.05 mm². The other one has a bit rate at 48 kHz. It has a power consumption of 2.6 μW and chip area of 0.018 mm². The features of low power and small chip area in these TRNG circuits provide a good choice to solve the security and privacy problems in RFID systems.     

A Novel Electrically Tunable RF Inductor With Ultra-Low Power Consumption

In this study, we propose for the first time an electrically and continuously tunable RF inductor using grounded metal oxide semiconductor (MOS) transistor as a control device. By adjusting the output resistance of the grounded MOSFET, the ground-return current can lead to a significant variation in series inductance. This proposed inductor structure was implemented in a standard CMOS process and characterized up to 30 GHz, which demonstrates maximum inductance variations of 32% and 58% at 5.8 and 18 GHz, respectively. The dc power consumption of the proposed design is kept within 50 muW over the entire tuning range.     

多载波超密集网络的抗干扰分布式节能功率分配

该文研究多载波超密集网络(UDN)上行链路能效最优功率分配方案,基于非合作博弈论提出一种抗干扰分布式功率分配方案,使每个小区独立优化能效的同时抑制邻小区干扰.由于最大传输功率和QoS约束下的能效函数具有不易解决的非凸特性,且小小区间存在严重干扰.针对以上挑战,该文在最佳响应过程中设计了一种高精度低复杂度的阶梯注水算法,基于该算法利用干扰信道增益提出了一种多用户抗干扰功率分配算法.仿真结果和数值分析表明该算法运算复杂度低,且能在保证系统频谱效率的同时大幅度提升系统能效.     

Energy-Efficient Power Allocation for IoT Devices in CR-NOMA Networks

Non-orthogonal multiple access is a promising technique to meet the harsh requirements for the internet of things devices in cognitive radio networks.To improve the energy efficiency(EE)of the unlicensed secondary users(SU),a power allocation(PA)algorithm with polynomial complexity is investigated.We first establish the feasible range of power consumption ratio using Karush-Kuhn-Tucker optimality conditions to support each SU’s minimum quality of service and the effectiveness of successive interference cancellation.Then,we formulate the EE optimization problem considering the total transmit power requirements which leads to a non-convex fractional programming problem.To efficiently solve the problem,we divide it into an inner-layer and outer-layer optimization sub-problems.The inner-layer optimization which is formulated to maximize the sub-carrier PA coefficients can be transformed into the difference of convex programming by using the first-order Taylor expansion.Based on the solution of the inner-layer optimization sub-problem,the concave-convex fractional programming problem of the outer-layer optimization sub-problem may be converted into the Lagrangian relaxation model employing the Dinkelbach algorithm.Simulation results demonstrate that the proposed algorithm has a faster convergence speed than the simulated annealing algorithm,while the average system EE loss is only less than 2%.     

A Flexible Loss-Minimizing and Stress-Sharing Switch Cell for Power Converters

A switch cell named split-cell for power converters is proposed. Basically it is composed of two split bridge cells with identical power ratings. Two small resonant inductors are introduced to enable zero-voltage-switching (ZVS) operation of the split-cell. An external snubber capacitor can also be employed to further reduce turn-off losses of all the switches. With flexible and smooth mode-changing operation, the two internal bridge cells can perfectly share the stresses. Simulations and experiments have been conducted. The results have verified the expected performance for the split-cell. The split-cell can be used in high power and high frequency applications to reduce system losses, stresses, and improve reliability.     

Wireless Power Transfer and In-Vehicle Networking Integration for Energy-Efficient Electric Vehicles

This paper presents the wireless power transfer (WPT) technology based on inductive coupling and the design challenges of a hybrid energy harvester (EH) circuit as a promising solution to promote the energy efficiency of the electric vehicles (EVs). The design methodologies of ultra-low power (ULP) electronic module based on low leakage conditioning and processing device are detailed based on nanoscale transistor technology so that the WPT and hybrid EH can be implemented for self-powered devices in EVs. Moreover, in-vehicle network design verification based on a new power-aware behavioral model formulation and extraction for high-speed and ULP transceivers that enables the transient prediction of power and ground currents and voltages when multiple drivers are simultaneously switching for signal-power integrity evaluation. The derivation of the proposed model is based on the analysis and extension of the input/output buffer information specification (IBIS). The analysis of the previous IBIS and Mpilog modeling approaches is followed by a new model formulation along with a well-designed characterization and parametric extraction procedure.     

面向移动嵌入式终端的柔性人机界面模型

文章提出一个面向移动嵌入式终端的柔性人机界面模型--FHCIM.该模型首先对柔性人机界面的控件、参数以及动作进行了形式化抽象描述,然后在给定的柔性人机界面标记集合的基础上,使用该自定义的标记构造了人机界面的具体描述.随后,将人机界面的具体描述送入柔性人机界面显示模块,根据标记描述的控件属性,生成相应的对象并显示,并在相应动作的触发下,获得所需信息.最后给出了一个移动嵌入式终端的柔性人机界面实现的具体实例.     

TA-MAC：一种流量感知的低能耗传感器网络MAC协议

提出一种流量感知的信道访问控制协议TA-MAC.其核心思想是通过引入自适应机制来适应流量变化,根据负载的大小动态调整侦听期的实际长度,有效减小了空闲侦听.仿真结果表明,TA-MAC在满足保持丢包率为零,只轻微增加时延的情况下,显著降低了能耗.     

Flexible System LSI for Embedded Systems and Its Optimization Techniques

In this paper, we propose a chip architecture and design techniques to simultaneously reduce both the chip cost and power consumption of system-on-a-chip (SOCs). The chip cost of SOCs consists of the design cost, the mask cost, the fabrication cost, the package cost, and the test cost. In case that the production volume of one design is large, the fabrication cost becomes relatively larger than other costs. The minimization of the fabrication cost by shrinking the chip area has been the main problem to reduce the chip cost. SOCs are not always mass-produced and their design and the mask costs are dominant. We need new design criteria and a new design methodology for SOCs whose production volume is small. Our major contribution is a proposal of a design methodology based on new criteria suitable for SOC design. In our methodology, system designers use a pre-fabricated chip, called Flexible System LSI (FlexSys) chip, which consists of a processor, memories, and other cores specific to an application domain. At the fabrication phase, the power supply for unused parts of the FlexSys chip is cut off using a few additional masks which are designed for a specific application. This leads the reduction of wasteful power consumed by circuits which do not essentially contribute to the computation of the application. Since the basic die of the FlexSys is fabricated as a general purpose product, we can reduce the cost of the dies drastically. Experimental results show that about 30% power reduction can be achieved without performance loss by reducing the wasteful power consumption.