共查询到20条相似文献,搜索用时 46 毫秒
1.
Vikram Iyengar Krishnendu Chakrabarty Erik Jan Marinissen 《Journal of Electronic Testing》2002,18(2):213-230
Test access mechanisms (TAMs) and test wrappers are integral parts of a system-on-chip (SOC) test architecture. Prior research has concentrated on only one aspect of the TAM/wrapper design problem at a time, i.e., either optimizing the TAMs for a set of pre-designed wrappers, or optimizing the wrapper for a given TAM width. In this paper, we address a more general problem, that of carrying out TAM design and wrapper optimization in conjunction. We present an efficient algorithm to construct wrappers that reduce the testing time for cores. Our wrapper design algorithm improves on earlier approaches by also reducing the TAM width required to achieve these lower testing times. We present new mathematical models for TAM optimization that use the core testing time values calculated by our wrapper design algorithm. We further present a new enumerative method for TAM optimization that reduces execution time significantly when the number of TAMs being designed is small. Experimental results are presented for an academic SOC as well as an industrial SOC. 相似文献
2.
A modify wrapper/test access mechanism(TAM) structure is described to explore the maximal potential capacity of TAM, named “IP cores resource multiplexing(IPRM)”, reducing test application time for DVFS-based multicore System-on-Chips(MSoCs). The IPRM core wrappers, different from standard wrappers, enable to isolated core wrapper resource again to store test data for embedded cores under test. An integer linear programming (ILP) formulation with IPRM wrapper is proposed to improve multi-site test. Experimental results of the ITC’02 SoC Benchmark show that IPRM core wrapper reduces the burdens on ATE effectively, and can reduce the test application time by 10–50%. 相似文献
3.
System-on-chip test scheduling with reconfigurable core wrappers 总被引:1,自引:0,他引:1
Larsson E. Fujiwara H. 《Very Large Scale Integration (VLSI) Systems, IEEE Transactions on》2006,14(3):305-309
The problem with increasing test application time for testing core-based system-on-chip (SOC) designs is addressed with test architecture design and test scheduling. The scan-chains at each core are configured into a set of wrapper-chains, which by a core wrapper are connected to the test access mechanism (TAM), and the tests are scheduled in such a way that the test time is minimized. In this paper, we make use of reconfigurable core wrappers that, in contrast to standard wrappers, can dynamically change (reconfigure) the number of wrapper-chains during test application. We show that by using reconfigurable wrappers the test scheduling problem is equivalent to independent job scheduling on identical machines, and we make use of an existing preemptive scheduling algorithm that produces an optimal solution in linear time (O(n); n is the number of tests). We also show that the problem can be solved without preemption, and we extend the algorithm to handle: 1) test conflicts due to interconnection tests and 2) cases when the test time of a core limits an optimal usage of the TAM. The overhead in logic is given by the number of configurations, and we show that the upper-bound is three configurations per core. We compare the proposed approach with the existing technique and show, in comparison, that our technique is 2% less from lower bound. 相似文献
4.
Sandeep Koranne 《Journal of Electronic Testing》2002,18(4-5):415-434
In this paper a mathematical formulation and an efficient solution, of the embedded core-based system-on-chip (SOC) test scheduling problem (ECTSP) is presented. The ECTSP can be stated as follows; given a chip with N
C cores each having a test T
i; where T
i takes time
to execute on a test access mechanism (TAM) of width w
j, and a constraint W on the number of top-level test pins; calculate the TAM assignment vector and the schedule for each test T
i, such that the completion time of the full chip test is minimized. All existing approaches have solved the ECTSP by solving the TAM partition and scheduling problem sequentially. In this paper we present an unified approach to solve the ECTSP. We present the first report of a design of reconfigurable core wrapper which allows for a dynamic change in the width of the test access mechanism (TAM) executing a core test. An automatic procedure for the creation of DfT hardware required for reconfiguration using a graph theoretic representation of core wrappers is also presented. For the case of reconfigurable wrappers, efficient algorithms to compute the schedule are presented based upon some recent results in the field of malleable task scheduling. Cases in which the degree of reconfigurability are constrained are considered; the case when only a single core can have reconfigurable wrapper, a schedule with zero TAM idle time can be found in time O(N
C(N
C + W)lgW), and the case when only 2 different wrapper configurations are allowed can be solved in time O(N
C
3). Comparison with existing results on benchmark SOCs show that our algorithms outperform state-of-art ILP formulations not only in schedule makespan, but also significantly reduce computation time. 相似文献
5.
Dan Zhao Yi Wang 《Very Large Scale Integration (VLSI) Systems, IEEE Transactions on》2008,16(8):1046-1057
The rapid migration to nanometer design processes has brought an unprecedented level of integration by allowing system designers to pack a wide variety of functionalities on-chip, namely, systems-on-a-chip (SoCs). In the meantime, electronic testing becomes an enabling technology for this SoC paradigm, since the integration of various core tests is a big challenge, and has revealed a widening gap between design and manufacturing. In particular, the increasing complexity and density of nanometer SoCs have led to the problem of visibility and accessibility in testing. In this paper, we propose an integrated wireless test framework to resolve the acerbated core accessibility problem and to eliminate the incompatibility between the existing SoC test strategies and the next generation billion-transistor SoC specification. Under such a test strategy, the intra-chip wireless links form the wireless test access mechanism (TAM) to transport test data chip-wide. We present a self-configurable multi-hop wireless test micronetwork, dubbed MTNet, with simple and efficient data transmission protocols, and develop a system level design-for-testability structure. Consequently, we propose a geographic routing algorithm to find the test access paths for the deeply embedded cores and a path driven test scheduling algorithm to design and integrate the MTNet-based SoC test access architecture. Extensive simulation study show the feasibility and applicability of MTNet. 相似文献
6.
Arkan Abdulrahman Author Vitae Spyros Tragoudas Author Vitae 《Integration, the VLSI Journal》2008,41(4):459-473
A function-based automatic test pattern generation (ATPG) tool for embedded core testing is presented that reduces test cost and considers test power dissipation of system-on-chip (SoC). Cores are tested concurrently with the use of test functions, as opposed to simple patterns, and by I/O pin allocation on the test access mechanism (TAM) during a compact ATPG process. Turnaround time benefits from pre-existing test vectors, or test functions supplied by the provider of each core. The presented method also targets low-power dissipation by considering the switching activity on the SoC inputs. Experimental results show a significant reduction in the test application time due to the achieved level of concurrency. 相似文献
7.
Sehgal A. Ozev S. Chakrabarty K. 《Very Large Scale Integration (VLSI) Systems, IEEE Transactions on》2006,14(3):292-304
Many system-on-chips (SOCs) today contain both digital- and analog-embedded cores. Even though the test cost for such mixed-signal SOCs is significantly higher than that for digital SOCs, most prior research in this area has focused exclusively on digital cores. We propose a low-cost test development methodology for mixed-signal SOCs that allows the analog and digital cores to be tested in a unified manner, thereby minimizing the overall test cost. The analog cores in the SOC are wrapped such that they can be accessed using a digital test access mechanism (TAM). We evaluate the impact of the use of analog test wrappers on area overhead and test time. To reduce area overhead, we present an analog test wrapper optimization technique, which is then combined with TAM optimization in a cost-oriented heuristic approach for test scheduling. We also demonstrate the feasibility of using analog wrappers by presenting transistor-level simulations for an analog wrapper and a representative core. We present experimental results for three SOCs from the ITC '02 test benchmarks that have been augmented with three analog cores: an I-Q transmit path pair and an audio CODEC path used in cellular phone applications. 相似文献
8.
CAS-BUS: A Test Access Mechanism and a Toolbox Environment for Core-Based System Chip Testing 总被引:2,自引:0,他引:2
As System on a Chip (SoC) testing faces new challenges, some new test architectures must be developed. This paper describes a Test Access Mechanism (TAM) named CAS-BUS that solves some of the new problems the test industry has to deal with. This TAM is scalable, flexible and dynamically reconfigurable. The CAS-BUS architecture is compatible with the IEEE P1500 standard proposal in its current state of development, and is controlled by Boundary Scan features.This basic CAS-BUS architecture has been extended with two independent variants. The first extension has been designed in order to manage SoC made up with both wrapped cores and non wrapped cores with Boundray Scan features. The second deals with a test pin expansion method in order to solve the I/O bandwidth problem. The proposed solution is based on a new compression/decompression mechanism which provides significant results in case of non correlated test patterns processing. This solution avoids TAM performance degradation.These test architectures are based on the CAS-BUS TAM and allow trade-offs to optimize both test time and area overhead. A tool-box environment is provided, in order to automatically generate the needed component to build the chosen SoC test architecture. 相似文献
9.
基于扫描链技术的SoC芯片测试可产生比正常使用模式下更大的功耗,这将会对器件可靠性产生不利影响,故在测试时需要将芯片测试功耗控制在允许峰值功耗之下.文中采用蚁群优化思路设计SoC测试调度算法,用于在峰值功耗和TAM总线最大宽度约束下降低SoC测试时间.实验结果表明,本方法优于先前已发表的相关方法. 相似文献
10.
As the system‐on‐chip (SoC) design becomes more complex, the test costs are increasing. One of the main obstacles of a test cost reduction is the limited number of test channels of the ATE while the number of pins in the design increases. To overcome this problem, a new test architecture using a channel sharing compliant with IEEE Standard 1149.1 and 1500 is proposed. It can significantly reduce the pin count for testing a SoC design. The test input data is transmitted using a test access mechanism composed of only input pins. A single test data output pin is used to measure the sink values. The experimental results show that the proposed architecture not only increases the number of sites to be tested simultaneously, but also reduces the test time. In addition, the yield loss owing to the proven contact problems can be reduced. Using the new architecture, it is possible to achieve a large test time and cost reduction for complex SoC designs with negligible design and test overheads. 相似文献
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13.
System-on-chip (SoC) integrated circuits are designed and fabricated with multiple levels of hierarchy. However, most previous
works on wrapper design, test access mechanism optimization and test scheduling did not take care of the hierarchy properly,
thus the corresponding test schedules were often invalid for SoCs with hierarchical cores. We propose a low-area wrapper cell
design which can treat SoCs with hierarchy properly and allows simultaneous testing of parent and child cores. The proposed
cell uses 13%∼23% less area than a recently proposed cell design in equivalent gate count. As a result we achieve up to 21%
area reduction for hierarchical ITC ’02 SoCs compared to the most recently proposed designs. 相似文献
14.
This paper describes the implementation of a digital audio effect system‐on‐a‐chip (SoC), which integrates an embedded digital signal processor (DSP) core, audio codec intellectual property, a number of peripheral blocks, and various audio effect algorithms. The audio effect SoC is developed using a software and hardware co‐design method. In the design of the SoC, the embedded DSP and some dedicated hardware blocks are developed as a hardware design, while the audio effect algorithms are realized using a software centric method. Most of the audio effect algorithms are implemented using a C code with primitive functions that run on the embedded DSP, while the equalization effect, which requires a large amount of computation, is implemented using a dedicated hardware block with high flexibility. For the optimized implementation of audio effects, we exploit the primitive functions of the embedded DSP compiler, which is a very efficient way to reduce the code size and computation. The audio effect SoC was fabricated using a 0.18 μm CMOS process and evaluated successfully on a real‐time test board. 相似文献
15.
16.
《Very Large Scale Integration (VLSI) Systems, IEEE Transactions on》2009,17(8):1152-1156
17.
The use of 3D-IC technology has become quite widespread in designing core-based systems-on-chip (SoCs). Concomitantly, testing of cores and inter-layer through-silicon-vias (TSVs) spanning through different layers of 3D chips has become an important problem in the manufacturing cycle. Testing 3D-SoCs is more challenging compared to their 2D counterparts because of the complexity of their design and power management issues. Also, the test procedure demands substantially more power than what is required in the normal functional mode, and hence, stringent thermal constraints during test need to be fulfilled to safeguard future performance and reliability of the chip. Since the overall 3D infrastructure depends on routing layer assignments, core allocation, and the geometry of TSV locations, these parameters should be given due consideration while designing the test-access-mechanism (TAM) that aims for minimizing overall test time satisfying power and TSV constraints. In this paper, we present a three-stage algorithm for reducing the test time in automated post-bond core-based 3D-SoCs, under a set of given constraints on test power, TAM-width, and the number of available TSVs. The proposed algorithm, when run on several ITC-02 SoC benchmarks, outperforms the algorithms presented in earlier work with respect to CPU-time, and additionally, reduces test time in many instances. 相似文献
18.
Petre F. Leus G. Deneire L. Engels M. Moonen M. Hugo De Man 《Selected Areas in Communications, IEEE Journal on》2003,21(3):350-361
The combination of space-time block coding (STBC) and direct-sequence code-division multiple access (DS-CDMA) has the potential to increase the performance of multiple users in a cellular network. However, if not carefully designed, the resulting transmission scheme suffers from increased multiuser interference (MUI), which dramatically deteriorates the performance. To tackle this MUI problem in the downlink, we combine two specific DS-CDMA and STBC techniques, namely single-carrier block transmission (SCBT) DS-CDMA and time-reversal STBC. The resulting transmission scheme allows for deterministic maximum-likelihood (ML) user separation through low-complexity code-matched filtering, as well as deterministic ML transmit stream separation through linear processing. Moreover, it can achieve maximum diversity gains of N/sub T/N/sub R/(L+1) for every user in the system, irrespective of the system load, where N/sub T/ is the number of transmit antennas, N/sub R/ the number of receive antennas, and L the order of the underlying multipath channels. In addition, it turns out that a low-complexity linear receiver based on frequency-domain equalization comes close to extracting the full diversity in reduced, as well as full load settings. In this perspective, we also develop two (recursive) least squares methods for direct equalizer design. Simulation results demonstrate the outstanding performance of the proposed transceiver compared to competing alternatives. 相似文献
19.
软硬件协同验证是系统芯片设计的重要组成部分。针对基于32 Bit CPU核的某控制系统芯片的具体要求,提出了一种系统芯片软硬件协同验证策略,构建了一个软硬件协同验证环境。该环境利用处理器内核模型支持内核指令集的特性运行功能测试程序,实现SoC软硬件的同步调试,并能够快速定位软硬件的仿真错误点,有效提高了仿真效率。该SoC软硬件协同验证环境完成了设计目的,并对其他系统芯片设计具有一定的参考价值。 相似文献