p-Channel MOSFET's in LPCVD PolySilicon

p-channel MOSFET's have been fabricated in LPCVD polysilicon. A 5000-Å n⁺poly acts as the gate electrode on which a 500-Å thermal oxide is grown to act as the gate insulator. Then a 1500-Å LPCVD polysilicon layer is deposited at 620°C and is subsequently boron doped to form the conductive channel. Devices with channel length as small as 2 µm show well-behaved transistor characteristics. The drive current and leakage current are as suitable for usage as load element in memory applications. At large gate voltages the accumulation hole mobility is 9 cm²/V.s. The drain-to-source breakdown voltage exceeds -20 V.     

Ga0.4In0.6As/Al0.55In0.45As pseudomorphic modulation-doped field-effect transistors

High-performance pseudomorphic Ga0.4In0.6As/ Al0.55In0.45As modulation-doped field-effect transistors (MODFET's) grown by MBE on InP have been fabricated and characterized. DC transconductances as high as 271, 227, and 197 mS/mm were obtained at 300K for 1.6-µm and 2.9-µm gate-length enhancement-mode and 2-µm depletion-mode devices, respectively. An average electron velocity as high as 2.36 × 10⁷cm/s has been inferred for the 1.6-µm devices, which is higher than previously reported values for 1-µm gate-length Ga0.47In0.53As/Al0.48In0.52As MODFET's. The higher bandgap Al0.55In0.45As pseudomorphic barrier also offers the advantages of a larger conduction-band discontinuity and a higher Schottky barrier height.     

Formation of TiN/TiSi2/p+-Si/n-Si by rapid thermal annealing (RTA) silicon implanted with boron through titanium

A low temperature method of fabricating conductive (3.5 Ω/ sq.) p⁺/n junction diodes possessing excellentI-Vcharacteristics with reverse-bias leakage less than -3 nA.cm^-2at -5 V is described. Single crystal n-type 〈100〉 Si is implanted with 60 keV¹¹B+through 0.028-µm thick sputtered Ti film. Rapid thermal annealing (RTA) in an N2ambient simultaneously forms a 0.36-µm deep p⁺/n junction and a 0.063-µm thick bilayer of TiN and TiSi2with a resistivity of 22 µΩ.cm. The electrical properties of these diodes are not degraded by annealing for 30 min at 500°C, suggesting that the outer layer of TiN is an effective diffusion barrier between TiSi2and Al.     

Rapid low-resistance interconnects by selective tungsten deposition on laser-direct-written polysilicon

Polysilicon interconnections were locally deposited on oxide-covered silicon wafers by pyrolysis of silane using a scanned Ar+-laser spot. The 2-µm-wide interconnects, written at scan speeds of 2.5 mm/s, have a 500-µΩ.cm resistivity and exhibit low contact resistance to underlying Al and Al/Si structures. These films were subsequently reacted with WF6vapor to form a tungsten-silicon composite interconnect by the silicon reduction of WF6. Electrical tests show that the conductivity of 0.4-µm-thick conductors is enhanced up to 20-fold, by formation of a surface metallic layer having conductivity characteristic of pure thin-film tungsten. Auger and Rutherford backscattering spectra (RBS) confirm the purity and selectivity of the surface tungsten layer formed at temperatures compatible with preexisting aluminum metallization. The tungsten-polysilicon composite interconnects have applications as rapidly written discretionary metallization for prototyping and in situ analysis of integrated circuits.     

Mo- and Ti-silicided low-resistance shallow junctions formed using the ion implantation through metal technique

Mo-and Ti-silicided junctions were formed using the ITM technique, which consists of ion implantation through metal (ITM) to induce metal-Si interface mixing and subsequent thermal annealing. Double ion implantation, using nondopant ions (Si or Ar) implantation for the metal-Si interface mixing and dopant ion (As or B) implantation for doping, has resulted in ultrashallow ( ≤ 0.1-µm) p⁺-n or n⁺-p junctions with ∼30-Ω sheet resistance for Mo-silicided junctions and ∼5.5-Ω sheet resistance for Ti-silicided junctions. The leakage current levels for the Mo-silicided n⁺-p junctions (0.1-µm junction depth) and the Mo-silicided p⁺-n junction (0.16-µm junction depth) are comparable to that for unsilicided n⁺-p junction with greater junction depth ( ∼0.25 µm).     

Monolithic microwave amplifiers formed by ion implantation into LEC gallium arsenide substrates

A fabrication procedure for broad-band monolithic power GaAs integrated circuits has been demonstrated which includes formation of via holes through the 100-µm-thick GaAs substrate. A selective implant of²⁹Si ions into the GaAs substrate is used to dope the FET channel region to 1.2 × 10¹⁷cm^-3. The ohmic contacts are AuGe/Ni/Pt and the gates are Ti/Pt/Au. A 1.5-µm-thick circuit pattern is achieved using metal rejection assited by chlorobenzene treatment of AZ1350J photoresist. Using undoped Czochralski wafers of GaAs pulled from a pyrolytic boron nitride crucible, integrated amplifiers have been produced which deliver 28 ± 0.7 dBm from 5.7 to 11 GHz. These chips are 2 mm × 4.75 mm × 0.1 mm thick.     

Hybrid IRCCD imaging array

A hybrid IRCCD for high background application has been successfully fabricated. The device consists of fifty Hg0.7Cd0.3Te detector diodes of 50-µm × 50-µm sensitive areas and a silicon CCD maltiplexer with input circuits on 40-µm centers having bucket background subtraction and blooming protection circuits. The noise-equivalent power (NEP) of the IRCCD is 5 × 10^-14W-Hz^-1/2at background photon flux level of 4 × 10¹⁵photons . cm^-2s^-1, integration time of 2 × 10^-5s, and clock frequency of 3 × 10⁶Hz. The noise source of the detector diodes limits the IRCCD performance. The IRCCD is also evaluated with the real-time raster-scanned thermal images displayed on a CRT monitor. Two-dimensional images are generated by using a scanning mirror. A fixed-pattern noise is reduced by comparison of an object video to the reference video stored in a memory. A noise-equivalent temperature difference of the system is 0.6°C at a frame rate of 30 Hz. Instantaneous field of view is 1 mrad × 1 mrad and the field of view of the system is 12° × 5.7°.     

Formation of shallow p+-n junctions using boron-nitride solid diffusion source

Shallow p⁺-n junctions on the order of 0.1-µm deep have been fabricated using boron-nitride (BN) solid diffusion sources. The process combines the hydrogen-injection method and rapid thermal processing (RTP). Sheet resistivities, in ranges from 50 to 130 Ω/sq with junction depths from 0.1 to 0.19 µm, are possible in this technique. Diode characteristics of 0.11-µm junctions show low reverse leakage current, of the order of 10 nA/cm², indicating the possibility of this method to form PMOS source-drain contacts.     

Utilization of NiSi2as an interconnect material for VLSI

The applicability of NiSi2as an interconnect material was investigated using narrow (5 µm- × 2600-µm) lines. 2500-Å-thick silicide lines were thermally oxidized to form a passivation layer of SiO2for the next metallization level. Isolation of more than 50 V for 2200-Å SiO2is achieved. The interconnect resistivity following the oxidation is 1.2-1.4 Ω. The maximum current capability of the lines was found to be > 5 × 10⁶A/cm²and their stability under prolonged high current densities was demonstrated. We propose a scheme to increase the local metallization-level density using NiSi2as an interconnect.     

Characteristics of a 1.2-µm CMOS technology fabricated on an RF-heated zone-melting recrystallized SOI

0.7-5-µm CMOSFET's were fabricated on SOI which was recrystallized using an RF-heated zone-melting recrystallization (RFZMR) method. The leakage currents of n-channel MOSFET's having gate lengths between 5- and 0.7-µm range between 10^-14and 10^-12A/µm and show no dependence on channel length. Those of the p-channel MOSFET's were 10^-14-10^-12A/µm when the gate lengths were longer than 1.2 µm, and increased when the gate lengths were shorter than 1.0 µm. The propagation delay time of the CMOSFET inverter was 0.13 ns per stage at a supply voltage of 3.5 V.     

Limitations on injection efficiency in power devices

In this paper the mechanisms of bandgap narrowing, Shockley-Read-Hall (SRH) recombination, Auger recombination, and carrier-carrier and carrier-lattice scattering are included in an exact one-dimensional model of a bipolar transistor. The transistor is used as a vehicle for studying the relative importance of each of these phenomena in determining emitter efficiency in devices with emitter junction depths of 1 µm to 8 µm. It is shown that bandgap narrowing is the dominant influence for devices with shallow emitters of 2 µm or less and that SRH recombination dominates for emitter depths greater than 4 µm. Calculations are also presented showing the effects of the emitter surface concentration and high-level injection on the current gain for devices with emitter junction depths of 1 µm to 8 µm. It is shown that there is an optimum surface concentration of 5 × 10¹⁹cm^-3for the 1-µm emitter depth but no optimum under 10²¹cm^-3for devices with emitter depths greater than 4 µm.     

Electron beam direct writing technology applied to 512 kbit ROM with 1 µm geometry

A 512 kbit read-only memory (ROM) to store Chinese ideographs has been fabricated using variable-shaped electron beam and dry-etching lithography. 1.0-µm minimum line width was used to delineate device area spacings smaller than those obtained with conventional design rules using photoimaging techniques. SiO2, Si3N4, and polysilicon etchings were accomplished by reactive sputter techniques with CF4+ H2and CCl3F gases using negative electron beam resist PGMA and positive resist AZ-2400. Al etching was carried out by plasma with CCl4gas using negative electron beam resist NER-1. The alignment marks detectability and their locating accuracy were improved by properly using the basis arithmetic operations, subtraction and summation, in backscatter signal processings. 6.6 mm × 8.9 mm chip-by-chip alignment yielded about 0.2-µm level-to-level registration accuracy. Memory cell size and chip size are 5.2 µm × 8.4 µm and 6.6 mm × 8.9 mm, respectively; access time and power dissipation are 400 ns and 800 mW, respectively.     

Sensitivity measurement of a 10.6-µm parametric upconverter

The sensitivity of a parametric upconverter for the detection of 10.6-µm radiation was measured. 10.6-µm radiation was mixed with the 1.06 µm beam of an Nd :YAG laser in properly oriented single-crystal proustite. The upconverted output at 0.967 µm was then detected by an S-1 photomultiplier tube. NEP of 1.1×10^-9W . s^½was measured.     

0.4-µm gate-length devices fabricated by contrast-enhanced lithography

This letter describes the fabrication of submicrometer polysilicon-gate MOS devices by an advanced optical process called contrast enhancement. Functional devices having gate lengths as small as 0.4 µm were fabricated with this process. Contrast-enhanced lithography (CEL) allows usable photoresist patterns to be fabricated at smaller dimensions than is possible with conventional resist. The simultaneous replication of mask dimensions for isolated lines at 0.35 µm and above was achieved in this work using a single exposure on an Optimetrix 10:1 DSW system. Contrast enhancement has been applied to the fabrication of n-channel MOS devices having gate lengths from 0.4 to 1.5 µm in steps of 0.1 µm. Long-channel devices were also fabricated. The transconductance of the 0.4-µm devices is 40 mS/mm at Vds= 5 V. Threshold voltages (Vds= 0) are nearly independent of gate length, ranging from 1.21 to 1.31 V over the 7.5- to 0.4-µm range in gate length. The effective mobility for long-channel devices is 430 cm²/V.s.     

Junction-current-confinement planar light-emitting diodes and optical coupling into large-core diameter fibers using lenses

High-radiance AlGaAs-GaAs double-heterostructure light-emitting diodes utilizing junction current confinement are described. Diode resistance and junction ideality factor are investigated as a function of emission diameters from 10 to 75 µm. Near-field intensity profiles indicate tight current confinement over the full range of emission diameters. Rise-time measurements are consistent with a simple carrier lifetime model for >25-µm emission diameters. An effective radiative-recombination constant, B = 1.5(±0.5) × 10-¹⁰cm³/s is deduced from the rise-time data and model. Peak wavelength and spectral width data are discussed in terms of junction current density and temperature. With decreasing emission diameter, the optical coupling efficiencies into 100- and 200-µm core diam high-numerical-aperture fibers increased from 10 to 25 percent and 25 to 50 percent, respectivley, using spherical glass lenses.     

GaInAsP/InP fast, high-radiance, 1.05-1.3-µm wavelength LED's with efficient lens coupling to small numerical aperture Silica optical fibers

Power levels up to 100 µW have been launched from GaInAsP LED's with 14-µm-diameter emitting regions into low-loss small numerical aperture (NA) silica fibers at a dc drive level of only 25 mA. A maximum launch power of 206 µW at 100-mA dc was obtained from slightly larger devices. The high coupling efficiency was achieved using truncated spheres of Ti2O3:SiO2glass as microlenses. Gains over the butt coupled case exceeded a factor of twelve for the small-area devices. The high operating current densities (2-20 kA/cm²) for the small-area devices resulted in modulation bandwidths extending to beyond 300 MHz (-3 dB optical). The surface-emitting LED's showed an enhanced performance over edge-emitting LED's fabricated from similar material. Linewidths of the devices, which were prepared by liquid-phase epitaxy with step followed by ramp cooling, were approximately 3 kT. Even with the relatively broad linewidth, material dispersion limits in silica fibers exceeding 1 GHz . km around 1.3 µm are predicted. These devices are suitable for long-haul, wide-bandwidth fiber links operating in the 1.3-µm window.     

Rapid isothermal processing with electron beams of small-geometry CMOS devices

Small-geometry CMOS devices with shallow n⁺and p⁺source-drain regions formed by arsenic and boron difluoride ion implantation, respectively, have been studied. Activation of implants was produced by a single rapid isothermal anneal using the multiple-scan electron-beam approach. Transistor and circuit simulations were used to determine a requirement for the source-drain region of a sheet resistance of < 100 Ω/square with a junction depth of less than 0.2 µm in 1-µm channel length devices. These values cannot be obtained by conventional furnace annealing at 950°C, but can be achieved by a single heat treatment With an e-beam. E-beam-annealed devices have a reverse-bias junction leakage similar to furnace-annealed control samples, and show improvements in short-channel effects such as short-channel threshold voltage shifts and punchthrough, without introducing other deleterious effects.     

Electrical properties of tellurium thin films

Semiconducting properties of evaporated tellurium thin films, in the thickness range of 100 to 400 Å, are studied and correlated with observed structural properties. It is found that less-than-monolayer gold films can act as nucleation sites and stimulate the growth of large crystallites in deposited Te films. The Au-nucleated Te films are preferentially oriented with the c axis in the substrate plane and have crystallite diameters ranging from 2 to 5 µm. Hall mobilities as high as 250 cm²/V ċ s are observed in 400-Å Au-nucleated films with 5-µm crystallites. These large-grain films exhibit a temperature dependence for mobility of the form µ ∼ T^3/2between 85°K and 250°K, while the carrier concentrations in the films do not change appreciably with temperature. Transconductances greater than 1000 µmhos are achieved for Au-nucleated Te thin-film transistors with 3-mil channels (operating with a saturated drain current of 1 mA). Several devices exhibit field-effect mobilities greater than 100 cm²/V ċ s, a value consistent with the observed Hall mobilities for similar films. Transconductance measurements indicate that Te thin-film transistor (TFT) instabilities result primarily from hole trapping at the Te-insulator interface. It is possible to alter the threshold voltage of Te TFTs by applying a gate bias at room temperature. Improved stability (changes in V0less than 50 mV in 1 h) is observed at 77°K. From the observed changes in threshold, a lower limit of the trapping-state density at the surface is inferred to be 5×10¹²traps/cm². The surface-state density at the Te-SiO interface is estimated to be less than 6×10¹²surface states/cm²ċ eV as determined from capacitance and conductance measurements.     

A high-current drivability i-AlGaAs/n-GaAs doped-channel MIS-Like FET (DMT)

A high-current drivability doped-channel MIS-like FET (DMT) has been proposed. The DMT takes advantage of high saturation current with large transconductance and high breakdown voltage, in regard to its operating principle. The fabricated 0.5-µm gate DMT showed 310-mS/mm (410-mS/mm) transconductance and 650-mA/mm (800-mA/mm) maximum saturation current at room temperature (at 77 K). Output current values are about three or four times those for conventional two-dimensional electron gas (2DEG) FET's. Estimated average electron velocity is rather high, 1.5 × 10⁷cm/s (2 × 10⁷cm/s) at room temperature (77 K). In addition,f_{max}is as high as 41 GHz. fTis 45 GHz, which is the best data ever reported in 0.5-µm gate FET's.     

Facet-coated graded-index separate-confinement-heterostructure single-quantum-well lasers having low degradation rates (<1 percent/kh) at 70°C

The results of accelerated life testing of single-quantum-well (QW) lasers having graded-index (GRIN) separate-confinement heterostructure (SCH) active regions are reported. These results are the first to show that lasers grown by MOCVD can have low degradation rates (<1 percent/kh) at 70°C and are also the first light-emitting lifetime data for GRIN-SCH quantum-well lasers. The laser structures were grown by metalorganic chemical vapor deposition (MOCVD) at atmospheric pressure using an uninterrupted growth sequence. Shallow proton-bombarded 5-µm × 250-µm stripe-geometry lasers were fabricated from these wafers and lasers with and without Al2O3facet coatings were life tested at 70°C and 5 mW per mirrors facet. Facet-coated lasers have lived longer than 1100 h with degradation rates as low as 0.5 percent/kh.