A Low-Power 5-Gb/s Current-Mode LVDS Output Driver and Receiver with Active Termination

In this work, a novel circuit topology for a Low-Voltage Differential Signaling (LVDS) output driver with reduced power consumption is proposed. Also, a low-signal current version of the LVDS driver working with lower supply voltage is proposed along with a compatible differential current-mode receiver. Both the drivers and the receiver feature active-terminated ports that eliminate the need for a dedicated passive terminator for matching. An asymmetric impedance network on the output side of the driver selectively eliminates any reflections coming from the channel while providing a high output impedance to the outgoing signal. For a target signal swing at the receiver input, the proposed termination scheme helps to reduce the driver signal current to up to a third of the current required by a conventional LVDS driver using a passive termination at the output. The asymmetric impedance network consists of a scaled-down replica driver that drives a common drain stage acting as the load for the main driver. The proposed driver topology meeting all LVDS specifications has been implemented in 3.3-V thick-gate CMOS technology. Simulation results show an achievable data rate of 5 Gb/s while transmitting over a 7.5-in FR4 PCB backplane trace for a target BER of 10⁻¹⁵, with power consumption equal to 17.8 mW, which is 25% less than a conventional LVDS driver with passive source end termination producing the same voltage swing at the receiver input. The low-current version of the driver has been implemented in 0.18-μm 1.8-V digital CMOS technology and shows similar performance over the same channel with a power consumption of 4.5 mW.     

Data Supply Voltage Reduction Scheme for Low‐Power AMOLED Displays

This paper demonstrates a new driving scheme that allows reducing the supply voltage of data drivers for low‐power active matrix organic light‐emitting diode (AMOLED) displays. The proposed technique drives down the data voltage range by 50%, which subsequently diminishes in the peak power consumption of data drivers at the full white pattern by 75%. Because the gate voltage of a driving thin film transistor covers the same range as a conventional driving scheme by means of a level‐shifting scheme, the low‐data supply scheme achieves the equivalent dynamic range of OLED currents. The average power consumption of data drivers is reduced by 60% over 24 test images, and power consumption is kept below 25%.     

Design of high speed LVDS transceiver ICs

The design of low-power LVDS(low voltage differential signaling) transceiver ICs is presented.The LVDS transmitter integrates a common-mode feedback control on chip,while a specially designed pre-charge circuit is proposed to improve the speed of the circuit,making the highest data rate up to 622 Mb/s.For the LVDS receiver design, the performance degradation issues are solved when handling the large input common mode voltages of the conventional LVDS receivers.In addition,the LVDS receiver also supports ...     

Equalization and pre-emphasis based LVDS transceiver

This work presents an area-efficient, low-power, high data rate low voltage differential signal (LVDS) transmitter and receiver with signal quality enhancing techniques. The proposed common mode feedback scheme significantly reduces the size of the LVDS transmitter by eliminating the use of area consuming passive resistor and capacitor used for close loop stability compensation. A preemphasis technique has been introduced to enhance the transmitter output’s signal quality without significantly increasing the power draw. On the receiver part, an equalization technique has also been introduced to further enhance signal quality, increases data rate and improved jitter with relatively low power consumption. The LVDS transmitter consumes 5.4 mA of current while driving an external 100 ohm resistor with an output voltage swing of 440 mV. The chip consumes an area of 0.044 mm². This LVDS receiver has an input common mode range from 0.1 to 1.6 V. It consumes 34 mW of power with a maximum data rate of 2 Gbps. It consumes an area of 0.147 mm² a jitter of 11.74 ps rms. A test chip is implemented using 0.18 μm CMOS process.     

Design and realization of 1.3?Gb/s off-chip transmission circuitry using 0.35?μm CMOS technology

Low-voltage-differential-signaling (LVDS) is one of the very popular technologies which simultaneously addresses low dynamic power consumption and high data rate transmission in modern high speed circuit applications. In this paper, system level integration design approach is applied to design LVDS transmitter featuring high off-chip data rate. Full wave electromagnetic simulation technique was adopted to accurately characterize possible couplings and parasitic effects induced from the off-chip components which then acted as the termination of the output circuitry. Common mode feedback was included to perform fine tuning on the offset leading to much higher overall precision. Meanwhile, generation of the controlled current and voltage across termination was guaranteed through the introduction of a constant transconductance bias network. The design was implemented using TSMC 3.3?V 0.35???m CMOS technology with overall chip size of 0.923?mm². At a DC power consumption level of 29.4?mW, the LVDS transmitter exhibited an off-chip data rate of 1.3?Gb/s validated through measurements.     

A 3.1 to 5 GHz CMOS Transceiver for DS‐UWB Systems

This paper presents a direct‐conversion CMOS transceiver for fully digital DS‐UWB systems. The transceiver includes all of the radio building blocks, such as a T/R switch, a low noise amplifier, an I/Q demodulator, a low pass filter, a variable gain amplifier as a receiver, the same receiver blocks as a transmitter including a phase‐locked loop (PLL), and a voltage controlled oscillator (VCO). A single‐ended‐to‐differential converter is implemented in the down‐conversion mixer and a differential‐to‐single‐ended converter is implemented in the driver amplifier stage. The chip is fabricated on a 9.0 mm² die using standard 0.18 µm CMOS technology and a 64‐pin MicroLead Frame package. Experimental results show the total current consumption is 143 mA including the PLL and VCO. The chip has a 3.5 dB receiver gain flatness at the 660 MHz bandwidth. These results indicate that the architecture and circuits are adaptable to the implementation of a wideband, low‐power, and high‐speed wireless personal area network.     

SOA‐Integrated Dual‐Mode Laser and PIN‐Photodiode for Compact CW Terahertz System

We designed and fabricated a semiconductor optical amplifier‐integrated dual‐mode laser (SOA‐DML) as a compact and widely tunable continuous‐wave terahertz (CW THz) beat source, and a pin‐photodiode (pin‐PD) integrated with a log‐periodic planar antenna as a CW THz emitter. The SOA‐DML chip consists of two distributed feedback lasers, a phase section for a tunable beat source, an amplifier, and a tapered spot‐size converter for high output power and fiber‐coupling efficiency. The SOA‐DML module exhibits an output power of more than 15 dBm and clear four‐wave mixing throughout the entire tuning range. Using integrated micro‐heaters, we were able to tune the optical beat frequency from 380 GHz to 1,120 GHz. In addition, the effect of benzocyclobutene polymer in the antenna design of a pin‐PD was considered. Furthermore, a dual active photodiode (PD) for high output power was designed, resulting in a 1.7‐fold increase in efficiency compared with a single active PD at 220 GHz. Finally, herein we successfully show the feasibility of the CW THz system by demonstrating THz frequency‐domain spectroscopy of an α‐lactose pellet using the modularized SOA‐DML and a PD emitter.     

An Offset‐Compensated LVDS Receiver with Low‐Temperature Poly‐Si Thin Film Transistor

The poly‐Si thin film transistor (TFT) shows large variations in its characteristics due to the grain boundary of poly‐crystalline silicon. This results in unacceptably large input offset of low‐voltage differential signaling (LVDS) receivers. To cancel the large input offset of poly‐Si TFT LVDS receivers, a full‐digital offset compensation scheme has been developed and verified to be able to keep the input offset under 15 mV which is sufficiently small for LVDS signal receiving.     

A New Automatic Compensation Network for System‐on‐Chip Transceivers

This paper proposes a new automatic compensation network (ACN) for a system‐on‐chip (SoC) transceiver. We built a 5 GHz low noise amplifier (LNA) with an on‐chip ACN using 0.18 µm SiGe technology. This network is extremely useful for today's radio frequency (RF) integrated circuit devices in a complete RF transceiver environment. The network comprises an RF design‐for‐testability (DFT) circuit, capacitor mirror banks, and a digital signal processor. The RF DFT circuit consists of a test amplifier and RF peak detectors. The RF DFT circuit helps the network to provide DC output voltages, which makes the compensation network automatic. The proposed technique utilizes output DC voltage measurements and these measured values are translated into the LNA specifications such as input impedance, gain, and noise figure using the developed mathematical equations. The ACN automatically adjusts the performance of the 5 GHz LNA with the processor in the SoC transceiver when the LNA goes out of the normal range of operation. The ACN compensates abnormal operation due to unusual thermal variation or unusual process variation. The ACN is simple, inexpensive and suitable for a complete RF transceiver environment.     

High-Speed Single-Ended Parallel Link Based on Three-Level Differential Encoding

An encoding scheme for high-speed single-ended parallel transceiver system is presented. Compared to the 50% I/O pin utilization of the conventional differential encoding, the proposed system employs 3-level differential coding to increase the utilization to 75% and 93% using a group of four and six conductors, respectively. The proposed coding scheme also reduces the effects of inter-symbol interference (ISI), removes reference ambiguity, and reduces power line fluctuations at the transmitter side. Using simple encoder/decoder, the proposed scheme enables multiple drivers at the transmitter to recycle the same current, reducing power consumption. To validate the proposed system, a parallel link was designed in 0.18 mum CMOS process. The chip implements the coding algorithm over four conductors and achieves a data rate of 4.2 Gb/s/pin while dissipating 17.1 mW/Gb/s.     

A 2-Gbaud 0.7-V swing voltage-mode driver and on-chip terminatorfor high-speed NRZ data transmission

A large-swing, voltage-mode driver and an on-chip termination circuit are presented for high-speed nonreturn-to-zero (NRZ) data transmission through a copper cable. The proposed driver with active pull-up and pull-down can generate a 700-mV signal to deliver a 2 Gbaud serial NRZ data stream. Low output impedance offered by simple negative-feedback resistors alleviates the detrimental effect of the parasitic capacitance by supplying fast current impulses. A proposed on-chip termination circuit provides termination impedance to a mid-supply termination voltage with the benefit of reduced parasitic capacitance and better termination characteristics compared with off-chip termination. The driver and termination circuits have been incorporated in a 2 Gbaud transceiver chip and fabricated in 0.35 μm CMOS technology. Measurements show a 1.4 V differential swing with a slew rate of 2.5 V/ns at the receiver output and a 65% reduction of reflection by the on-chip termination circuit with power consumption of 191 mW at 3.3 V supply     

Nearly optimal linear transceiver design for amplify‐and‐forward MIMO multiple‐relay systems under MMSE criterion

In this paper, we consider amplify‐and‐forward multiple‐input multiple‐output multiple‐relay systems, where all the nodes have multiple antennas. For enhancing link reliability, we address the problem of designing optimal linear transceiver to minimize the mean squared error (MSE) of symbol estimations subject to the total relay transmit power constraint. This problem is highly complex and has not been solved in the literature. We first simplify this optimization problem to one that takes a singular value vector and a unitary matrix as optimization variables. Then based on the analyses for the simplified problem, we develop an iterative algorithm consisting of one boundary optimization and one unitary matrix constrained optimization. We show analytically that the proposed iterative algorithm always converges, and the MSE is monotonically decreasing from one iteration to the next. Finally, numerical results demonstrate the nearly optimal performance of the proposed scheme. Copyright © 2012 John Wiley & Sons, Ltd.     

Cross‐Layer Resource Allocation Scheme for WLANs with Multipacket Reception

Tailored for wireless local area networks, the present paper proposes a cross‐layer resource allocation scheme for multiple‐input multiple‐output orthogonal frequency‐division multiplexing systems. Our cross‐layer resource allocation scheme consists of three stages. Firstly, the condition of sharing the subchannel by more than one user is studied. Secondly, the subchannel allocation policy which depends on the data packets’ lengths and the admissible combination of users per subchannel is proposed. Finally, the bits and corresponding power are allocated to users based on a greedy algorithm and the data packets’ lengths. The analysis and simulation results demonstrate that our proposed scheme not only achieves significant improvement in system throughput and average packet delay compared with conventional schemes but also has low computational complexity.     

一种基于CMOS工艺的Gbps高速LVDS发送电路

低压差分信号（LVDS）是用于高速低功耗数据传输的一种非常理想的传输技术。由于使用全差分技术和低电压摆幅,LVDS技术达到高速度的同时消耗的功耗非常小。设计了一种具有Gbps发送速度的LVDS发送电路。通过在输出采用闭环控制模式,使得LVDS输出共模电平和电压幅值被控制在一个合理的范围内。基于SMIC 0．18μm CMOS工艺模型,采用Hspice仿真器对整个发送电路进行模拟,结果表明所设计的发送电路具有4Gbps发送速度,功耗仅为18．6mW。     

A 900 MHz Zero‐IF RF Transceiver for IEEE 802.15.4g SUN OFDM Systems

This paper presents a 900 MHz zero‐IF RF transceiver for IEEE 802.15.4g Smart Utility Networks OFDM systems. The proposed RF transceiver comprises an RF front end, a Tx baseband analog circuit, an Rx baseband analog circuit, and a ΔΣ fractional‐N frequency synthesizer. In the RF front end, re‐use of a matching network reduces the chip size of the RF transceiver. Since a T/Rx switch is implemented only at the input of the low‐noise amplifier, the driver amplifier can deliver its output power to an antenna without any signal loss; thus, leading to a low dc power consumption. The proposed current‐driven passive mixer in Rx and voltage‐mode passive mixer in Tx can mitigate the IQ crosstalk problem, while maintaining 50% duty‐cycle in local oscillator clocks. The overall Rx‐baseband circuits can provide a voltage gain of 70 dB with a 1 dB gain control step. The proposed RF transceiver is implemented in a 0.18 μm CMOS technology and consumes 37 mA in Tx mode and 38 mA in Rx mode from a 1.8 V supply voltage. The fabricated chip shows a Tx average power of ?2 dBm, a sensitivity level of ?103 dBm at 100 Kbps with , an Rx input P_1dB of ?11 dBm, and an Rx input IP3 of ?2.3 dBm.     

千兆比特数据率LVDS接口电路设计

设计了一个采用0.18μm1.8V/3.3V CMOS工艺制造的千兆比特数据率LVDS I/O接口电路。发送器电路采用内部参考电流源和片上匹配电阻,使工艺偏差、温度变化对输出信号幅度的影响减小50%;接收器电路采用一种改进的结构,通过检测输入共模电平,自适应调整预放大器偏置电压,保证跨导Gm在LVDS标准[1]要求的共模范围内恒定,因此芯片在接收端引入的抖动最小。芯片面积0.175mm2,3.3V电源电压下功耗为33mW,测试表明此接口传输速率达到1Gb/s。     

A CMOS 10-gb/s SONET transceiver

This paper presents a single-chip SONET OC-192 transceiver (transmitter and receiver) fabricated in a 90-nm mixed-signal CMOS process. The transmitter consists of a 10-GHz clock multiplier unit (CMU), 16:1 multiplexer, and 10-Gb/s output buffer. The receiver consists of a 10-Gb/s limiting input amplifier, clock and data recovery circuit (CDR), 1:16 demultiplexer, and drivers for low-voltage differential signal (LVDS) outputs. Both transmit and receive phase-locked loops employ a 10-GHz on-chip LC voltage-controlled oscillator (VCO). This transceiver exceeds all SONET OC-192 specifications with ample margin. Jitter generation at 10.66-Gb/s data rate is 18 mUI/sub pp/ (unit interval, peak-to-peak) and jitter tolerance is 0.6 UI/sub pp/ at 4-MHz jitter frequency. This transceiver requires 1.2V for the core logic and 1.8 V for input/output LVDS buffers. Multiple power supply domains are implemented here to mitigate crosstalk between receiver and transmitter. The overall power dissipation of this chip is 1.65 W.     

A low‐complexity MSK‐based M‐ary cyclic‐shift keying transceiver for direct sequence spread spectrum system over multipath fading channels

In this paper, a low‐complexity spread spectrum system with M‐ary cyclic‐shift keying (MCSK) symbol spreading is proposed. In addition, by using the minimum‐shift‐keying (MSK) as the chip‐level modulation, we obtain a high‐rate QPSK‐MCSK transceiver scheme which not only provides a constant‐envelop and continuous‐phase transmitted signal, but can also achieve a better performance than the conventional direct sequence spread spectrum (DSSS) system. At the transmitter, the data stream is first mapped into QPSK‐MCSK symbols in terms of orthogonal Gold code sequences, then followed by the cyclic prefix (CP) insertion for combating the interblock interference, and finally applying the MSK scheme to maintain the constant‐envelope property. The receiver first performs MSK demodulation, then CP removal, and finally the channel‐included MCSK despreading and symbol demapping. Furthermore, the single input single output (SISO) QPSK‐MCSK transceiver can be easily extended to the multiple input single output (MISO) case by incorporating the space–time block coding for high‐link quality. Simulation results show that the proposed SISO and MISO QPSK‐MCSK systems significantly outperform the conventional DSSS counterparts under the AWGN channel, and attain a more robust performance under the multipath fading channel. Copyright © 2011 John Wiley & Sons, Ltd.     

Wide‐Band Fine‐Resolution DCO with an Active Inductor and Three‐Step Coarse Tuning Loop

This paper presents a wide‐band fine‐resolution digitally controlled oscillator (DCO) with an active inductor using an automatic three‐step coarse and gain tuning loop. To control the frequency of the DCO, the transconductance of the active inductor is tuned digitally. To cover the wide tuning range, a three‐step coarse tuning scheme is used. In addition, the DCO gain needs to be calibrated digitally to compensate for gain variations. The DCO tuning range is 58% at 2.4 GHz, and the power consumption is 6.6 mW from a 1.2 V supply voltage. An effective frequency resolution is 0.14 kHz. The phase noise of the DCO output at 2.4 GHz is –120.67 dBc/Hz at 1 MHz offset.     

A Dual‐Mode 2.4‐GHz CMOS Transceiver for High‐Rate Bluetooth Systems

This paper reports on our development of a dual‐mode transceiver for a CMOS high‐rate Bluetooth system‐on‐chip solution. The transceiver includes most of the radio building blocks such as an active complex filter, a Gaussian frequency shift keying (GFSK) demodulator, a variable gain amplifier (VGA), a dc offset cancellation circuit, a quadrature local oscillator (LO) generator, and an RF front‐end. It is designed for both the normal‐rate Bluetooth with an instantaneous bit rate of 1 Mb/s and the high‐rate Bluetooth of up to 12 Mb/s. The receiver employs a dualconversion combined with a baseband dual‐path architecture for resolving many problems such as flicker noise, dc offset, and power consumption of the dual‐mode system. The transceiver requires none of the external image‐rejection and intermediate frequency (IF) channel filters by using an LO of 1.6 GHz and the fifth order on‐chip filters. The chip is fabricated on a 6.5‐mm² die using a standard 0.25‐μm CMOS technology. Experimental results show an in‐band image‐rejection ratio of 40 dB, an IIP3 of ?5 dBm, and a sensitivity of ?77 dBm for the Bluetooth mode when the losses from the external components are compensated. It consumes 42 mA in receive π/4‐diffrential quadrature phase‐shift keying (π/4‐DQPSK) mode of 8 Mb/s, 35 mA in receive GFSK mode of 1 Mb/s, and 32 mA in transmit mode from a 2.5‐V supply. These results indicate that the architecture and circuits are adaptable to the implementation of a low‐cost, multi‐mode, high‐speed wireless personal area network.