Filter‐Free Wavelength Conversion Using Mach‐Zehnder Interferometer with Integrated Multimode Interference Semiconductor Optical Amplifiers

We propose a filter‐free wavelength conversion using a Mach‐Zehnder interferometer with monolithically integrated 2×2 multimode interference semiconductor optical amplifiers (MMI‐SOAs). The device has been optimized by considering a non‐homogeneous carrier distribution due to the self‐imaging properties of the MMI‐SOA. Static measurements show an extinction ratio of up to 18 dB and an input signal rejection ratio of up to 20 dB.     

Chromatic Dispersion Monitoring of CSRZ Signal for Optimum Compensation Using Extracted Clock‐Frequency Component

This paper presents a chromatic dispersion monitoring technique using a clock‐frequency component for carrier‐suppressed return‐to‐zero (CSRZ) signal. The clock‐frequency component is extracted by a clock‐extraction (CE) process. To discover which CE methods are most efficient for dispersion monitoring, we evaluate the monitoring performance of each extracted clock signal. We also evaluate the monitoring ability to detect the optimum amount of dispersion compensation when optical nonlinearity exists, since it is more important in nonlinear transmission systems. We demonstrate efficient CE methods of CSRZ signal to monitor chromatic dispersion for optimum compensation in high‐speed optical communication systems.     

3‐Level Envelope Delta‐Sigma Modulation RF Signal Generator for High‐Efficiency Transmitters

This paper presents a 0.13 μm CMOS 3‐level envelope delta‐sigma modulation (EDSM) RF signal generator, which synthesizes a 2.6 GHz‐centered fully symmetrical 3‐level EDSM signal for high‐efficiency power amplifier architectures. It consists of an I‐Q phase modulator, a Class B wideband buffer, an up‐conversion mixer, a D2S, and a Class AB wideband drive amplifier. To preserve fast phase transition in the 3‐state envelope level, the wideband buffer has an RLC load and the driver amplifier uses a second‐order BPF as its load to provide enough bandwidth. To achieve an accurate 3‐state envelope level in the up‐mixer output, the LO bias level is optimized. The I‐Q phase modulator adopts a modified quadrature passive mixer topology and mitigates the I‐Q crosstalk problem using a 50% duty cycle in LO clocks. The fabricated chip provides an average output power of –1.5 dBm and an error vector magnitude (EVM) of 3.89% for 3GPP LTE 64 QAM input signals with a channel bandwidth of 10/20 MHz, as well as consuming 60 mW for both channels from a 1.2 V/2.5 V supply voltage.     

Analysis and Demonstration of Mach–Zehnder Polymer Modulators Using In-Plane Coplanar Waveguide Structure

Analysis, design, and experimental demonstration of polymer Mach-Zehnder (MZ) modulators with a newly proposed in-plane coplanar waveguide (CPW) electrode are presented in this paper. Compared to the conventional CPW electrode, the new in-plane CPW configuration significantly enhances the overlap factor between microwave and optical wave by 40% from the theoretical calculations. Different from polymer modulators using the traditional microstrip electrodes, this structure can suppress dc bias voltage drift and widen modulation bandwidth. Using CLD1/APC and AJL8/APC electrooptic polymers, MZ modulators using the in-plane CPW are fabricated and tested. The measured Vpi's of the MZ with 15-mum gap spacing and 2 cm electrode length are 5.4 and 9.5 V at 1.55 mum for the AJL8/APC and CLD1/APC devices, respectively. The evaluated Upsi₃₃'s are 46 pm/V for the AJL8/APC and 26 pm/V for the CLD1/APC MZ. The dc bias stability is tested and compared for both the microstrip and the in-plane CPW electrode modulators. Experimental results show that the in-plane CPW modulator greatly improves the bias stability. From the microwave measurement, the microwave signal loss of the modulator using the in-plane CPW is much reduced to 0.2 dB/cmradicGHz, while 0.7 dB/cmradicGHz using the microstrip.     

Pseudo Optical PAM‐N Signal Using Externally Modulated Lasers

We propose a pseudo optical N‐level pulse‐amplitude modulation (PO PAM‐N) signal using a few externally‐modulated lasers (EMLs) operating at different wavelengths, which is suitable for upgrading the transmission speed over an optical link of ＜ 10 km single‐mode fiber with low‐cost components. To compare a PO PAM‐N signal with that of a standard optical PAM‐N signal, we perform experiments for evaluating the performance of a 51.56‐Gb/s PO PAM‐4 signal and standard 51.56‐Gb/s optical PAM‐4 signal. The receiver sensitivity (at ) of the PO PAM‐4 signal is 1.5 dB better than the receiver sensitivity of a standard optical PAM‐4 signal. We also investigate the feasibility of PO PAM‐N signals operating at 103.12 Gb/s, considering relative intensity noise, timing jitter, extinction ratio (ER) of EMLs, and dispersion. From the results, a PO PAM‐8 signal performs better than PO PAM‐4 and PO PAM‐16 signals at 103.12 Gb/s. Finally, we suggest a timing control method to suppress the effect of dispersion in a PO PAM‐N signal. We show that the tolerance to dispersion of a 103.12‐Gb/s PO PAM‐8 signal can be improved to ±40 ps/nm by applying a proposed scheme.     

High‐Gain Wideband CMOS Low Noise Amplifier with Two‐Stage Cascode and Simplified Chebyshev Filter

An ultra‐wideband low‐noise amplifier is proposed with operation up to 8.2 GHz. The amplifier is fabricated with a 0.18‐μm CMOS process and adopts a two‐stage cascode architecture and a simplified Chebyshev filter for high gain, wide band, input‐impedance matching, and low noise. The gain of 19.2 dB and minimum noise figure of 3.3 dB are measured over 3.4 to 8.2 GHz while consuming 17.3 mW of power. The Proposed UWB LNA achieves a measured power‐gain bandwidth product of 399.4 GHz.     

Design of Two‐Stage Class AB CMOS Buffers: A Systematic Approach

A systematic approach for the design of two‐stage class AB CMOS unity‐gain buffers is proposed. It is based on the inclusion of a class AB operation to class A Miller amplifier topologies in unity‐gain negative feedback by a simple technique that does not modify quiescent currents, supply requirements, noise performance, or static power. Three design examples are fabricated in a 0.5 µm CMOS process. Measurement results show slew rate improvement factors of approximately 100 for the class AB buffers versus their class A counterparts for the same quiescent power consumption (< 200 µW).     

低电压CMOS模拟集成运算放大器输入级的研究

对于低电压CMOS模拟集成运算放大器输入级所面临的问题,我们提出了三种解决的方法,其中包括输出为Rail—to—Rail的差分输入放大电路,差分输入的互导为恒定值的差分输入电路(假设KN=KP)和差分输入的互导为常数的差分输入电路(KN≠KP)。分别对三种方法进行了详细的分析和讨论,最后,提出了低电压CMOS模拟集成运算放大器输入级还需要解决的问题。     

A Low‐Voltage High‐Performance CMOS Feedforward AGC Circuit for Wideband Wireless Receivers

Wireless communication systems, such as WLAN or Bluetooth receivers, employ preamble data to estimate the channel characteristics, introducing stringent settling‐time constraints. This makes the use of traditional closed‐loop feedback automatic gain control (AGC) circuits impractical for these applications. In this paper, a compact feedforward AGC circuit is proposed to obtain a fast‐settling response. The AGC has been implemented in a 0.35 μm standard CMOS technology. Supplied at 1.8 V, it operates with a power consumption of 1.6 mW at frequencies as high as 100 MHz, while its gain ranges from 0 dB to 21 dB in 3 dB steps through a digital word. The settling time of the circuit is below 0.25 μs.     

A Low‐Spur CMOS PLL Using Differential Compensation Scheme

This paper proposes LC voltage‐controlled oscillator (VCO) phase‐locked loop (PLL) and ring‐VCO PLL topologies with low‐phase noise. Differential control loops are used for the PLL locking through a symmetrical transformer‐resonator or bilaterally controlled varactor pair. A differential compensation mechanism suppresses out‐band spurious tones. The prototypes of the proposed PLL are implemented in a CMOS 65‐nm or 45‐nm process. The measured results of the LC‐VCO PLL show operation frequencies of 3.5 GHz to 5.6 GHz, a phase noise of –118 dBc/Hz at a 1 MHz offset, and a spur rejection of 66 dBc, while dissipating 3.2 mA at a 1 V supply. The ring‐VCO PLL shows a phase noise of –95 dBc/Hz at a 1 MHz offset, operation frequencies of 1.2 GHz to 2.04 GHz, and a spur rejection of 59 dBc, while dissipating 5.4 mA at a 1.1 V supply.     

用CMOS集成跨导器实现通用电流传递函数

本文用COMS集成跨导器实现了通用电流传递函数，以三阶巴特活思高通滤波器传递函数的实现电路为例，进行了MOS管级的PSPICE模拟，结果表明所提出的方法的可行性。     

Demonstration of 4H-SiC CMOS digital IC gates based on the mainstream 6-inch wafer processing technique

In this article, the design, fabrication and characterization of silicon carbide (SiC) complementary-metal-oxide-semiconductor (CMOS)-based integrated circuits (ICs) are presented. A metal interconnect strategy is proposed to fabricate the fundamental N-channel MOS (NMOS) and P-channel MOS (PMOS) devices that are required for the CMOS circuit configuration. Based on the mainstream 6-inch SiC wafer processing technology, the simultaneous fabrication of SiC CMOS ICs and power MOSFET is realized. Fundamental gates, such as inverter and NAND gates, are fabricated and tested. The measurement results show that the inverter and NAND gates function well. The calculated low-to-high delay (low-to-high output transition) and high-to-low delay (high-to-low output transition) are 49.9 and 90 ns, respectively.     

Circuit Design of a High Speed and Low Power CMOS Continuous-time Current Comparator

Current comparator is a fundamental component of current-mode analog integrated circuits. A novel high-performance continuous-time CMOS current comparator is proposed in this paper, which comprises one CMOS complementary amplifier, two resistive-load amplifiers and two CMOS inverters. A MOS resistor is used as the CMOS complementary amplifier's negative feedback. Because the voltage swings of the CMOS complementary amplifier are reduced by low input and output resistances, the delay time of the current comparator is shortened. Its power consumption can be reduced rapidly with the increase of input current. Simulation results based on 1.2 m CMOS process model show the speed of the novel current comparator is comparable with those of the existing fastest CMOS current comparators, and its power consumption is the lowest, so it has the smallest power-delay product. Furthermore, the new current comparator occupies small area and is process-robust, so it is very suitable to high-speed and low-power applications.     

TDM系统高速CMOS单片集成复用/解复用器的研究

本文分析了TDM系统中复用器和解复用器的电路结构,通过比较各种结构之间的优缺点和应用特点,提出了10Gb/s速率工作的复用和解复用器结构及其内部所应采用的电路.进而,本文着重研究了系统中关键的同步电路,给出了具体的设计和优化方法.采用TSMC 0.25 μm CMOS 工艺,本文制作了四种不同的同步触发器并对其性能进行了比较,其中双预充电TSPC触发器可工作在4GHz.以此为基础,本文还设计了半静态结构工作在1.25Gb/s速率的10:1复用器、1∶10解复用器以及TSPC结构工作在1.5625Gb/s速率的5∶1复用器和CML结构工作在10Gb/s速率的1∶4解复用器,通过在晶片测试,其结果表明电路功能正确、工作稳定,达到了设计要求,证明了本文提出的设计方法的可行性和正确性.     

应用于USB2.0的CMOS锁相环设计

以应用于USB2.0接收端的480MHz锁相环作为设计实例,阐述了锁相环集成电路设计的要素,给出了模块设计思路和仿真波形,并比较了集成电路和印制板电路锁相环的设计方法,展示两种设计思路上的共性和差异.     

1.5 V Sub‐mW CMOS Interface Circuit for Capacitive Sensor Applications in Ubiquitous Sensor Networks

In this paper, a low‐power CMOS interface circuit is designed and demonstrated for capacitive sensor applications, which is implemented using a standard 0.35‐μm CMOS logic technology. To achieve low‐power performance, the low‐voltage capacitance‐to‐pulse‐width converter based on a self‐reset operation at a supply voltage of 1.5 V is designed and incorporated into a new interface circuit. Moreover, the external pulse signal for the reset operation is made unnecessary by the employment of the self‐reset operation. At a low supply voltage of 1.5 V, the new circuit requires a total power consumption of 0.47 mW with ultra‐low power dissipation of 157 μW of the interface‐circuit core. These results demonstrate that the new interface circuit with self‐reset operation successfully reduces power consumption. In addition, a prototype wireless sensor‐module with the proposed circuit is successfully implemented for practical applications. Consequently, the new CMOS interface circuit can be used for the sensor applications in ubiquitous sensor networks, where low‐power performance is essential.     

Design and testing of a self-powered 3D integrated SOI CMOS system

A self-powering 3D integrated circuit built using an SOI CMOS process is presented. The 3D integrated circuit has three tiers connected by vertical vias through the intertier oxides. The circuit elements are a photodiode array, a charge-integrating capacitor, and a local oscillator with an output buffer, each on a separate tier. The final system size is 250 μm × 250 μm × 696 μm. Our results demonstrate the circuit as a feasible proof-of-concept 3D “system”. The photodiode array stores charge on the capacitor and powers the oscillator as designed.     

Signal Synchronization Using a Flicker Reduction and Denoising Algorithm for Video‐Signal Optical Interconnect

A video signal through a high‐density optical link has been demonstrated to show the reliability of optical link for high‐data‐rate transmission. To reduce optical point‐to‐point links, an electrical link has been utilized for control and clock signaling. The latency and flicker with background noise occurred during the transferring of data across the optical link due to electrical‐to‐optical with optical‐to‐electrical conversions. The proposed synchronization technology combined with a flicker and denoising algorithm has given good results and can be applied in high‐definition serial data interface (HD‐SDI), ultra‐HD‐SDI, and HD multimedia interface transmission system applications.     

CMOS／SEED光电子集成Crossbar互连网络的实现及控制

本文报道了光电子集成 Crossbar互连网络的光学实现及电控制方法。采用带光窗口的 CMOS/SEED灵巧像元列阵作为逻辑控制交换开关节点 ,输出光强的高低态对比度约为 1.4。由波长为 85 0 nm的半导体激光器发出的光束经过位相计算全息光栅分束器分束 ,形成 8× 2的光束阵列 ,为 CMOS/SEED光调制器窗口列阵提供泵浦光源 ,采用精密加工的高精度二维光纤阵列作为信号输入、输出接口器件。采用计算机并口产生电控制信号实现网络的交叉连接功能 ,编制了相应的控制软件。实验上完成了 16× 16 Crossbar光互连网络的交换功能     

Cost‐Effective Transition to 40 Gb/s Line Rate Using the Existing 10 Gb/s‐Based DWDM Infrastructure

In this paper, we propose and demonstrate a cost‐effective technique to upgrade the capacity of dense wavelength division multiplexing (DWDM) networks to a 40 Gb/s line rate using the existing 10 Gb/s‐based infrastructure. To accommodate 40 Gb/s over the link optimized for 10 Gb/s, we propose applying a combination of super‐FEC, carrier‐suppressed return‐to‐zero, and pre‐emphasis to the 40 Gb/s transponder. The transmission of 40 Gb/s DWDM channels over existing 10 Gb/s line‐rate long‐haul DWDM links, including 40×40 Gb/s transmission over KT's standard single‐mode fiber optimized for 10 Gb/s achieves successful results. The proposed upgrading technique allows the Q‐value margin for a 40 Gb/s line rate to be compatible with that of 10 Gb/s.