2.5Gb/s 0.18μm CMOS时钟数据恢复电路

采用TSMC公司标准的0.18μm CMOS工艺,设计并实现了一个全集成的2.5Gb/s时钟数据恢复电路.时钟恢复由一个锁相环实现.通过使用一个动态的鉴频鉴相器,优化了相位噪声性能.恢复出2.5GHz时钟信号的均方抖动为2.4ps,单边带相位噪声在10kHz频偏处为-111dBc/Hz.恢复出2.5Gb/s数据的均方抖动为3.3ps.芯片的功耗仅为120mW.     

2.5Gb/s/ch 0.18μm CMOS数据恢复电路

设计了一个应用于SFI-5接口的2.5Gb/s/ch数据恢复电路.应用一个延迟锁相环,将数据的眼图中心调整为与参考时钟的上升沿对准,因而同步了并行恢复数据,并降低了误码率.采用TSMC标准的0.18μm CMOS工艺制作了一个单通道的2.5Gb/s/ch数据恢复电路,其面积为0.46mm2.输入231-1伪随机序列,恢复出2.5Gb/s数据的均方抖动为3.3ps.在误码率为10-12的条件下,电路的灵敏度小于20mV.     

A 40 Gb/s Clock and Data Recovery Module with Improved Phase‐Locked Loop Circuits

A 40 Gb/s clock and data recovery (CDR) module for a fiber‐optic receiver with improved phase‐locked loop (PLL) circuits has been successfully implemented. The PLL of the CDR module employs an improved D‐type flip‐flop frequency acquisition circuit, which helps to stabilize the CDR performance, to obtain faster frequency acquisition, and to reduce the time of recovering the lock state in the event of losing the lock state. The measured RMS jitter of the clock signal recovered from 40 Gb/s pseudo‐random binary sequence (2³¹‐1) data by the improved PLL clock recovery module is 210 fs. The CDR module also integrates a 40 Gb/s D‐FF decision circuit, demonstrating that it can produce clean retimed data using the recovered clock.     

10 Gb/s Linear Full-Rate CMOS Phase Detector for Clock Data Recovery Circuit

An improved linear full-rate CMOS 10 Gb/s phase detector is proposed. The improved phase detector overcomes the difficulties in realizing the full-rate operation by adding an I/Q splitter for the input data. Such a topology enlarges the pulse width of output signals to ease the full clock rate operation and the problem of the half period skew in the whole clock data recovery system. The proposed topology is able to provide a good linearity over a wider operating range of input phase offset compared to that of existing designs. The phase detector using the Chartered 0.18 μ m CMOS process is capable of operating up to a 10 GHz clock rate and 10 Gb/s input data for a 1.8 V supply voltage with 31 mW power consumption.     

基于半速率锁相环的5Gb/s CMOS单片时钟恢复电路

利用TSMC的O．18μm CMOS工艺,设计实现了单片集成的5 Gb/s锁相环型时钟恢复电路。该电路采用由半速率鉴相器、四相位环形电流控制振荡器、电荷泵以及环路滤波器组成的半速率锁相环结构。测试表明：在输入速率为5 Gb/s、长度为211-1伪随机序列的情况下,恢复出时钟的均方根抖动为4．7 ps。在偏离中心频率6MHz频率处的单边带相位噪声为-112．3 dBe/Hz。芯片面积仅为0．6mm×O．6 mm,采用1.8 V电源供电,功耗低于90 mW。     

10 Gb/s 0.18 μm CMOS时钟恢复芯片

介绍了基于0．18μmCMOS工艺的10Gb／s时钟恢复电路的设计。核心电路采用预处理加简单锁相环的结构。模拟结果表明，该电路能工作在10GHz频率上，输入信号峰值0．4V时，同步范围可以达到270MHz，总功耗210mW。     

CMOS 5 Gb/s串行接收器

设计了一个使用0.13μm CMOS工艺制造的低电压低功耗串行接收器。它的核心电路工作电压为1V,工作频率范围从2.5 GHz到5 GHz。接收器包括两个1:20的解串器、一个输入信号预放大器以及时钟恢复电路。在输入信号预放大器中设计了一个简单新颖的电路,利用前馈均衡来进一步消除信号的码间串扰,提高接收器的灵敏度。测试表明,接收器功耗45 mW。接收器输入信号眼图闭合0.5UI,信号差分峰-峰值150 mV条件下误码率小于10~(-12)。接收器还包含了时钟数据恢复电路,其中的相位插值器通过改进编码方式,使得输出信号的幅度能够保持恒定,并且相位具有良好的线性度。     

2.5Gb/s Ga As MESFET定时判决电路

设计了 2 .5 Gb/ s光纤通信用耗尽型 Ga As MESFET定时判决电路 .通过 SPICE模拟表明恢复的时钟频率达2 .5 GHz,判决电路传输速率达 2 .5 Gb/ s.实验证明经时钟信号抽样后判决电路可产生正确的数字信号 ,传输速率达 2 .5 Gb/ s     

2.5Gb/s单片时钟恢复数据判决与1:4分接集成电路的设计

用0.25μm CMOS工艺实现一个复杂的高集成度的2.5Gb/s单片时钟数据恢复与1:4分接集成电路.对应于2.5Gb/s的PRBS数据(231-1),恢复并分频后的625MHz时钟的相位噪声为-106.26dBc/Hz@100kHz,同时2.5Gb/s的PRBS数据分接出4路625Mb/s数据.芯片面积仅为0.97mm×0.97mm,电源电压3.3V时核心功耗为550mW.     

A CMOS 5.4/3.24‐Gbps Dual‐Rate CDR with Enhanced Quarter‐Rate Linear Phase Detector

This paper presents a clock and data recovery circuit that supports dual data rates of 5.4 Gbps and 3.24 Gbps for DisplayPort v1.2 sink device. A quarter‐rate linear phase detector (PD) is used in order to mitigate high speed circuit design effort. The proposed linear PD results in better jitter performance by increasing up and down pulse widths of the PD and removes dead‐zone problem of charge pump circuit. A voltage‐controlled oscillator is designed with a ‘Mode’ switching control for frequency selection. The measured RMS jitter of recovered clock signal is 2.92 ps, and the peak‐to‐peak jitter is 24.89 ps under 231–1 bit‐long pseudo‐random bit sequence at the bitrate of 5.4 Gbps. The chip area is 1.0 mm×1.3 mm, and the power consumption is 117 mW from a 1.8 V supply using 0.18 μm CMOS process.     

10Gb/s NRZ码时钟信息提取电路

利用法国OMM IC公司的0.2μm G aA s PHEM T工艺,设计实现了10 G b/s NRZ码时钟信息提取电路。该电路采用改进型双平衡G ilbert单元的结构,引进了容性源极耦合差动电流放大器和调谐负载电路,大大提高了电路的性能。测试表明:在输入速率为9.953 28 G b/s长度为223-1伪随机序列的情况下,提取出的时钟的均方根抖动是1.18 ps,峰峰值抖动是8.44 ps。芯片面积为0.5 mm×1 mm,采用-5 V电源供电,功耗约为100 mW。     

2.5 Gb／s 16：1 MUX IC Design with CMOS

A low--power and high--speed 16.-1 MUX IC designed for optical fiber communication based on TSMC 0.25μm CMOS technology is presented. A tree—type architecture was utilized. The output data bit rate is 2.5 Gb/s at input clock rate of 1.25 GHz. The simulation results show that the output signal has peak—to—peak amplitude of 400 mV, the power dissipation is less than 200 mW and the power dissipation of core circuit is less than 20 mW at the 2.5 Gb/s standard bit rate and supply voltage of 2.5 V. The chip area is 1.8mm^2.     

2.5Gb/s 16:1MUX IC Design with CMOS

A low-power and high-speed 16:1 MUX IC designed for optical fiber communication based on TSMC 0.25 μm CMOS technology is presented. A tree-type architecture was utilized. The output data bit rate is 2.5 Gb/s at input clock rate of 1.25 GHz. The simulation results show that the output signal has peak-to-peak amplitude of 400 mV, the power dissipation is less than 200 mW and the power dissipation of core circuit is less than 20 mW at the 2.5 Gb/s standard bit rate and supply voltage of 2.5 V. The chip area is 1.8 mm2.     

Fabrication of Transimpedance Amplifier Module and Post‐Amplifier Module for 40 Gb/s Optical Communication Systems

The design and performance of an InGaAs/InP transimpedance amplifier and post amplifier for 40 Gb/s receiver applications are presented. We fabricated the 40 Gb/s transimpedance amplifier and post amplifier using InGaAs/InP heterojunction bipolar transistor (HBT) technology. The developed InGaAs/InP HBTs show a cut‐off frequency (f_T) of 129 GHz and a maximum oscillation frequency (f_max) of 175 GHz. The developed transimpedance amplifier provides a bandwidth of 33.5 GHz and a gain of 40.1 dBΩ. A 40 Gb/s data clean eye with 146 mV amplitude of the transimpedance amplifier module is achieved. The fabricated post amplifier demonstrates a very wide bandwidth of 36 GHz and a gain of 20.2 dB. The post‐amplifier module was fabricated using a Teflon PCB substrate and shows a good eye opening and an output voltage swing above 520 mV.     

A 33.6-to-33.8 Gb/s Burst-Mode CDR in 90 nm CMOS Technology

A 33.6–33.8 Gb/s burst-mode clock/data recovery circuit (BMCDR) is presented in this paper. To reduce the data jitter and generate the high-frequency output clock, the LC gated voltage-controlled oscillator is presented. To receive and transmit the broadband data, a wideband input matching circuit and a wideband data buffer are presented, respectively. The phase selector is proposed to overcome the false phase lock due to the full-rate operation. This proposed BMCDR has been fabricated in a 90 nm CMOS process. The measured peak-to-peak and rms jitters for the recovered data are 7.56 ps and 1.15 ps, respectively, for a 33.72 Gb/s, 2 $^{11} -$1 PRBS. The measured bit error rate is less than $10^{-8}$ for a 33.72 Gb/s, 2$^{7} -$1 PRBS. It consumes 73 mW without buffers from a 1.2 V supply.      

1.25～3.125 Gb/s连续数据速率CDR设计

设计了一款工作速率为1.25～3.125 Gb/s的连续可调时钟数据恢复(CDR)电路,可以满足多种通信标准的设计需求.CDR采用相位插值型双环路结构,使系统可以根据应用需求对抖动抑制和相位跟踪能力独立进行优化.针对低功耗和低噪声的需求,提出一种新型半速率采样判决电路,利用电流共享和节点电容充放电技术,数据速率为3.125 Gb/s时,仅需要消耗50 μA电流.芯片采用0.13 μm工艺流片验证,面积0.42 m㎡,功耗98 mw,测试结果表明,时钟数据恢复电路接收PRBS7序列时,误码率小于10-12.     

Si bipolar 14 Gb/s 1:4-demultiplexer IC for system applications

A 1:4-demultiplexer IC meeting the essential requirements for lightwave communication systems has been designed based on a 21 GHz f _T 0.4 μm Si bipolar process. The circuit provides features such as bit-rotation control, clock enable control, outputs aligned in time, and phase aligner for clock signals. It operates up to 14 Gb/s (14 GHz) with a phase margin of ⩾250°. The power consumption is 2 W with a -4.5 V supply. 1:16-demultiplexer operation is demonstrated on the basis of 1:4-demultiplexer IC's at 10 Gb/s     

10Gb/s CMOS时钟和数据恢复电路的设计

介绍了利用0.18μmCMOS工艺实现了应用于光纤传输系统SDHSTM-64级别的时钟和数据恢复电路。采用了电荷泵锁相环(CPPLL)结构,CPPLL中的鉴相器能够鉴测相位产生超前滞后逻辑,采样数据具有1∶2分接的功能。振荡器采用全集成LC压控振荡器,鉴相器采用半速率的结构。对应于10Gb/s的PRBS数据(231-1),恢复出的5GHz时钟的相位噪声为-112dBc/Hz@1MHz,同时10Gb/s的PRBS数据分接出两路5Gb/s数据。芯片面积仅为1.00mm×0.8mm,电源电压1.8V时功耗为158mW。     

A 6 Gbps/pin Low‐Power Half‐Duplex Active Cross‐Coupled LVDS Transceiver with Switched Termination

A novel linear switched termination active cross‐coupled low‐voltage differential signaling (LVDS) transceiver operating at 1.5 GHz clock frequency is presented. On the transmitter side, an active cross‐coupled linear output driver and a switched termination scheme are applied to achieve high speed with low current. On the receiver side, a shared preamplifier scheme is employed to reduce power consumption. The proposed LVDS transceiver implemented in an 80 nm CMOS process is successfully demonstrated to provide a data rate of 6 Gbps/pin, an output data window of 147 ps peak‐to‐peak, and a data swing of 196 mV. The power consumption is measured to be 4.2 mW/pin at 1.2 V.     

43 Gb/s decision circuits in InP DHBT technology

Packaged master-slave D-flip-flops designed in InP DHBT technology with 150 GHz f/sub t/ and 180 GHz f/sub max/ are presented. Measurement results using a 43.2 Gb/s nonreturn to zero (NRZ), pseudo random binary sequence (PRBS) data (generated from 4 channels of 10.8 Gb/s, 2/sup 31/-1, PRBS data) and a 43.2 GHz clock, show a clock phase margin of 190/spl deg/. 2:1 Static frequency dividers designed using the D-flip-flops have been tested up to 50 GHz and show normal operation. These circuits are key building blocks in numerous front-end circuits used for 40 Gb/s optical communication systems.