Ultra-broadband 20.5-31 GHz monolithically-integrated CMOS power amplifier

A fully monolithically-integrated power amplifier with a bandwidth (-3 dB) from 20.5 to 31 GHz was realised in a 0.13 /spl mu/m standard CMOS technology. A maximum power added efficiency of 13% with a corresponding output power of 13 dBm was achieved at 25.7 GHz with 1.5 V supply voltage.     

A DC-11.5 GHz Low-Power, Wideband Amplifier Using Splitting-Load Inductive Peaking Technique

A DC-11.5 GHz low-power amplifier is developed in commercial 0.13 mum, CMOS technology. This amplifier design is based on a three-stage shunt-feedback inverter-configuration with splitting load inductive peaking technique. The peaking inductor is placed at the gate of the nMOS to compensate gain roll-off of the inverter stage and extend its operating bandwidth. This amplifier achieves a gain flatness of 13.21 dB from dc to 11.5 GHz with I/O return losses better than 17 dB at a power consumption of 9.1 mW. The measured noise figure is less than 5.6 dB between 1-11 GHz. The output P1 dB is 8 dBm and input third-order intercept point is 10 dBm. The total chip size is 0.34 mm² including all testing pads, with a core area of only 0.08 mm².     

A 3.1 to 5 GHz CMOS Transceiver for DS‐UWB Systems

This paper presents a direct‐conversion CMOS transceiver for fully digital DS‐UWB systems. The transceiver includes all of the radio building blocks, such as a T/R switch, a low noise amplifier, an I/Q demodulator, a low pass filter, a variable gain amplifier as a receiver, the same receiver blocks as a transmitter including a phase‐locked loop (PLL), and a voltage controlled oscillator (VCO). A single‐ended‐to‐differential converter is implemented in the down‐conversion mixer and a differential‐to‐single‐ended converter is implemented in the driver amplifier stage. The chip is fabricated on a 9.0 mm² die using standard 0.18 µm CMOS technology and a 64‐pin MicroLead Frame package. Experimental results show the total current consumption is 143 mA including the PLL and VCO. The chip has a 3.5 dB receiver gain flatness at the 660 MHz bandwidth. These results indicate that the architecture and circuits are adaptable to the implementation of a wideband, low‐power, and high‐speed wireless personal area network.     

Algorithmic Design of CMOS LNAs and PAs for 60-GHz Radio

Sixty-gigahertz power (PA) and low-noise (LNA) amplifiers have been implemented, based on algorithmic design methodologies for mm-wave CMOS amplifiers, in a 90-nm RF-CMOS process with thick 9-metal-layer Cu backend and transistor f_T/f_MAX of 120 GHz/200 GHz. The PA, fabricated for the first time in CMOS at 60 GHz, operates from a 1.5-V supply with 5.2 dB power gain, a 3-dB bandwidth >13 GHz, a P _1dB of +6.4 dBm with 7% PAE and a saturated output power of +9.3 dBm at 60 GHz. The LNA represents the first 90-nm CMOS implementation at 60 GHz and demonstrates improvements in noise, gain and power dissipation compared to earlier 60-GHz LNAs in 160-GHz SiGe HBT and 0.13-mum CMOS technologies. It features 14.6 dB gain, an IIP ₃ of -6.8 dBm, and a noise figure lower than 5.5 dB, while drawing 16 mA from a 1.5-V supply. The use of spiral inductors for on-chip matching results in highly compact layouts, with the total PA and LNA die areas with pads measuring 0.35times0.43 mm² and 0.35times0.40 mm², respectively     

A 1.5-V 0.7–2.5-GHz CMOS Quadrature Demodulator for Multiband Direct-Conversion Receivers

An integrated quadrature demodulator with an on-chip frequency divider is reported. The mixer consists of a transconductance stage, a passive current switching stage, and an operational amplifier output stage. A complementary input architecture has been used to increase the transconductance for a given bias current. The circuit is inductorless and is capable of operating over a broad frequency range. The chip was implemented in a 0.13-mum CMOS technology. From 700 MHz to 2.5 GHz, the demodulator achieves 35 dB of conversion voltage gain with 250-kHz IF bandwidth, a double-sideband NF of 10 dB with 9-33 kHz 1/f-noise corner. The measured IIP3 is 4 dBm for a 0.1-MHz IF frequency and 10 dBm for a 1-MHz IF frequency. The total chip draws 20 to 24 mA from a single 1.5-V supply.     

80-GHz Tuned Amplifier in Bulk CMOS

An 80-GHz six-stage common source tuned amplifier has been demonstrated using low leakage (higher V_T) NMOS transistors of a 65-nm digital CMOS process with six metal levels. It achieves power gain of 12 dB at 80 GHz with a 3-dB bandwidth of 6 GHz, noise figures (NF's) lower than 10.5 dB at frequencies between 75 and 81 GHz with the lowest NF of 9 dB. IP_{1 dB} is -21 dBm and IIP3 is -11.5 dBm. The amplifier consumes 27 mA from a 1.2 V supply. At V_DD = 1.5 V and 33 mA bias current, NF is less than 9.5 dB within the 3-dB bandwidth and reaches a minimum of 8 dB at 80 GHz.     

应用于IEEE 802.11b无线局域网系统的2.4GHzCMOS单片收发机射频前端

实现了一个应用于IEEE 802.11b无线局域网系统的2.4GHz CMOS单片收发机射频前端,它的接收机和发射机都采用了性能优良的超外差结构.该射频前端由五个模块组成:低噪声放大器、下变频器、上变频器、末前级和LO缓冲器.除了下变频器的输出采用了开漏级输出外,各模块的输入、输出端都在片匹配到50Ω.该射频前端已经采用0.18μm CMOS工艺实现.当低噪声放大器和下变频器直接级联时,测量到的噪声系数约为5.2dB,功率增益为12.5dB,输入1dB压缩点约为-18dBm,输入三阶交调点约为-7dBm.当上变频器和末前级直接级联时,测量到的噪声系数约为12.4dB,功率增益约为23.8dB,输出1dB压缩点约为1.5dBm,输出三阶交调点约为16dBm.接收机射频前端和发射机射频前端都采用1.8V电源,消耗的电流分别为13.6和27.6mA.     

一种24 GHz CMOS功率放大器设计

基于130 nm互补金属氧化物半导体(CMOS)工艺,设计了一种高增益和高输出功率的24 GHz功率放大器。通过片上变压器耦合实现阻抗匹配和功率合成,有效改善放大器的匹配特性和提高输出功率。放大器电路仿真结果表明,在1.5 V供电电压下,功率增益为27.2 dB,输入输出端回波损耗均大于10 dB,输出功率1 dB压缩点13.2 dBm,饱和输出功率17.2 dBm,峰值功率附加效率13.5%。     

E‐Band Wideband MMIC Receiver Using 0.1 µm GaAs pHEMT Process

In this paper, the implementations of a 0.1 µm gallium arsenide (GaAs) pseudomorphic high electron mobility transistor process for a low noise amplifier (LNA), a subharmonically pumped (SHP) mixer, and a single‐chip receiver for 70/80 GHz point‐to‐point communications are presented. To obtain high‐gain performance and good flatness for a 15 GHz (71 GHz to 86 GHz) wideband LNA, a five‐stage input/output port transmission line matching method is used. To decrease the package loss and cost, 2nd and 4th SHP mixers were designed. From the measured results, the five‐stage LNA shows a gain of 23 dB and a noise figure of 4.5 dB. The 2nd and 4th SHP mixers show conversion losses of 12 dB and 17 dB and input P1dB of –1.5 dBm to 1.5 dBm. Finally, a single‐chip receiver based on the 4th SHP mixer shows a gain of 6 dB, a noise figure of 6 dB, and an input P1dB of –21 dBm.     

一种具有精确增益控制的CMOS可编程增益放大器

采用0.13μm RF CMOS工艺,设计了一款具有精确增益步长控制的宽带可编程增益放大器.在传统电阻网络衰减器的基础上,提出了一种新的增益控制方法.该方法采用两个互相重叠的反馈环路,通过改变环路中跨导的比值以实现精细的增益步长控制.测试结果表明,当电源电压为1.2V时,功耗为24 mW,-3 dB带宽为600MHz....     

A monolithic 3.1-4.8 GHz MB-OFDM UWB transceiver in 0.18-μm CMOS

A monolithic RF transceiver for an MB-OFDM UWB system in 3.1-4.8 GHz is presented.The transceiver adopts direct-conversion architecture and integrates all building blocks including a gain controllable wideband LNA,a I/Q merged quadrature mixer,a fifth-order Gm-C bi-quad Chebyshev LPF/VGA,a fast-settling frequency synthesizer with a poly-phase filter,a linear broadband up-conversion quadrature modulator,an active D2S converter and a variablegain power amplifier.The ESD protected transceiver is fabricated in Jazz Semiconductor's 0.18-μm RF CMOS with an area of 6.1 mm2 and draws a total current of 221 mA from 1.8-V supply.The receiver achieves a maximum voltage gain of 68 dB with a control range of 42 dB in 6 dB/Step,noise figures of 5.5-8.8 dB for three sub-bands,and an inband/out-band IIP3 better than-4 dBm/+9 dBm.The transmitter achieves an output power ranging from-10.7 to-3dBm with gain control,an output P1dB better than-7.7 dBm,a sideband rejection about 32.4 dBc,and LO suppression of 31.1 dBc.The hopping time among sub-bands is less than 2.05 ns.     

基于GaN HEMT的13～17 GHz收发多功能芯片

基于GaN高电子迁移率晶体管(HEMT)工艺设计制作了一款收发(T/R)多功能芯片(MFC),主要用于射频前端收发系统.该芯片集成了单刀双掷(SPDT)开关用于选择接收通道或发射通道工作,芯片具有低噪声性能、高饱和输出功率和高功率附加效率等特点.芯片接收通道的LNA采用四级放大、单电源供电、电流复用结构,发射通道的功率放大器采用三级放大、末级四胞功率合成结构,选通SPDT开关采用两个并联器件完成.采用微波在片测试系统完成该芯片测试,测试结果表明,在13～ 17 GHz频段内,发射通道功率增益大于17.5 dB,输出功率大于12W,功率附加效率大于27％.接收通道小信号增益大于24 dB,噪声系数小于2.7 dB,1 dB压缩点输出功率大于9 dBm,输入/输出电压驻波比小于1.8∶1,芯片尺寸为3.70 mm×3.55 mm.     

应用于无线传感网络的2.4GHz低噪声放大器

采用SMIC0.13μmRFCMOS工艺设计,并实现了应用于无线传感网络的2.4GHz差分低功耗低噪声放大器。在低功耗约束下,电路采用差分共源共栅源极退化电感结构。考虑了ESD保护PAD和封装等寄生电容,分析了输入阻抗匹配、增益、噪声和线性度,提出了低功耗条件下输入阻抗匹配和噪声优化措施。芯片测试结果显示,噪声系数NF为2.5dB,输出采用片外无源网络匹配下功率增益S21为9.4dB,输入三阶交调点IIP3为-1.5dBm。在1.2V电源电压下消耗电流3.3mA。芯片面积为860μm×680μm。     

A Sub-2 dB NF Dual-Band CMOS LNA for CDMA/WCDMA Applications

This letter presents the design and experimental results of a 1.8/2.14 GHz dual-band CMOS low-noise amplifier (LNA), which is usable for code division multiple access and wideband code division multiple access applications. To achieve the narrow-band gain and impedance matching at both bands, an extra capacitor in parallel with the C_gs of the main transistor and a harmonic tuned load are switched. Except for the output blocking capacitor and series inductor, all components are integrated on a single-chip. The LNA is designed using a 0.13mum- CMOS process and employs a supply voltage of 1.5 V and dissipates a dc power of 7.5 mW. The measured performances are gains of 14.54 dB and 16.6 dB, and noise figures of 1.75 dB and 1.97 dB at the two frequency bands, respectively. The linearity parameters of and P1dB_in are -16dBm and -5.8 dBm at the 1.8 GHz, -14.8 dBm and -5.3 dBm at the 2.14 GHz, respectively.     

数字硅MOSFET微波特性的研究

利用国内先进的 0 .6μm数字 Si-MOS工艺 ,设计了射频 MOSFET,并研究了其 DC和微波特性 :I-V曲线、S参数、噪声参数和输出功率。研究发现 ,数字电路用 Si MOSFET的频率响应较高 :频率为 1 GHz时功率增益可达 1 0 d B,2 GHz时为 8d B,4GHz时为 5 d B。 1 .8GHz时 ,1分贝压缩输出功率 1 2 .8d Bm,饱和输出功率可达 1 8d Bm,且最小噪声系数为 3 .5 d B。用提取的参数设计并研制了微波 Si MOSFET低噪声放大器 ,以验证MOS器件的微波性能。此放大器由两级级联而成 ,单电源供电 ,输入输出电容隔直。在频率 1 .7～ 2 .2 GHz的范围内 ,测得放大器增益 1 5± 0 .5 d B,噪声系数 N F<3 .8d B,1分贝压缩输出功率 1 2 d Bm;在频率 1 .5～ 2 .5 GHz的范围内 ,放大器增益大于 1 3 d B。     

A 77 GHz mHEMT MMIC Chip Set for Automotive Radar Systems

A monolithic microwave integrated circuit (MMIC) chip set consisting of a power amplifier, a driver amplifier, and a frequency doubler has been developed for automotive radar systems at 77 GHz. The chip set was fabricated using a 0.15 µm gate‐length InGaAs/InAlAs/GaAs metamorphic high electron mobility transistor (mHEMT) process based on a 4‐inch substrate. The power amplifier demonstrated a measured small signal gain of over 20 dB from 76 to 77 GHz with 15.5 dBm output power. The chip size is 2 mm × 2 mm. The driver amplifier exhibited a gain of 23 dB over a 76 to 77 GHz band with an output power of 13 dBm. The chip size is 2.1 mm × 2 mm. The frequency doubler achieved an output power of –6 dBm at 76.5 GHz with a conversion gain of ?16 dB for an input power of 10 dBm and a 38.25 GHz input frequency. The chip size is 1.2 mm × 1.2 mm. This MMIC chip set is suitable for the 77 GHz automotive radar systems and related applications in a W‐band.     

A 77 GHz FMCW radar transmitter with reconfigurable power amplifier in 65 nm CMOS

A frequency modulated continuous-wave (FMCW) radar transmitter in 65 nm CMOS is presented. The transmitter consists of one FMCW signal generator, one reconfigurable power amplifier and bias circuits. FMCW chirp signal comes from a sigma-delta modulated fractional-N phase-locked loop (PLL) with an integrated digital triangle-wave generator to control the output division-ratio of the sigma-delta modulator. A four-way power combining power amplifier is employed to improve the output power with a reconfigurable output power to satisfy different detection distance requirements. The measured results show that the chirp bandwidth achieves 2 GHz, from 76 GHz to 78 GHz, and the power amplifier achieves 13.1 dBm output P1dB with 8.1% PAE. The power amplifier and FMCW signal generator consume 228 mW and 56 mW power, respectively, with a 1.0 V power supply. The core die area is only 2.6×0.88 mm².     

3‐Level Envelope Delta‐Sigma Modulation RF Signal Generator for High‐Efficiency Transmitters

This paper presents a 0.13 μm CMOS 3‐level envelope delta‐sigma modulation (EDSM) RF signal generator, which synthesizes a 2.6 GHz‐centered fully symmetrical 3‐level EDSM signal for high‐efficiency power amplifier architectures. It consists of an I‐Q phase modulator, a Class B wideband buffer, an up‐conversion mixer, a D2S, and a Class AB wideband drive amplifier. To preserve fast phase transition in the 3‐state envelope level, the wideband buffer has an RLC load and the driver amplifier uses a second‐order BPF as its load to provide enough bandwidth. To achieve an accurate 3‐state envelope level in the up‐mixer output, the LO bias level is optimized. The I‐Q phase modulator adopts a modified quadrature passive mixer topology and mitigates the I‐Q crosstalk problem using a 50% duty cycle in LO clocks. The fabricated chip provides an average output power of –1.5 dBm and an error vector magnitude (EVM) of 3.89% for 3GPP LTE 64 QAM input signals with a channel bandwidth of 10/20 MHz, as well as consuming 60 mW for both channels from a 1.2 V/2.5 V supply voltage.     

2.4GHz CMOS高线性功率放大器

采用A类与B类并联的结构,设计了一种2.4GHz高线性功率放大器.输入信号较小时,A类放大器起主要作用;随着输入信号的增大,B类放大器起的作用越来越明显,来补偿A类的压缩,由此显著提高了放大器的线性度.电路主体为共栅管采用自偏置方法的共源共栅结构,提升了功放大信号工作时的可靠性.电路采用中芯国际0.13 μmCMOS工...     

A 65 nm CMOS fully-integrated dynamic reconfigurable differential power amplifier with high gain in both bands

A fully-integrated dual-band dynamic reconfigurable differential power amplifier with high gain in 65 nm CMOS is presented. A switchable shunt LC network is proposed to implement the dual-band reconfigurable operation and achieve high gain at both low and high frequency bands, and the high quality on-chip transformers are utilized to implement input/output impedance matching and single-ended to differential conversion. Measured results show that the dual-band dynamic reconfigurable power amplifier can provide 23 dB gain at 2.15 GHz and 21 dB gain at 4.70 GHz, and achieve more than 19 dBm saturated output power at 2.15 GHz and 13 dBm saturated output power at 4.70 GHz, respectively. The die area is about 1.7 mm×2.0 mm.