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A CMOS frequency synthesizer block for multi‐band orthogonal frequency division multiplexing ultra‐wideband systems is proposed. The proposed frequency synthesizer adopts a double‐conversion architecture for simplicity and to mitigate spur suppression requirements for out‐of‐band interferers in 2.4 and 5 GHz bands. Moreover, the frequency synthesizer can consist of the fewest nonlinear components, such as divide‐by‐Ns and a mixer with the proposed frequency plan, leading to the generation of less spurs. To evaluate the feasibility of the proposed idea, the frequency synthesizer block is implemented in 0.18‐µm CMOS technology. The measured sideband suppression ratio is about 32 dBc, and the phase noise is ‐105 dBc/Hz at an offset of 1 MHz. The fabricated chip consumes 17.6 mA from a 1.8 V supply, and the die‐area including pads is 0.9 × 1.1 mm2. 相似文献
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MB-OFDM UWB系统中高吞吐率Viterbi译码器的实现 总被引:2,自引:2,他引:0
提出了一种用于MB-OFDM UWB系统的高吞吐率低功耗Viterbi译码器结构.该结构利用基4蝶形单元的对称性,降低了Viterbi译码器的实现复杂度.采用SMIC 0.131μm CMOS工艺设计并实现了该译码器,在时钟频率为240MHz时,它的最大数据吞吐率为480Mb/s,功耗为135mW.在加性高斯白噪声信道下,它的误码率十分接近理论仿真值.该译码器可用于MB-OFDM UWB系统以及其他高吞吐率低功耗的通信系统中. 相似文献
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使用一种新的Viterbi译码器设计方法来达到高速率、低功耗设计。在传统Viterbi译码器中,ACS(add-compare-select)单元是基于radix-2网格设计的,而这里将介绍一种新的ACS设计方法,即基于radix-4网格的ACS单元设计。每个这样的ACS单元将有4路输入,即在每个时钟周期能够处理两级传统的基于radix-2设计的两级网格。同时在这里的Viterbi译码器设计中采用了Top-To-Down设计思想,用Verilog语言来描述RTL电路层。并用QuartusII软件进行电路仿真和综合。用本算法在33.333MHz时钟下实观在Altera公司的APEX20KFPGA的64状态Viterbi译码器译码速率可达8Mbps以上,且仅占用很小的硬件资源。采用此方法设计的高速Viterbi解码器SoftIPCore可应用于需要高速,低功耗译码的多媒体移动通讯上。 相似文献
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对MIMO—OFDM系统和Viterbi译码器算法作为最流行的卷积码解码方案进行了探讨。对Viterbi译码器进行进一步的优化设计以及降低其复杂性和功耗等方面的问题进行了探讨。提出用分支对称的特性来进一步降低Viterbi译码器的计算复杂度。 相似文献
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Chanho Lee 《ETRI Journal》2004,26(1):21-26
This paper proposes a new architecture for a Viterbi decoder with an efficient memory management scheme. The trace‐back operation is eliminated in the architecture and the memory storing intermediate decision information can be removed. The elimination of the trace‐back operation also reduces the number of operation cycles needed to determine decision bits. The memory size of the proposed scheme is reduced to 1/(5×constraint length) of that of the register exchange scheme, and the throughput is increased up to twice that of the trace‐back scheme. A Viterbi decoder complying with the IS‐95 reverse link specification is designed to verify the proposed architecture. The decoder has a code rate of 1/3, a constraint length of 9, and a trace‐forward depth of 45. 相似文献
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Viterbi解码器RTL级设计优化 总被引:1,自引:0,他引:1
当今芯片产业竞争激烈,速度低、面积大、功耗高的产品难以在市场中占有一席之地。Viterbi解码器作为一种基于最大后验概率的最优化卷积码解码器,被广泛应用于多种数字通信系统中,却由于其较高算法复杂程度,给芯片设计带来了挑战。针对芯片的速度、面积和功耗,通过对Viterbi解码器RTL级设计的若干优化方法进行研究和讨论,实现了一个应用于DVB-S系统的面积约为2万门的Viterbi解码器。 相似文献
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Viterbi译码器ACS单元的一种新设计 总被引:1,自引:0,他引:1
通过研究几种高速Viterbi译码器的ACS(加比选)单元的结构,提出一种ACS单元新的设计方法.设计中采用Radix-4网格结构,能提高译码器的吞吐量;而简单的逻辑可以有效降低译码器的资源占用率. 相似文献
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一种基于FPGA的Viterbi译码器 总被引:2,自引:2,他引:0
介绍了一种(2,1,6)删余生成的(3,2,6)卷积码的Viterbi译码器的FPGA实现方法。该译码器基于软判决设计,约束长度为7。在具体实现中采用了全并行的处理方法,提高了译码速率。 相似文献
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In this paper, we present a fast Fourier transform (FFT) processor with four parallel data paths for multiband orthogonal frequency‐division multiplexing ultra‐wideband systems. The proposed 128‐point FFT processor employs both a modified radix‐24 algorithm and a radix‐23 algorithm to significantly reduce the numbers of complex constant multipliers and complex booth multipliers. It also employs substructure‐sharing multiplication units instead of constant multipliers to efficiently conduct multiplication operations with only addition and shift operations. The proposed FFT processor is implemented and tested using 0.18 µm CMOS technology with a supply voltage of 1.8 V. The hardware‐ efficient 128‐point FFT processor with four data streams can support a data processing rate of up to 1 Gsample/s while consuming 112 mW. The implementation results show that the proposed 128‐point mixed‐radix FFT architecture significantly reduces the hardware cost and power consumption in comparison to existing 128‐point FFT architectures. 相似文献
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The mutual interference between the two ultra wideband (UWB) technologies, which use the same frequency spectrum, will be a matter of concern in the near future. In this context, we present a performance analysis of direct‐sequence (DS) UWB communication in the presence of multiband orthogonal frequency division multiplexing (MB‐OFDM) UWB interfering transmissions. The channel fading is modeled according to Nakagami‐m distribution, and multi‐user interference is taken into account. The DS‐UWB system performance is evaluated in terms of bit error rate (BER). Specifically, using the characteristic function approach, an analytical expression for the average BER is derived conditioned on the channel impulse response. Numerical and simulation results are provided and compared for different coexistence scenarios. Copyright © 2011 John Wiley & Sons, Ltd. 相似文献
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设计了一种适用于导航系统的低功耗、串行维特比译码器电路.介绍了设计的维特比译码器电路的整体结构和各部分硬件电路的设计与特点,仿真结果显示设计的维特比译码器电路能够正常译码,并能纠正传输过程中的错误比特;SMIC0.18μm工艺下的综合结果表明译码器电路的面积只有4102门,功耗为399.514μW. 相似文献
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This letter considers the channel estimation for two‐way relay MIMO OFDM systems. A least square (LS) channel estimation algorithm under block‐based training is proposed. The mean square error (MSE) of the LS channel estimate is computed, and the optimal training sequences with respect to this MSE are derived. Some numerical examples are presented to evaluate the performance of the proposed channel estimation method. 相似文献
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为满足当前通信系统中存在的多种通信标准要求,提出了一种基于滑窗回溯的多标准Viterbi译码器。与其他Viterbi译码器相比,该译码器在支持任意长度序列译码的基础上,实现了1/2、1/3和1/4三种不同码率的配置,并适配5~9五种可变约束长度。此外,该译码器还具有软判决和硬判决两种判决模式,其中软判决采用8 bit有符号数量化。在对路径度量防溢出及幸存路径管理等模块进行优化后,该译码器能够在不显著增加延迟的前提下,具有更优异的工作性能。实验结果表明,该译码器可以根据设置的参数适用多种通信标准,并得到更好的误码性能。 相似文献
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设计了基于正交频分复用(OFDM)超宽带(UWB)系统的下变频混频器(Mixer),并采用0.18μm RF CMOS工艺,通过一种不同于传统Gilbert结构的新颖的双平衡结构来实现,以降低本振大信号对输出中频端的噪声贡献和干扰,降低混频器的静态直流功耗等.测试结果表明:在4~252MHz的中频范围内,转换增益大于2.5~7.8dB,线性度IIP3大于3.3dBm,噪声系数为22.5~26dB,各端口间隔离度均在约-50dB,在1.8V电压下消耗总电流约为8mA. 相似文献
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设计了基于正交频分复用(OFDM)超宽带(UWB)系统的下变频混频器(Mixer),并采用0.18μm RF CMOS工艺,通过一种不同于传统Gilbert结构的新颖的双平衡结构来实现,以降低本振大信号对输出中频端的噪声贡献和干扰,降低混频器的静态直流功耗等.测试结果表明:在4~252MHz的中频范围内,转换增益大于2.5~7.8dB,线性度IIP3大于3.3dBm,噪声系数为22.5~26dB,各端口间隔离度均在约-50dB,在1.8V电压下消耗总电流约为8mA. 相似文献
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The tone reservation method is one of the most effective pre‐distortion methods for peak‐to‐average power ratio reduction in orthogonal frequency division multiplexing (OFDM) systems. Its direct application to OFDM systems with offset quadrature amplitude modulation (OQAM) is, however, not effective. In this paper, two novel TR‐based methods are proposed, specifically designed for OFDM/OQAM systems by taking into consideration the overlapping nature of OQAM signals. These two methods have different approaches to the generation of the peak‐cancelling signal. The first one (overlapped scaling tone reservation) generates the peak‐cancelling signal using a least squares approximation algorithm with possible adjacent symbol overlap; the second one (multi‐kernel tone reservation) generates the peak‐cancelling signal by using multiple impulse‐like time domain kernels. It is shown by simulation that, when used in OFDM/OQAM systems, the proposed methods can provide better performance than the direct application of the existing controlled clipping tone reservation method, and even outperform the multi‐block tone reservation method. 相似文献