High‐Performance Low‐Power FFT Cores

Recently, the power consumption of integrated circuits has been attracting increasing attention. Many techniques have been studied to improve the power efficiency of digital signal processing units such as fast Fourier transform (FFT) processors, which are popularly employed in both traditional research fields, such as satellite communications, and thriving consumer electronics, such as wireless communications. This paper presents solutions based on parallel architectures for high throughput and power efficient FFT cores. Different combinations of hybrid low‐power techniques are exploited to reduce power consumption, such as multiplierless units which replace the complex multipliers in FFTs, low‐power commutators based on an advanced interconnection, and parallel‐pipelined architectures. A number of FFT cores are implemented and evaluated for their power/area performance. The results show that up to 38% and 55% power savings can be achieved by the proposed pipelined FFTs and parallel‐pipelined FFTs respectively, compared to the conventional pipelined FFT processor architectures.     

40 Gbps All‐Optical 3R Regeneration and Format Conversion with Related InP‐Based Semiconductor Devices

We report an experimental demonstration of 40 Gbps all‐optical 3R regeneration with all‐optical clock recovery based on InP semiconductor devices. We also obtain all optical non‐return‐to‐zero to return‐to‐zero (NRZ‐to‐RZ) format conversion using the recovered clock signal at 10 Gbps and 40 Gbps. It leads to a good performance using a Mach‐Zehnder interferometric wavelength converter and a self‐pulsating laser diode (LD). The self‐pulsating LD serves a recovered clock, which has an rms timing jitter as low as sub‐picosecond. In the case of 3R regeneration of RZ data, we achieve a 1.0 dB power penalty at 10^?9 BER after demultiplexing 40 Gbps to 10 Gbps with an eletro‐absorption modulator. The regenerated 3R data shows stable error‐free operation with no BER floor for all channels. The combination of these functional devices provides all‐optical 3R regeneration with NRZ‐to‐RZ conversion.     

High-speed VLSI architectures for the AES algorithm

This paper presents novel high-speed architectures for the hardware implementation of the Advanced Encryption Standard (AES) algorithm. Unlike previous works which rely on look-up tables to implement the SubBytes and InvSubBytes transformations of the AES algorithm, the proposed design employs combinational logic only. As a direct consequence, the unbreakable delay incurred by look-up tables in the conventional approaches is eliminated, and the advantage of subpipelining can be further explored. Furthermore, composite field arithmetic is employed to reduce the area requirements, and different implementations for the inversion in subfield GF(2/sup 4/) are compared. In addition, an efficient key expansion architecture suitable for the subpipelined round units is also presented. Using the proposed architecture, a fully subpipelined encryptor with 7 substages in each round unit can achieve a throughput of 21.56 Gbps on a Xilinx XCV1000 e-8 bg560 device in non-feedback modes, which is faster and is 79% more efficient in terms of equivalent throughput/slice than the fastest previous FPGA implementation known to date.     

Design and Experiment Results of High‐Speed Wireless Link Using Sub‐terahertz Wave Generated by Photonics‐Based Technology

Using a sub‐terahertz (sub‐THz) wave generated using a photonics‐based technology, a high‐speed wireless link operating at up to 10 Gbps is designed and demonstrated for realization of seamless connectivity between wireless and wired networks. The sub‐THz region is focused upon because of the possibility to obtain sufficient bandwidth without interference with the allocated RF bands. To verify the high‐speed wireless link, such dynamic characteristics as the eye diagrams and bit error rate (BER) are measured at up to 10 Gbps for non‐return‐to‐zero pseudorandom binary sequence data. From the measurement results, a receiver sensitivity of –23.5 dBm at is observed without any error corrections when the link distance between the transmitter and receiver is 3 m. Consequently, we hope that our design and experiment results will be helpful in implementing a high‐speed wireless link using a sub‐THz wave.     

16‐QAM OFDM‐Based W‐Band Polarization‐Division Duplex Communication System with Multi‐gigabit Performance

This paper presents a novel 90 GHz band 16‐quadrature amplitude modulation (16‐QAM) orthogonal frequency‐division multiplexing (OFDM) communication system. The system can deliver 6 Gbps through six channels with a bandwidth of 3 GHz. Each channel occupies 500 MHz and delivers 1 Gbps using 16‐QAM OFDM. To implement the system, a low‐noise amplifier and an RF up/down conversion fourth‐harmonically pumped mixer are implemented using a 0.1‐μm gallium arsenide pseudomorphic high‐electron‐mobility transistor process. A polarization‐division duplex architecture is used for full‐duplex communication. In a digital modem, OFDM with 256‐point fast Fourier transform and (255, 239) Reed‐Solomon forward error correction codecs are used. The modem can compensate for a carrier‐frequency offset of up to 50 ppm and a symbol rate offset of up to 1 ppm. Experiment results show that the system can achieve a bit error rate of 10^–5 at a signal‐to‐noise ratio of about 19.8 dB.     

High‐Speed Access over Copper: Rate Optimization and Signal Construction

This paper focuses on assessment and design of transmission systems for distribution of digital signals over standard Category‐7A copper cables at speeds beyond 10 Gbps. The main contribution of this paper is on the technical feasibility and system design for data rates of 40 Gbps and 100 Gbps over copper. Based on capacity analysis and rate optimization algorithms, system parameters are obtained and the design implementation trade‐offs are discussed. Our simulation results confirm that with the aid of a decision‐feedback equalizer and powerful coding techniques, namely, TCM or LDPC code, 40 Gbps transmission is feasible over 50 m of CAT‐7A copper cable. These results also indicate that 100 Gbps transmission can be achieved over 15 m cables.     

16‐QAM‐Based Highly Spectral‐Efficient E‐band Communication System with Bit Rate up to 10 Gbps

This paper presents a novel 16‐quadrature‐amplitude‐modulation (QAM) E‐band communication system. The system can deliver 10 Gbps through eight channels with a bandwidth of 5 GHz (71‐76 GHz/81‐86 GHz). Each channel occupies 390 MHz and delivers 1.25 Gbps using a 16‐QAM. Thus, this system can achieve a bandwidth efficiency of 3.2 bit/s/Hz. To implement the system, a driver amplifier and an RF up‐/down‐conversion mixer are implemented using a 0.1 µm gallium arsenide pseudomorphic high‐electron‐mobility transistor (GaAs pHEMT) process. A single‐IF architecture is chosen for the RF receiver. In the digital modem, 24 square root raised cosine filters and four (255, 239) Reed‐Solomon forward error correction codecs are used in parallel. The modem can compensate for a carrier‐frequency offset of up to 50 ppm and a symbol rate offset of up to 1 ppm. Experiment results show that the system can achieve a bit error rate of 10^?5 at a signal‐to‐noise ratio of about 21.5 dB.     

High‐Speed,Low‐Voltage,and Environmentally Stable Operation of Electrochemically Gated Zinc Oxide Nanowire Field‐Effect Transistors

Single‐crystal, 1D nanostructures are well known for their high mobility electronic transport properties. Oxide‐nanowire field‐effect transistors (FETs) offer both high optical transparency and large mechanical conformability which are essential for flexible and transparent display applications. Whereas the “on‐currents” achieved with nanowire channel transistors are already sufficient to drive active matrix organic light emitting diode (AMOLED) displays; it is shown here that incorporation of electrochemical‐gating (EG) to nanowire electronics reduces the operation voltage to ≤2 V. This opens up new possibilities of realizing flexible, portable, transparent displays that are powered by thin film batteries. A composite solid polymer electrolyte (CSPE) is used to obtain all‐solid‐state FETs with outstanding performance; the field‐effect mobility, on/off current ratio, transconductance, and subthreshold slope of a typical ZnO single‐nanowire transistor are 62 cm²/Vs, 10⁷, 155 μS/μm and 115 mV/dec, respectively. Practical use of such electrochemically‐gated field‐effect transistor (EG FET) devices is supported by their long‐term stability in air. Moreover, due to the good conductivity (≈10^?2 S/cm) of the CSPE, sufficiently high switching speed of such EG FETs is attainable; a cut‐off frequency in excess of 100 kHz is measured for in‐plane FETs with large gate‐channel distance of >10 μm. Consequently, operation speeds above MHz can be envisaged for top‐gate transistor geometries with insulator thicknesses of a few hundreds of nanometers. The solid polymer electrolyte developed in this study has great potential in future device fabrication using all‐solution processed and high throughput techniques.     

Annihilation-reordering look-ahead pipelined CORDIC-based RLSadaptive filters and their application to adaptive beamforming

The novel annihilation-reordering look-ahead technique is proposed as an attractive technique for pipelining of Givens rotation (or CORDIC)-based adaptive filters. Unlike the existing relaxed look-ahead, the annihilation-reordering look-ahead does not depend on the statistical properties of the input samples. It is an exact look-ahead based on CORDIC arithmetic, which is known to be numerically stable. The conventional look-ahead is based on multiply-add arithmetic. The annihilation-reordering look-ahead technique transforms an orthogonal sequential adaptive filtering algorithm into an equivalent orthogonal concurrent one by creating additional concurrency in the algorithm. Parallelism in the transformed algorithm is explored and different implementation styles including pipelining, block processing, and incremental block processing are presented. Their complexities are also studied and compared. The annihilation-reordering look-ahead is employed to develop fine-grain pipelined QR decomposition-based RLS adaptive filters. Both QRD-RLS and inverse QRD-RLS algorithms are considered. The proposed pipelined architectures can be operated at arbitrarily high sample rate without degrading the filter convergence behavior. Stability under finite-precision arithmetic are studied and proved for the proposed architectures. The pipelined CORDIC-based RLS adaptive filters are then employed to develop high-speed linear constraint minimum variance (LCMV) adaptive beamforming algorithms. Both QR decomposition-based minimum variance distortionless response (MVDR) realization and generalized sidelobe canceller (GSC) realization are presented. The complexity of the pipelined architectures are analyzed and compared. The proposed architectures can be operated at arbitrarily high sample rate and consist of only Givens rotations, which can be scheduled onto CORDIC arithmetic-based processors     

Highly dispersive substitution box (S‐box) design using chaos

Highly dispersive S‐boxes are desirable in cryptosystems as nonlinear confusion sub‐layers for resisting modern attacks. For a near optimal cryptosystem resistant to modern cryptanalysis, a highly nonlinear and low differential probability (DP) value is required. We propose a method based on a piecewise linear chaotic map (PWLCM) with optimization conditions. Thus, the linear propagation of information in a cryptosystem appearing as a high DP during differential cryptanalysis of an S‐box is minimized. While mapping from the chaotic trajectory to integer domain, a randomness test is performed that justifies the nonlinear behavior of the highly dispersive and nonlinear chaotic S‐box. The proposed scheme is vetted using well‐established cryptographic performance criteria. The proposed S‐box meets the cryptographic performance criteria and further minimizes the differential propagation justified by the low DP value. The suitability of the proposed S‐box is also tested using an image encryption algorithm. Results show that the proposed S‐box as a confusion component entails a high level of security and improves resistance against all known attacks.     

Titania‐Based Spherical Mie Resonators Elaborated by High‐Throughput Aerosol Spray: Single Object Investigation

In the framework of photonics with all‐dielectric nanoantennas, sub‐micrometric spheres can be exploited for a plethora of applications including vanishing back‐scattering, enhanced directivity of a light emitter, beam steering, and large Purcell factors. Here, the potential of a high‐throughput fabrication method based on aerosol‐spray is shown to form quasi‐perfect sub‐micrometric spheres of polycrystalline TiO₂. Spectroscopic investigation of light scattering from individual particles reveals sharp resonances in agreement with Mie theory, neat structural colors, and a high directivity. Owing to the high permittivity and lossless material in use, this method opens the way toward the implementation of isotropic meta‐materials and forward‐directional sources with magnetic responses at visible and near‐UV frequencies, not accessible with conventional Si‐ and Ge‐based Mie resonators.     

High Speed FPGA-Based Implementations of Delayed-LMS Filters

A variation of the least means squares (LMS) algorithm, called the delayed LMS (DLMS) algorithm is ideally suited for highly pipelined, adaptive digital filter implementations. In this paper, we present an efficient method to determine the delays in the DLMS filter. Furthermore, in order to achieve fully pipelined circuit architectures for FPGA implementation, we transfer these delays using retiming. The method has been used to derive a series of retimed delayed LMS (RDLMS) architectures, which allow a 66.7% reduction in delays and 5 times faster convergence time thereby giving superior performance in terms of throughput rate when compared to previous work. Three circuit architectures and three hardware shared versions are presented which have been implemented using the Virtex-II FPGA technology resulting in a throughput rate of 182 Msample/s.     

Design methodology for subdigit pipelined digit-serial IIR filters

A novel architecture for high performance two's complement digit-serial IIR filters is presented. The application of the digit-serial computation to the design of IIR filters introduces delay elements in the feedback loop of the IIR filter. This offers the possibility of pipelining the feedback loop inherent in the IIR filters. To fully explore the advantages offered by the use of digit-serial computation, the digit serial structure is based on the feed forward of the carry digit, which allows subdigit pipelining to increase the throughput rate of the IIR filters. A systematic design methodology is presented to derive a wide range of digit-serial IIR filter architectures which can be pipelined to the subdigit level. This will give designers greater flexibility in finding the best trade off between hardware cost and throughput rate. It is shown that the application of digit-serial computations for the realisation of IIR filters combined with the possibility of subdigit pipelining, results in an increase in the computation speed with a considerable reduction in silicon area consumption when compared to an equivalent bit-parallel IIR filter realisations.     

Digital Median Filters

Several DSP algorithms need to remove high-frequency or impulsive noise while preserving edges, e.g., in speech and image processing applications: median filtering has been proved to be more effective for achieving this goal than other filtering techniques. Efficient architectural implementation for real-time applications involves a careful VLSI design, which takes into account modularity, regularity, adaptability, scalability, throughput, circuit complexity and fault tolerance.Four new architectural approaches are presented and evaluated in this paper to deal with different application and implementation constraints. They are: the serial-input polarizing median filter, the floating median filter, the pipelined polarizing median filter and the pipelined sorting median filter. The 1st and the 2nd architectures are based on majority voting, while the 3rd and the 4th ones are based on sorting techniques. All of them are designed so as to exhibit high scalability and to be easily pipelined for higher working frequencies.     

Fast-Converging and Low-Power LDPC Decoding: Algorithm,Architecture, and VLSI Implementation

Low-latency and energy-efficient multi-Gbps LDPC decoding requires fast-converging iterative schedules. Hardware decoder architectures based on such schedules can achieve high throughput at low clock speeds, resulting in reduced power consumption and relaxed timing closure requirements for physical VLSI design. In this work, a fast column message-passing (FCMP) schedule for decoding LDPC codes is presented and investigated. FCMP converges in half the number of iterations compared to existing serial decoding schedules, has a significantly lower computational complexity than residual-belief-propagation (RBP)-based schedules, and consumes less power compared to state-of-the-art schedules. An FCMP decoder architecture supporting IEEE 802.11ad (WiGig) LDPC codes is presented. The decoder is fully pipelined to decode two frames with no idle cycles. The architecture is synthesized using the TSMC 40 nm and 65 nm CMOS technology nodes, and operates at a clock-frequency of 200 MHz. The decoder achieves a throughput of 8.4 Gbps, and it consumes 72 mW of power when synthesized using the 40 nm technology node. This results in an energy efficiency of 8.6 pJ/bit, which is the best-reported energy-efficiency in the literature for a WiGig LDPC decoder.

     

Digital Median Filters

Several DSP algorithms need to remove high-frequency or impulsive noise while preserving edges, e.g., in speech and image processing applications: median filtering has been proved to be more effective for achieving this goal than other filtering techniques. Efficient architectural implementation for real-time applications involves a careful VLSI design, which takes into account modularity, regularity, adaptability, scalability, throughput, circuit complexity and fault tolerance. Four new architectural approaches are presented and evaluated in this paper to deal with different application and implementation constraints. They are: the serial-input polarizing median filter, the floating median filter, the pipelined polarizing median filter and the pipelined sorting median filter. The 1st and the 2nd architectures are based on majority voting, while the 3rd and the 4th ones are based on sorting techniques. All of them are designed so as to exhibit high scalability and to be easily pipelined for higher working frequencies.     

A chip set for pipeline and parallel pipeline FFT architectures

A chip set for pipelined and parallel pipelined FFT applications is presented. The set consists of two cascadeable chips with built-in self-test and a chip-interconnectivity test feature. The two ASICs are a 15k gate Complex-Butterfly and a 9k gate FFT Switch. The Complex-Butterfly uses redundant binary arithmetic (RBA), a modified Booth algorithm and a Wallace tree architecture to achieve a throughput of better than 25 Msamples/sec. The cascadeable FFT Switch is designed to support the implementation of radix-2, 2 ^N point, pipeline FFTs. Both devices have been fabricated in 1.5m CMOS gate array technology.     

Bit-Level systolic architectures for high performance IIR filtering

Several novel systolic architectures for implementing densely pipelined bit parallel IIR filter sections are presented. The fundamental problem of latency in the feedback loop is overcome by employing redundant arithmetic in combination with bit-level feedback, allowing a basic first-order section to achieve a wordlength-independent latency of only two clock cycles. This is extended to produce a building block from which higher order sections can be constructed. The architecture is then refined by combining the use of both conventional and redundant arithmetic, resulting in two new structures offering substantial hardware savings over the original design. In contrast to alternative techniques, bit-level pipelinability is achieved with no net cost in hardware.This paper is a revised and extended version of a paper by the same authors presented at the second International Conference on Systolic Arrays, San Diego, May 1988 [1].     

Efficient Masking Methods Appropriate for the Block Ciphers ARIA and AES

In this paper, we propose efficient masking methods for ARIA and AES. In general, a masked S‐box (MS) block can be constructed in different ways depending on the implementation platform, such as hardware and software. However, the other components of ARIA and AES have less impact on the implementation cost. We first propose an efficient masking structure by minimizing the number of mask corrections under the assumption that we have an MS block. Second, to make a secure and efficient MS block for ARIA and AES, we propose novel methods to solve the table size problem for the MS block in a software implementation and to reduce the cost of a masked inversion which is the main part of the MS block in the hardware implementation.