Uniform and position-controlled InAs nanowires on 2" Si substrates for transistor applications

This study presents a novel approach for indirect integration of InAs nanowires on 2' Si substrates. We have investigated and developed epitaxial growth of InAs nanowires on 2' Si substrates via the introduction of a thin yet high-quality InAs epitaxial layer grown by metalorganic vapor phase epitaxy. We demonstrate well-aligned nanowire growth including precise position and diameter control across the full wafer using very thin epitaxial layers (<300 nm). Statistical analysis results performed on the grown nanowires across the 2' wafer size verifies our full control on the grown nanowire with 100% growth yield. From the crystallographic viewpoint, these InAs nanowires are predominantly of wurtzite structure. Furthermore, we show one possible device application of the aforementioned structure in vertical wrap-gated field-effect transistor geometry. The vertically aligned InAs nanowires are utilized as transistor channels and the InAs epitaxial layer is employed as the source contact. A high uniformity of the device characteristics for numerous transistors is further presented and RF characterization of these devices demonstrates an f(t) of 9.8 GHz.     

Edge‐Epitaxial Growth of InSe Nanowires toward High‐Performance Photodetectors

Semiconducting nanowires offer many opportunities for electronic and optoelectronic device applications due to their unique geometries and physical properties. However, it is challenging to synthesize semiconducting nanowires directly on a SiO₂/Si substrate due to lattice mismatch. Here, a catalysis‐free approach is developed to achieve direct synthesis of long and straight InSe nanowires on SiO₂/Si substrates through edge‐homoepitaxial growth. Parallel InSe nanowires are achieved further on SiO₂/Si substrates through controlling growth conditions. The underlying growth mechanism is attributed to a selenium self‐driven vapor–liquid–solid process, which is distinct from the conventional metal‐catalytic vapor–liquid–solid method widely used for growing Si and III–V nanowires. Furthermore, it is demonstrated that the as‐grown InSe nanowire‐based visible light photodetector simultaneously possesses an extraordinary photoresponsivity of 271 A W^?1, ultrahigh detectivity of 1.57 × 10¹⁴ Jones, and a fast response speed of microsecond scale. The excellent performance of the photodetector indicates that as‐grown InSe nanowires are promising in future optoelectronic applications. More importantly, the proposed edge‐homoepitaxial approach may open up a novel avenue for direct synthesis of semiconducting nanowire arrays on SiO₂/Si substrates.     

Cover Picture: Dendritic Nanowire Growth Mediated by a Self‐Assembled Catalyst (Adv. Mater. 5/2005)

The dendritic nanostructures shown on the cover background were generated by self‐assembled Mn clusters deposited from the vapor phase during vapor–liquid–solid growth of InAs nanowires. By carefully controlling the timing and amount of the Mn precursor, on p. 598 Lauhon and co‐workers demonstrate a route to the formation of ordered hierarchical nanowire structures shown from various perspectives in the cover insets.     

Strain and shape of epitaxial InAs/InP nanowire superlattice measured by grazing incidence X-ray techniques

Quantitative structural information about epitaxial arrays of nanowires are reported for a InAs/InP longitudinal heterostructure grown by chemical beam epitaxy on an InAs (111)B substrate. Grazing incidence X-ray diffraction allows the separation of the nanowire contribution from the substrate overgrowth and gives averaged information about crystallographic phases, epitaxial relationships (with orientation distribution), and strain. In-plane strain inhomogeneities, intrinsic to the nanowires geometry, are measured and compared to atomistic simulations. Small-angle X-ray scattering evidences the hexagonal symmetry of the nanowire cross-section and provides a rough estimate of size fluctuations.     

Single crystalline PtSi nanowires, PtSi/Si/PtSi nanowire heterostructures, and nanodevices

We report the formation of PtSi nanowires, PtSi/Si/PtSi nanowire heterostructures, and nanodevices from such heterostructures. Scanning electron microscopy studies show that silicon nanowires can be converted into PtSi nanowires through controlled reactions between lithographically defined platinum pads and silicon nanowires. High-resolution transmission electron microscopy studies show that PtSi/Si/PtSi heterostructure has an atomically sharp interface with epitaxial relationships of Si[110]//PtSi[010] and Si(111)//PtSi(101). Electrical measurements show that the pure PtSi nanowires have low resistivities approximately 28.6 microOmega.cm and high breakdown current densities>1x10(8) A/cm2. Furthermore, using single crystal PtSi/Si/PtSi nanowire heterostructures with atomically sharp interfaces, we have fabricated high-performance nanoscale field-effect transistors from intrinsic silicon nanowires, in which the source and drain contacts are defined by the metallic PtSi nanowire regions, and the gate length is defined by the Si nanowire region. Electrical measurements show nearly perfect p-channel enhancement mode transistor behavior with a normalized transconductance of 0.3 mS/microm, field-effect hole mobility of 168 cm2/V.s, and on/off ratio>10(7), demonstrating the best performing device from intrinsic silicon nanowires.     

van der Waals epitaxy of InAs nanowires vertically aligned on single-layer graphene

Semiconductor nanowire arrays integrated vertically on graphene films offer significant advantages for many sophisticated device applications. We report on van der Waals (VDW) epitaxy of InAs nanowires vertically aligned on graphene substrates using metal-organic chemical vapor deposition. The strong correlation between the growth direction of InAs nanowires and surface roughness of graphene substrates was investigated using various graphene films with different numbers of stacked layers. Notably, vertically well-aligned InAs nanowire arrays were obtained easily on single-layer graphene substrates with sufficiently strong VDW attraction. This study presents a considerable advance toward the VDW heteroepitaxy of inorganic nanostructures on chemical vapor-deposited large-area graphenes. More importantly, this work demonstrates the thinnest epitaxial substrate material that yields vertical nanowire arrays by the VDW epitaxy method.     

Cover Picture: Influence of Plasma Stimulation on Si Nanowire Nucleation and Orientation Dependence (Adv. Mater. 18/2007)

On p. 2603, Tom Picraux and co‐workers report on the use of plasma excitation to strongly enhance the nucleation of Si nanowires by the vapor–liquid–solid growth method. This control allows the preferential formation of very small diameter [110] oriented nanowires, as well as significant enhancements in low temperature nanowire growth.     

Scanned probe imaging of quantum dots inside InAs nanowires

We show how a scanning probe microscope (SPM) can be used to image electron flow through InAs nanowires, elucidating the physics of nanowire devices on a local scale. A charged SPM tip is used as a movable gate. Images of nanowire conductance versus tip position spatially map the conductance of InAs nanowires at liquid-He temperatures. Plots of conductance versus backgate voltage without the tip present show complex patterns of Coulomb-blockade peaks. Images of nanowire conductance identify their source as multiple quantum dots formed by disorder along the nanowire--each dot is surrounded by a series of concentric rings corresponding to Coulomb blockade peaks. An SPM image locates the dots and provides information about their size. In this way, SPM images can be used to understand the features that control transport through nanowires. The nanowires were grown from metal catalyst particles and have diameters approximately 80 nm and lengths 2-3 microm.     

Contactless Electrical and Structural Characterization of Semiconductor Nanowires with Axially Modulated Doping Profiles

Efficient characterization of semiconductor nanowires having complex dopant profiles or heterostructures is critical to fully understand these materials and the devices built from them. Existing electrical characterization techniques are slow and laborious, particularly for multisegment nanowires, and impede the statistical understanding of highly variable samples. Here, it is shown that electro‐orientation spectroscopy (EOS)—a high‐throughput, noncontact method for statistically characterizing the electrical properties of entire nanowire ensembles—can determine the conductivity and dimensions of two distinct segments in individual Si nanowires with axially encoded dopant profiles. This analysis combines experimental measurements and computational simulations to determine the electrical conductivity of the nominally undoped segment of two‐segment Si nanowires, as well as the ratio of the segment lengths. The efficacy of this approach is demonstrated by comparing results generated by EOS with conventional four‐point‐probe measurements. This work provides new insights into the control and variability of semiconductor nanowires for electronic applications and is a critical first step toward the high‐throughput interrogation of complete nanowire‐based devices.     

Si/InGaN core/shell hierarchical nanowire arrays and their photoelectrochemical properties

Three-dimensional hierarchical nanostructures were synthesized by the halide chemical vapor deposition of InGaN nanowires on Si wire arrays. Single phase InGaN nanowires grew vertically on the sidewalls of Si wires and acted as a high surface area photoanode for solar water splitting. Electrochemical measurements showed that the photocurrent density with hierarchical Si/InGaN nanowire arrays increased by 5 times compared to the photocurrent density with InGaN nanowire arrays grown on planar Si (1.23 V vs RHE). High-resolution transmission electron microscopy showed that InGaN nanowires are stable after 15 h of illumination. These measurements show that Si/InGaN hierarchical nanostructures are a viable high surface area electrode geometry for solar water splitting.     

Faceting, composition and crystal phase evolution in III-V antimonide nanowire heterostructures revealed by combining microscopy techniques

III-V antimonide nanowires are among the most interesting semiconductors for transport physics, nanoelectronics and long-wavelength optoelectronic devices due to their optimal material properties. In order to investigate their complex crystal structure evolution, faceting and composition, we report a combined scanning electron microscopy (SEM), transmission electron microscopy (TEM), and scanning tunneling microscopy (STM) study of gold-nucleated ternary InAs/InAs(1-x)Sb(x) nanowire heterostructures grown by molecular beam epitaxy. SEM showed the general morphology and faceting, TEM revealed the internal crystal structure and ternary compositions, while STM was successfully applied to characterize the oxide-free nanowire sidewalls, in terms of nanofaceting morphology, atomic structure and surface composition. The complementary use of these techniques allows for correlation of the morphological and structural properties of the nanowires with the amount of Sb incorporated during growth. The addition of even a minute amount of Sb to InAs changes the crystal structure from perfect wurtzite to perfect zinc blende, via intermediate stacking fault and pseudo-periodic twinning regimes. Moreover, the addition of Sb during the axial growth of InAs/InAs(1-x)Sb(x) heterostructure nanowires causes a significant conformal lateral overgrowth on both segments, leading to the spontaneous formation of a core-shell structure, with an Sb-rich shell.     

Remote p-doping of InAs nanowires

We report on remote p-type doping of InAs nanowires by a p-doped InP shell grown epitaxially on the core nanowire. This approach addresses the challenge of obtaining quantitative control of doping levels in nanowires grown by the vapor-liquid-solid (VLS) mechanism. Remote doping of III-V nanowires is demonstrated here with the InAs/InP system. It is especially challenging to make p-type InAs wires because of Fermi level pinning around 0.1 eV above the conduction band. We demonstrate that shielding with a p-doped InP shell compensates for the built-in potential and donates free holes to the InAs core. Moreover, the off-current in field-effect devices can be reduced up to 6 orders of magnitude. The effect of shielding critically depends on the thickness of the InP capping layer and the dopant concentration in the shell.     

Control of InAs nanowire growth directions on Si

We report on control of growth directions of InAs nanowires on Si substrate. We achieved to integrate vertical InAs nanowires on Si by modifying initial Si(111) surface in selective-area metal-organic vapor phase epitaxy with flow-rate modulation mode at low temperature. Cross-sectional transmission electron microscope and Raman scattering showed that misfit dislocation with local strains were accommodated in the interface.     

Effects of a shell on the electronic properties of nanowire superlattices

We compute the structural and electronic properties of core-shell InAs/GaAs nanowire superlattices using Keating's valence force field and a sp3d5s* tight-binding model. We show that the GaAs shell limits strain relaxation but homogenizes the hydrostatic strain distribution in the InAs layers. This prevents the formation of a strain-induced well in the conduction band at the surface of the nanowires, which was shown to trap the electrons in thin InAs layers (Phys. Rev. B 2006, 74, 155304). The shell, however, enhances the piezoelectric field, which increases the separation between the electrons and holes in thick InAs layers. These results emphasize the intricate links between the structural and electronic properties of strained nanowire heterostructures.     

Ultralong zinc-blende ZnS nanowires grown on polar C face of 6H-SiC substrates at low temperatures by metalorganic chemical vapor deposition

Ultralong ZnS nanowires with high purity were grown on Au-coated polar C face of 6H-SiC substrates via metalorganic chemical vapor deposition at low temperatures. The ZnS nanowires have zinc-blende structure and the length is up to tens of micrometers. HRTEM investigations show that the nanowires are well crystalline single crystal grown along [1 1 1] and free of bulk defects. However, sparse straight and curved nanowires with poor crystalline nature are randomly grown on the Au-coated Si face of 6H-SiC substrates. We deduce that the growth of ZnS is related to the substrates and C face can enhance Au-catalytic VLS growth. The CL spectra of an individual nanowire grown on C and Si face reveal different optical properties. Intrinsic sulfur and zinc vacancies are the main reasons for the 458.1 nm and 459.2 nm blue emission detected in the nanowire grown on C face and Si face, respectively. Nevertheless, an unusual green emission at 565.1 nm is observed in the poor crystalline nanowire grown on Si face, which originates from the bulk defects.     

Growing Oxide Nanowires and Nanowire Networks by Solid State Contact Diffusion into Solution‐Processed Thin Films

New techniques to directly grow metal oxide nanowire networks without the need for initial nanoparticle seed deposition or postsynthesis nanowire casting will bridge the gap between bottom‐up formation and top‐down processing for many electronic, photonic, energy storage, and conversion technologies. Whether etched top‐down, or grown from catalyst nanoparticles bottom‐up, nanowire growth relies on heterogeneous material seeds. Converting surface oxide films, ubiquitous in the microelectronics industry, to nanowires and nanowire networks by the incorporation of extra species through interdiffusion can provide an alternative deposition method. It is shown that solution‐processed thin films of oxides can be converted and recrystallized into nanowires and networks of nanowires by solid‐state interdiffusion of ionic species from a mechanically contacted donor substrate. NaVO₃ nanowire networks on smooth Si/SiO₂ and granular fluorine‐doped tin oxide surfaces can be formed by low‐temperature annealing of a Na diffusion species‐containing donor glass to a solution‐processed V₂O₅ thin film, where recrystallization drives nanowire growth according to the crystal habit of the new oxide phase. This technique illustrates a new method for the direct formation of complex metal oxide nanowires on technologically relevant substrates, from smooth semiconductors, to transparent conducting materials and interdigitated device structures.     

几种Si、Ge纳米线导热系数的原子模拟

采用非平衡分子动力学方法模拟了Si纳米线、Ge纳米线、核-壳结构的Si/Ge纳米线及超晶格结构的Si/Ge纳米线的导热系数,给出了纳米线的温度与导热系数关系曲线,对比了几种纳米线导热特性的差异,研究结果表明,随着温度的升高,各纳米线的导热系数降低;相同温度下,纳米线导热系数的大小顺序为：核-壳结构的Si/Ge纳米线、超晶格结构的Si/Ge纳米线、Si纳米线、Ge纳米线。     

Direct atomic scale imaging of III-V nanowire surfaces

We have succeeded in direct atomic scale imaging of the exterior surfaces of III-V nanowires by scanning tunneling microscopy (STM). By using atomic hydrogen, we expose the crystalline surfaces of InAs nanowires with regular InP segments in vacuum while retaining the wire morphology. We show images with atomic resolution of the two major types of InAs wurtzite nanowire surface facets and scanning tunneling spectroscopy (STS) data. Ab initio calculations of the lowest energy surface structures and simulated STM images, agree very well with experiments.     

Surface Coating Constraint Induced Anisotropic Swelling of Silicon in Si–Void@SiO x Nanowire Anode for Lithium‐Ion Batteries

Here a simple and an environmentally friendly approach is developed for the fabrication of Si–void@SiO_x nanowires of a high‐capacity Li‐ion anode material. The outer surface of the robust SiO_x backbone and the inside void structure in Si–void@SiO_x nanowires appropriately suppress the volume expansion and lead to anisotropic swelling morphologies of Si nanowires during lithiation/delithiation, which is first demonstrated by the in situ lithiation process. Remarkably, the Si–void@SiO_x nanowire electrode exhibits excellent overall lithium‐storage performance, including high specific capacity, high rate property, and excellent cycling stability. A reversible capacity of 1981 mAh g^?1 is obtained in the fourth cycle, and the capacity is maintained at 2197 mAh g^?1 after 200 cycles at a current density of 0.5 C. The outstanding overall properties of the Si–void@SiO_x nanowire composite make it a promising anode material of lithium‐ion batteries for the power‐intensive energy storage applications.     

Formation of epitaxial NiSi2 nanowires on Si(100) surface by atomic force microscope nanolithography

Ni nanowries were fabricated by atomic force microscope nanolithography, evaporation, lift-off and annealing processes. Epitaxial NiSi2 nanowires on a Si(100) surface along Si(110) and (100) directions were formed by the rapid thermal annealing treatment of the Ni nanowires at 400 degrees C. The silicide nanowires along the Si(110) direction had coherent type-A Si(111) and Si(100) interfaces, while those along the Si(100) direction had a type-A Si(110) interface. Silicide nanowires were agglomerated when the Ni nanowires were annealed at high temperature (> or = 500 degrees C). The mechanism of formation of a faceted nanowire was discussed based on the minimization of the total surface energy.