粗糙界面对超薄栅MOS结构的直接隧穿电流的影响

研究了粗糙界面对电子隧穿超薄栅金属-氧化物-半导体场效应晶体管的氧化层的影响.对于栅厚为3nm的超薄栅MOS结构的界面用高斯粗糙面进行模拟来获取界面粗糙度对直接隧穿电流的影响,数值模拟的结果表明:界面粗糙度对电子的直接隧穿有较大的影响,且直接隧穿电流随界面的粗糙度增加而增大,界面粗糙度对电子的直接隧穿的影响随着外加电压的增加而减小.     

镜像势引起的势垒降低对超薄栅MOS结构的直接隧穿电流的影响

随着器件尺寸的不断减小 ,直接隧穿电流将代替 FN电流而成为影响器件可靠性的主要因素 .数值求解的结果表明 :镜像势引起的势垒降低对超薄栅 MOS直接隧穿电流有较大的影响 .利用 WKB近似方法 ,获得了镜像势对直接隧穿电流影响的定性表达式 .镜像势对直接隧穿电流的影响随着栅电压的减小而增大 ,但是随着栅氧化层厚度的减小而减小     

超薄栅介质MOSFET直接隧穿电流自洽解模型

采用自洽解方法求解一维薛定谔方程和二维泊松方程,得到电子的量子化能级和相应的浓度分布,利用MWKB方法计算电子隧穿几率,从而得到不同栅偏置下超薄栅介质MOSFET的直接隧穿电流模型。一维模拟结果与实验数据十分吻合,表明了模型的准确性和实用性。二维模拟结果表明,低栅压下,沟道边缘隧穿电流远大于沟道中心隧穿电流,沟道各处的隧穿电流均大于一维模拟结果;高栅压下,隧穿电流在沟道的分布趋于一致,且逼近一维模拟结果。     

镜像势引起的势垒降低对超薄栅MOS结构的直接隧穿电流的影响

随着器件尺寸的不断减小,直接隧穿电流将代替FN电流而成为影响器件可靠性的主要因素．数值求解的结果表明：镜像势引起的势垒降低对超薄栅MOS直接隧穿电流有较大的影响．利用WKB近似方法,获得了镜像势对直接隧穿电流影响的定性表达式．镜像势对直接隧穿电流的影响随着栅电压的减小而增大,但是随着栅氧化层厚度的减小而减小．     

超薄栅MOS结构恒压应力下的直接隧穿弛豫谱

随着器件尺寸的迅速减小 ,直接隧穿电流将代替 FN电流而成为影响器件可靠性的主要因素 .根据比例差值算符理论和弛豫谱技术 ,针对直接隧穿应力下超薄栅 MOS结构提出了一种新的弛豫谱——恒压应力下的直接隧穿弛豫谱 (DTRS) .该弛豫谱保持了原有弛豫谱技术直接、快速和方便的优点 ,能够分离和表征超薄栅 MOS结构不同氧化层陷阱 ,提取氧化层陷阱的产生 /俘获截面、陷阱密度等陷阱参数 .直接隧穿弛豫谱主要用于研究直接隧穿注入的情况下超薄栅 MOS结构中陷阱的产生和复合 ,为超薄栅 MOS结构的可靠性研究提供了一强有力工具 .     

超薄栅MOS结构恒压应力下的直接隧穿弛豫谱

随着器件尺寸的迅速减小,直接隧穿电流将代替FN电流而成为影响器件可靠性的主要因素.根据比例差值算符理论和弛豫谱技术,针对直接隧穿应力下超薄栅MOS结构提出了一种新的弛豫谱--恒压应力下的直接隧穿弛豫谱(DTRS).该弛豫谱保持了原有弛豫谱技术直接、快速和方便的优点,能够分离和表征超薄栅MOS结构不同氧化层陷阱,提取氧化层陷阱的产生/俘获截面、陷阱密度等陷阱参数.直接隧穿弛豫谱主要用于研究直接隧穿注入的情况下超薄栅MOS结构中陷阱的产生和复合,为超薄栅MOS结构的可靠性研究提供了一强有力工具.     

一个适用于短沟HALO结构MOS器件的直接隧穿栅电流模型

对沟道长度从10μm到0.13μm,栅氧化层厚度为2.5nm的HALO结构nMOS器件的直接隧穿栅电流进行了研究,得到了一个适用于短沟道HALO结构MOS器件的直接隧穿栅电流模型.随着沟道尺寸的缩短,源/漏扩展区占据沟道的比例越来越大,源漏扩展区的影响不再可以忽略不计.文中考虑了源/漏扩展区对直接隧穿栅电流的影响,给出了适用于不同HALO掺杂剂量的超薄栅(2～4nm)短沟(0.13～0.25μm)nMOS器件的半经验直接隧穿栅电流模拟表达式.     

一个适用于短沟HALO结构MOS器件的直接隧穿栅电流模型

对沟道长度从10μm到0.13μm,栅氧化层厚度为2.5nm的HALO结构nMOS器件的直接隧穿栅电流进行了研究,得到了一个适用于短沟道HALO结构MOS器件的直接隧穿栅电流模型.随着沟道尺寸的缩短,源/漏扩展区占据沟道的比例越来越大,源漏扩展区的影响不再可以忽略不计.文中考虑了源/漏扩展区对直接隧穿栅电流的影响,给出了适用于不同HALO掺杂剂量的超薄栅(2～4nm)短沟(0.13～0.25μm)nMOS器件的半经验直接隧穿栅电流模拟表达式.     

MOSFET栅氧泄漏隧穿电流的分析模型:量子力学研究(英文)

研发了一种通过MOSFET的超薄栅氧化物分析直接隧穿电流密度的模型。采用Wentzel-Kramers-Brilliouin(WKB)近似计算了隧穿概率,利用清晰的表面势方程改进模型的准确性。在研究模型中考虑了Si衬底中反型层的量子化和多晶硅栅耗尽,还研究了多晶硅掺杂对栅氧化层隧穿电流的影响。仿真结果表明,栅氧化层隧穿电流随多晶硅栅掺杂浓度的增加而增加。该结论与已报道的结果相吻合,从而证明了该模型的正确性。     

考虑量子力学效应的超薄栅氧nMOSFET's直接隧穿电流二维模型

研究了超薄栅氧MOS器件的直接隧穿(direct tunneling,DT)电流模型问题.利用修正的WKB近似方法(modified WKB,MWKB)得到电子隧穿栅氧的几率,利用修正的艾利函数(modified Airy function,MAF)方法计算得到在高电场条件下载流子的量子化能级,从而计算出在不同偏置条件下的DT电流.模型实现了nMOSFET's栅隧穿电流的二维模拟,可以模拟在不同栅漏偏置条件下的器件工作情况,具有较广泛的适用性.通过对比表明,本模型能够与实验结果很好地吻合,且速度明显优于数值方法.利用模型可很好地对深亚微米MOS器件的栅电流特性进行预测.     

Effect of SiO2/Si interface roughness on gate current

In many theoretical investigations of the electric-tunnel effect through an ultrathin oxide in metal-oxide-semiconductor (MOS) structure, it is commonly assumed that the oxide is of uniform thickness. One example of nonuniformity in oxides is interface roughness. Interface roughness effects on direct tunneling current in ultrathin MOS structures are investigated theoretically in this article. The roughness at SiO₂/Si interface is described in terms of Gauss distribution. It is shown that the transmission coefficient increases with root-mean-square (rms) roughness increasing, and the effect of rms roughness on the direct tunneling current decreases with the applied voltage increasing and increases with rms roughness increasing.     

A review of gate tunneling current in MOS devices

Gate current in metal–oxide–semiconductor (MOS) devices, caused by carriers tunneling through a classically forbidden energy barrier, is studied in this paper. The physical mechanisms of tunneling in an MOS structure are reviewed, along with the particularities of tunneling in modern MOS transistors, including effects such as direct tunneling, polysilicon depletion, hole tunneling and valence band tunneling and gate current partitioning. The modeling approach to gate current used in several compact MOS models is presented and compared. Also, some of the effects of this gate current in the performance of digital, analog and RF circuits is discussed, and it is shown how new effects and considerations will come into play when designing circuits that use MOSFETs with ultra-thin oxides.     

Oxide roughness effect on tunneling current of MOS diodes

Two-dimensional (2-D) device simulation is used to investigate the tunneling current of metal ultra-thin-oxide silicon tunneling diodes with different oxide roughness. With the conformal nature of ultrathin oxide, the tunneling current density is simulated in both direct tunneling and Fowler-Nordheim (FN) tunneling regimes with different oxide roughness. The results show that oxide roughness dramatically enhances the tunneling current density and the 2-D electrical effect is responsible for this increment of tunneling current density. Furthermore, a set of devices with controlled oxide roughness is fabricated to verify the simulation results and our model qualitatively agrees with the experiment results.     

Modeling study of ultrathin gate oxides using direct tunnelingcurrent and capacitance-voltage measurements in MOS devices

Using both quantum mechanical calculations for the silicon substrate and a modified WKB approximation for the transmission probability, direct tunneling currents across ultra-thin gate oxides of MOS structures have been modeled for electrons from the inversion layers in p-type Si substrates. The modeled direct tunneling currents have been compared to experimental data obtained from nMOSFET's with direct tunnel gate oxides. Excellent agreement between the model and experimental data for gate oxides as thin as 1.5 nm has been achieved. Advanced capacitance-voltage techniques have been employed to complement direct tunneling current modeling and measurements. With capacitance-voltage (C-V) techniques, direct tunneling currents can be used as a sensitive characterization technique for direct tunnel gate oxides. The effects of both silicon substrate doping concentration and polysilicon doping concentration on the direct tunneling current have also been studied as a function of applied gate voltage     

Physically based quantum-mechanical compact model of MOS devices substrate-injected tunneling current through ultrathin (EOT /spl sim/ 1 nm) SiO/sub 2/ and high-/spl kappa/ gate stacks

Building on a previously presented compact gate capacitance (C/sub g/-V/sub g/) model, a computationally efficient and accurate physically based compact model of gate substrate-injected tunneling current (I/sub g/-V/sub g/) is provided for both ultrathin SiO/sub 2/ and high-dielectric constant (high-/spl kappa/) gate stacks of equivalent oxide thickness (EOT) down to /spl sim/ 1 nm. Direct and Fowler-Nordheim tunneling from multiple discrete subbands in the strong inversion layer are addressed. Subband energies in the presence of wave function penetration into the gate dielectric, charge distributions among the subbands subject to Fermi-Dirac statistics, and the barrier potential are provided from the compact C/sub g/-V/sub g/ model. A modified version of the conventional Wentzel-Kramer-Brillouin approximation allows for the effects of the abrupt material interfaces and nonparabolicities in complex band structures of the individual dielectrics on the tunneling current. This compact model produces simulation results comparable to those obtained via computationally intense self-consistent Poisson-Schro/spl uml/dinger simulators with the same MOS devices structures and material parameters for 1-nm EOTs of SiO/sub 2/ and high-/spl kappa//SiO/sub 2/ gate stacks on (100) Si, respectively. Comparisons to experimental data for MOS devices with metal and polysilicon gates, ultrathin dielectrics of SiO/sub 2/, Si/sub 3/N/sub 4/, and high-/spl kappa/ (e.g., HfO/sub 2/) gate stacks on (100) Si with EOTs down to /spl sim/ 1-nm show excellent agreement.     

高场势垒调制效应及其对陷阱测试分析的影响

高场应力条件下，ＶＬＳＩ／ＵＬＳＩ ＭＯＳ结构场发射极附近的镜像力效应和半导体／氧化层界面附近半导体一侧的表面量子化效应都将影响ＭＯＳ结构的高场隧穿势垒高度及形状。本文研究了这种高场势垒调制效应及其对ＭＯＳ结构高场隧穿特性和陷阱测试分析的影响，并给出了初步的修正分析方法。     

栅隧穿电流分量研究

MOS器件尺寸缩减,导致栅氧化层厚度急剧减小,引起栅隧穿电流的迅速增大,对MOS器件特性产生了很大影响。该文基于此,重点分析和研究了栅隧穿电流分量及其特性,并针对四端MOS器件给出了相应的栅隧穿电流分量测试原理及构思。     

The effects of interfacial sub-oxide transition regions andmonolayer level nitridation on tunneling currents in silicondevices

Direct tunneling (D-T) in Si metal-oxide-semiconductor (MOS) devices having 1.8 to 3 nm thick gate oxides is reduced approximately tenfold by monolayer Si-dielectric interface nitridation with respect to devices with nonnitrided interfaces. The reduction is independent of gate oxide-equivalent thickness, and gate or substrate injection, and extends into the Fowler-Nordheim tunneling (F-N-T) regime for thicker oxides as well. A barrier layer model, including sub-oxide transition regions, has been developed for the interface electronic structure for tunneling calculations using X-ray photoelectron spectroscopy data. These calculations provide a quantitative explanation for the observed tunneling current reductions