High-speed and low-power CMOS priority encoders

The design of two high-performance priority encoders is presented. The key techniques for high speed are twofold. First, a multilevel look-ahead structure is developed to shorten the critical path effectively. Second, this look-ahead structure is realized efficiently by the NP Domino CMOS logic, and all the dynamic gates have a parallel-connected circuit structure. For high speed and low power at the same time, the series-connected circuit structure is adopted in the less critical paths to reduce the switching activity, but such a design needs to cascade two n-type dynamic gates directly resulting in the race problem. A special circuit technique is utilized to rescue this problem. Several 32-bit priority encoders are designed to evaluate the feasibility of the proposed techniques. The best new design realizes a three-level look-ahead structure, and it achieves 65% speed improvement, 20% layout area reduction, and 30% power reduction simultaneously as compared to the conventional design with a simple look-ahead structure     

Design techniques for single-low-V/sub DD/ CMOS systems

In this paper, a new CMOS design scheme called the single-low-V/sub DD/ CMOS (SLVCMOS) is proposed. With this scheme, a CMOS design implemented in a multi-V/sub TH/ CMOS technology can be operated with a very low external supply voltage, say 0.5-V, with a sleep current at the level of only picoampere per gate. The key items for a single-chip SLVCMOS design include a sleepless mixed-V/sub TH/ flip-flop, a boosted sleeping clock signal, and three low-power hard blocks. Analysis shows that additional benefits of using the SLVCMOS include higher performance and lower power consumption in the active mode, smaller leakage current in the sleep mode, shorter wake-up time and reduced wake-up energy during the sleep-to-active transition, and a reduced number of sleep-control signals, saving precious routing resources and reducing the chip area. A dual-rail SLVCMOS cell library and two test chips, one 32-b RISC core and the other verifying the design of hard blocks, are designed and implemented to show the feasibility of the proposed design scheme and the design techniques.     

变压器耦合的4.6GHz高性能正交CMOS压控振荡器设计

设计一种采用平面螺旋变压器作为耦合终端的CMOS电感电容正交压控振荡器,该正交VCO采用SMIC 0.18 um 数模混合&RF 1P6M CMOS工艺进行了流片验证。测试结果表明：电路在1.8 V电源供电和工作频率为4.6 GHz时,相位噪声为-125.7 dBc/Hz@1MHz,核心直流功耗仅为10 mW。根据时域的输出波形,测量的相位误差大约为1.5°,输出功率约为-2dBm。芯片的工作频率为4.36-4.68 GHz,调谐范围为320MHz(7.0％),电路的优值为-189dB。     

Design of a 4.6 GHz high-performance quadrature CMOS VCO using transformer couple

A CMOS quadrature LC-tank voltage-controlled oscillator topology which uses a planar spiral trans-former as coupling elements has been implemented in mixed-signal and RF 1P6M 0.18μm CMOS technology of SMIC. The measured phase noise is -125.7 dBc/Hz at an offset frequency of 1 MHz from the carrier of 4.6 GHz while the VCO core circuit draws only of 10 mW from a 1.8 V supply. The measured phase error is approximately 1.5° based on the time domain outputs and the output power is about -2 dBm. The VCO can cover the frequency range of 4.36-4.68 GHz. The tuning range is 320 MHz (7.0%) and the FOM is -189 dB.     

Design techniques for high-frequency CMOS switched-capacitorfilters using non-op-amp-based unity-gain amplifiers

A fully differential non-op-amp-based unity-gain amplifier (UGA) is proposed, whose 3-dB frequency can be as high as 250 MHz in 3.5-μm p-well CMOS technology. The purpose is to develop a new design concept for high-frequency switched-capacitor (SC) filters which uses balanced non-op-amp type UGAs with tunable gain to replace conventional op-amp-based unity-gain buffers (UGBs). The proposed UGA has a normal gain of unit, but it has a greater bandwidth, better setting behavior, smaller chip area, and less transistors than op-amp-based UGB. The new UGA also has a fully differential balanced configuration. The balanced configuration and proper predistortion by CAD tools can reduce the error due to linear parasitic capacitances. Experimental results prove the capability of the proposed structures in the realization of high-frequency SC filters over the megahertz range     

Ultra-low-Voltage high-performance CMOS VCOs using transformer feedback

A transformer-feedback voltage-controlled oscillator (TF-VCO) is proposed to achieve low-phase-noise and low-power designs even at a supply below the threshold voltage. The advantages of the proposed TF-VCO are described together with its detailed analysis and its cyclo-stationary characteristic. Two prototypes using the proposed TF-VCO techniques are demonstrated in a standard 0.18-/spl mu/m CMOS process. The first design using two single-ended transformers is operated at 1.4 GHz at a 0.35-V supply using PMOS transistors whose threshold voltage is around 0.52 V. The power consumption is 1.46 mW while the measured phase noise is -128.6 dBc/Hz at 1-MHz frequency offset. Using an optimum differential transformer to maximize quality factor and to minimize the chip area, the second design is operated at 3.8 GHz at a 0.5-V supply with power consumption of 570 /spl mu/W and a measured phase noise of -119 dBc/Hz at 1-MHz frequency offset. The figures of merits are comparable or better to that of other state-of-the-art VCO designs operating at much higher supply voltage.     

Design techniques for a low-power low-cost CMOS A/D converter

A 10 bit 200 kHz algorithmic analog-to-digital converter (ADC) was designed to demonstrate design techniques for low-power low-cost CMOS integrated systems. A switched-bias power-reduction technique reduces the total system power by 10%. A layout technique employing extra thin poly-layer lines instead of conventional dummy devices reduces plasma-induced comparator offsets. Based on a standard digital CMOS process with a single poly layer, the ADC adopts metal-to-metal capacitors for internal charge storage. The experimental ADC was fabricated in a 0.6 μm single-poly double-metal n-well CMOS technology, and showed a power consumption of 7 mW and a signal-to-noise-and-distortion ratio (SNDR) of 53 dB at the Nyquist sampling rate with a 3.3 V single supply voltage. The measured differential and integral nonlinearities of the prototype are less than ±0.8 and ±1.8 LSB, respectively     

CMOS four-quadrant multiplier using bias feedback techniques

A new wide-range CMOS four-quadrant multiplier using the bias feedback techniques is presented. Simulation results show that for a power supply of ±5 V, the linear range is over 14 V and the linearity error is less than 1% over a 13 V input range. Experimental results show that the linear range is over ±1 V. The results will be useful in analog signal processing applications     

A high-performance CMOS 70-MHz palette/DAC

A VLSI circuit has been developed that combines dual-ported RAMs and three high-speed 8-b digital-to-analog converters (DACs). It is known as a palette/DAC. A 6-2 segmented DAC architecture improves differential linearity and monotonicity. The current-source cell uses a cascode device to improve the DAC's linearity. A reference current, set by an on-chip bandgap reference voltage generator, and its associated distribution scheme eliminate the negative effects of threshold mismatches between current source cells, supply line resistance, and noise. The maximum conversion rate is 70 MHz with typical DC differential nonlinearity of 0.48 LSB (least significant bit). The 253-mil/SUP 2/ is designed on a double-metal CMOS process and consumes 1.2 W of power.     

SOS/CMOS as a high-performance LSI device

To realize a high-performance LSI, the devices used should satisfy the following requirements: 1) high-speed operation, 2) low power consumption, 3) easy designability, and 4) high integration capability. SOS/CMOS has been examined both experimentally and theoretically for these aspects. Ideal CMOS operation withtau_{pd} sim 100ps with 0.1-pJ energy required to switch an inverter is obtained. 1-GHz operation is confirmed on dynamic 1/16 frequency dividers with 1.0-µm effective channel-length devices. Using the same device, a maximum multiplying time,tau_{mul} sim 25ns at 5 V with 15-mW average power at 10⁷multiplications/s is obtained on a 4 × 4 parallel multiplier. The above result agrees with circuit simulation predictions without including stray capacitance associated with the wiring. The same simulation predictstau_{mul} sim 60ns with a maximum power dissipation of 200 mW at 16-MHz operation for a 16 × 16 parallel multiplier. This prediction is also confirmed experimentally. These facts indicate good designability of SOS/CMOS. For larger scale integration capability estimation, power dissipation and wiring delay were examined theoretically for bulk NMOS, bulk CMOS, and SOS/CMOS. The results indicate that for smaller scale integration, bulk NMOS and SOS/CMOS operate faster than bulk CMOS. However, for larger scale integration, SOS/CMOS operates faster than bulk CMOS which, in turn, operates faster than bulk NMOS.     

Precise CMOS current sample/hold circuits using differential clockfeedthrough attenuation techniques

New CMOS current sample/hold (CSH) circuits capable of overcoming the accuracy limitations in conventional circuits without significantly reducing operating speed are proposed and analyzed. A novel differential clock feedthrough attenuation (DCFA) technique is developed to attenuate the signal-dependent clock feedthrough errors. Unlike conventional techniques, the DCFA circuit allows the use of dynamic mirror techniques, and results in no additional finite output resistance errors or device mismatch errors. The test chip of the proposed fully differential CSH circuit with multiple outputs has been fabricated in 1.2-μm CMOS technology. Using a single 5-V power supply, experimental results show that the signal-dependent clock feedthrough error current is less than ±0.4 μA for the input currents from -550 μA to 550 μA. The acquisition time for a 900-μA step transition to 0.1% settling accuracy is 150 ns. For a 410-μA_p-p input at 250 MHz with the fabricated fully-differential CSH circuit clocked at 4 MHz, a total harmonic distortion of -60 dB, and a signal-to-noise ratio of 79 dB have been obtained. The active chip area and power consumption of the fabricated CSH circuit are 0.64 mm² and 20 mW, respectively. Both simulation and experimental results have successfully verified the functions and performance of the proposed CSH circuits     

Design considerations for a high-performance 3-/spl mu/m CMOS analog standard-cell library

Several design aspects of a high-performance analog cell library implemented in 3-/spl mu/m CMOS are described, including an improved central biasing scheme, a circuit for high-swing cascode biasing, an impact ionization shielding technique, and a family of operational transconductance amplifiers including a precision low offset-voltage amplifier utilizing lateral bipolar transistors.     

CMOS four-quadrant current multiplier using switched current techniques

A new CMOS four-quadrant switched current multiplier, operating from a single 3V power supply and employing two-phase clocking scheme, is proposed. The circuit is designed to perform one multiplication per clock cycle. SPICE simulations using 0.5 /spl mu/m CMOS process parameters have been carried out to verify the multiplier performance.     

A high-speed 64K/spl times/4 CMOS DRAM using on-chip self-timing techniques

The duration of internal operation of this DRAM is controlled by on-chip self-timing signals. With this feature, the leading and trailing edges of the row address strobe are allowed to have timing windows of 16 and 11 ns, respectively, even at a minimum cycle time of 80 ns. A novel address decoding scheme, utilizing a combination of NMOS NOR row decoders, CMOS NAND column decoders, and common predecoders, is employed to realize a fast array access time and a small die. The RAM has been fabricated with a 1.2-/spl mu/m n-well CMOS technology, and has a 21.34-mm/SUP 2/ die. Typical row access and column address access times are 47 and 16 ns, respectively. The active power dissipation is 115 mW at 200-ns cycle time.     

Design of optical full encoders/decoders for code-based photonic routers

This paper demonstrates that standard multiplexers as generalized Mach-Zehnder interferometers or waveguide grating routers can be designed to generate/process a set of orthogonal optical codes (OCs) with very high-correlation performances. The same device can be used at the ingress node of a generalized multiprotocol label switching network to generate the photonic labels and at each routing node to perform all the correlations simultaneously. To enhance the code cardinality, without increasing the code length, this paper shows that it is possible to use the proposed encoder/decoder architectures to generate/process multidimensional OCs.     

Design techniques for dynamic range improvement in CMOS circuitry

Circuit design techniques that improve the dynamic range of signal processing circuitry are discussed. These techniques use differential processing techniques to minimize the effect of correlated and low-frequency noise sources (including feedthrough from power supplies) and dc offset voltage.     

Design techniques and implementation of an 8-bit 200-MS/s interpolating/averaging CMOS A/D converter

The design issues and tradeoffs of a high-speed high-accuracy Nyquist-rate analog-to-digital (A/D) converter are described. The presented design methodology covers the complete flow from specifications to verified layout and is supported by both commercial and internally developed computer-aided design tools. The major decisions to be made during the converter's design at both the architectural and the circuit level are described and the tradeoffs are elaborated. The approach is demonstrated for a real-life test case, where a Nyquist-rate 8-bit 200-MS/s 4-2 interpolating/averaging A/D converter was developed in a 0.35-/spl mu/m CMOS technology. The signal-to-noise-plus-distortion ratio at 40 MHz is 42.7 dB and the total power consumption is 655 mW.     

Generalized-and efficient techniques for the design of CMI andother encoders

The coded mark inversion (CMI) line code is becoming popular for wide-band fiber-optic systems. The advantages of the CMI include DC balance and guaranteed transition density, which simplifies timing recovery. Previous CMI encoder implementations typically relied on a mixture of digital, analog, and delay-line techniques. The encoders proposed are digital state machines that allow elegant, accurate, and efficient implementation with gate arrays or discrete logic components. A general approach is then discussed for designing state machines of the type described here. Such state machines may be used to implement other codes, such as Manchester, RZ, and BnZS codes     

Design techniques for VHF/UHF high-Q tunable bandpass filters usingsimple CMOS inverter-based transresistance amplifiers

In this paper, CMOS inverter-based wideband transresistance R_m amplifiers are proposed and analyzed. Using the R_m amplifiers, tunable VHF/UHF R_m-C bandpass biquadratic filters can be designed. In these filters, the center frequency f₀ can be post-tuned by adjusting the control voltages of the R_m amplifiers. The pseudodifferential configuration uses the extra inversely connected and self-shorted inverters for Q enhancement. Experimental results have shown that the center frequency f₀ of the single-ended-output R_m-C bandpass biquad is 386 MHz (258 MHz) and Q=1.195 (Q=1.012) for ±2.5 V (±1.5 V) supply voltage. The power consumption is 24.83 mW (3.42 mW), and the dynamic range is 61 dB (55.5 dB). For pseudodifferential-output high-Q configuration, the measured quality factor Q can be as high as 360 with f₀=222.7 MHz. When Q=94, the power consumption is 56.2 mW and the measured dynamic range is 57.8 dB for 12.5 V supply voltage     

Design of high-performance compact CMOS distributed amplifiers with on-chip patterned ground shield inductors

A CMOS distributed amplifier incorporating on-chip patterned ground shield (PGS) spiral inductors has been developed using a standard low cost 0.25 μm CMOS process. Measured results show that this distributed amplifier has an average gain of 7 dB, return loss of more than 10 dB, and noise figure between 4.1-6.1 dB across DC 11 GHz. The amplifier occupies a small chip area of only 1.2 x 0.8 mm², including RF pads. These represent the best results for 0.25 μm CMOS distributed amplifiers and demonstrate that miniaturisation and high performance can be achieved for CMOS distributed amplifiers and other wideband RFICs by implementing on-chip PGS inductors.