三维可重构阵列互连资源在线分布式容错方法

设计了一种新型三维可重构阵列结构, 并且对其互连资源在线分布式容错方法进行了研究。系统由相同的功能细胞和开关块以三维结构组成, 通过在线输入测试向量对互连线进行故障定位, 并且实现故障连线分层自修复。以四位加法/减法器电路为设计实例, 对可重构阵列功能和容错能力进行验证。实验结果表明该方法可有效完成容错, 且时间开销小、容错能力强、资源利用率高。     

可重构阵列自主容错方法研究

设计了一种具有故障自诊断和自修复能力的可重构阵列单元结构。在功能细胞单元内部实现分布式的故障自诊断,在测试到故障后,可以自主地将距故障单元最近的空闲单元进行替换,接着自动取消受故障影响的线网,并在新的布线端点间对这些线网重新布线。以4位并行乘法器为例,实验结果证明了可重构单元阵列的故障自修复能力,并验证其重构时间较短且可靠性较高。     

胚胎型仿生电路中具有自修复性能的存储器设计

胚胎型仿生电路是一种芯片级容错数字电路,其工作机制为汲取生物体生长过程的灵感从而使得数字系统具有自主容错能力。该电路是由二维电子细胞阵列组成,文中分析了这种数字电路的结构和容错机制,讨论了细胞的主要组成部件的设计,并基于海明码(Hamming Code)为细胞中的存储器设计了一种具有自检测和自修复能力的结构。最后,以4×4乘法器为应用实例,通过仿真实验验证了细胞中存储器的自诊断、自修复能力和该仿生电路的自修复能力。     

基于SRAM型FPGA的实时容错自修复系统设计方法

为提高辐射环境中电子系统的可靠性,提出了一种基于SRAM型FPGA的实时容错自修复系统结构和设计方法。该设计方法采用粗粒度三模冗余结构和细粒度三模冗余结构对系统功能模块进行容错设计;将一种细粒度的故障检测单元嵌入到各冗余模块中对各冗余模块进行故障检测;结合动态部分重构技术可在不影响系统正常工作的前提下实现故障模块的在线修复。该设计结构于Xilinx Virtex誖-6 FPGA中进行了设计实现,实验结果表明系统故障修复时间和可靠性得到显著提高。     

用于可重构硬件容错过程的辅助布线电路设计

目前可重构硬件的容错机制大多采用重新布局布线的方法,但是需要很长的重布线时间,难以满足工程应用的需要.为此,提出一种支持可重构单元阵列快速容错的辅助布线电路,该电路结构由二维的辅助布线模块构成,每个辅助布线模块可以读取并修改所在可重构单元的可编程开关配置数据.可重构单元阵列容错时,辅助布线电路代替外部软件执行故障线网的取消和线网重布线过程.以4位并行乘法器为例,证明了在系统容错时辅助布线电路可以有效地加速故障线网取消和重布线过程.     

一种具有自修复功能的容错数字电路

提出了一种针对数字电路的自修复容错方法。该方法基于胚胎细胞的可重构特性理论,用休眠细胞代替故障细胞的功能达到容错的目的。对应用实例的分析表明:在相同系统资源的情况下,所提出的方法在容错单元数上能达到整列排除法的4倍。     

环网处理器阵列的容错重构技术

高效的容错技术对于提高多处理器系统的可靠性至关重要。环网(Torus)是连接多处理器阵列的重要网络结构,而环网处理器阵列上的容错重构技术目前尚属空白。针对环网阵列的特殊连接方式,将环网阵列重构问题转化为矛盾图上求解最大独立集问题。矛盾图上的结点表示故障处理器的替换方案,而边代表了不同替换方案之间的不可共存特性。主要是根据三种不同的冗余处理器分布方案,设计生成矛盾图算法,求解最大独立集算法,以及由独立集生成逻辑处理器阵列算法,取得了令人满意的结果。实验结果表明,当阵列规模较小或故障率较低时,一行一列和十字型的冗余单元分布的重构能力较好;而随着阵列规模或故障率的增大,三种冗余单元分布策略的重构成功率都随之下降,但可通过增加冗余单元以及调整冗余分布来改善容错效果。此外,从实验结果中还可以看出,环网处理器阵列的容错能力显然优于网格(Mesh)处理器阵列。     

动态可重构总线数据传输管理方法设计与实现

为实现总线多通道数据并发高速传输与容错,解决故障状态下的总线数据动态重构问题,设计一种动态可重构总线数据传输管理方法。采用四体先入先出队列(FIFO)进行数据缓冲存储,利用通道故障状态表,通过4×32矩阵开关数据,传输管理阵列组织与4个FIFO缓冲区及所有有效通道间的数据传输。在8通道系统中的实验结果表明,最高通信速率可达到800 Mb/s,能对7个通道故障进行动态容错。     

考虑多传感器故障的可重构机械臂主动取代分散容错控制

针对可重构机械臂系统位置传感器和速度传感器多故障, 提出一种主动取代分散容错控制方法. 基于可重构机械臂的模块化属性, 设计正常工作模式下的分散神经网络控制器. 利用微分同胚原理将子系统结构进行非线性变换, 将传感器故障转化成伪执行器故障, 设计分散滑模观测器以对多传感器故障进行实时检测, 并利用其输出信号取代故障传感器信号, 实现了多传感器故障情形下可重构机械臂的主动容错控制. 仿真结果表明了所设计的容错控制方法的有效性.     

可重构系统的演化修复机制

利用演化算法实现系统自修复是一种新的容错设计思路,但是演化是一个非常耗时的过程.已有的演化容错系统多属于静态演化,演化过程仅发生在系统设计阶段,系统在运行过程中不具有演化修复的能力.这类演化容错系统虽然可以避免演化耗时,但是只能修复已知错误,无法修复未知错误.针对上述问题,文中提出一种基于动态演化的修复机制,容错系统采用可重构系统和被检测系统的耦合设计方案.当被检测系统出现故障时,可重构系统通过系统演化实现在线自修复.为了减少演化耗时,系统根据错误类型采取不同措施:如果出现已知错误,系统直接在预置配置库中搜索修复配置;如果出现未知错误,则通过动态演化在线生成修复配置,并更新预置配置库.最后,将该容错设计方案用于典型电路的故障模式.实验结果表明,文中提出的演化修复机制提高了系统运行的实时可靠性,预置配置库设计减少了演化耗时.     

A multipath network with cross links

A fault-tolerant multistage interconnection network, called the H-network, and a fault-tolerant control algorithm for this network are introduced. The novel feature of this network lies in its design, which has connections not only between switching elements of successive stages but also between switching elements of the same stage. The control algorithm is a simple modification of the destination tag algorithm, but it provides for fault tolerance and is dynamic in nature. It is shown that this design technique is effective in reducing hardware, improving fault tolerance, and giving better performance than other fault-tolerant networks with comparable hardware cost.     

Design of the EPLD-based reconfigurable fault-tolerant systems with cell-level redundancy

A procedure to design reconfigurable systems capable to recover their operability in the case of fault of an arbitrary EPLD cell or connection was proposed. The most important advantages of the procedure lie in the retention of the signal propagation delays guaranteeing system operability after reconfiguration, as well as in low redundancy of the fault-tolerant system which at the limit may correspond only to one standby cell. The package methods enable one to design fault-tolerant systems based on the closed intelligent core without their upgrading. Efficiency of the procedure was estimated, and possible limitations of its application were discussed.     

可重构机械臂反演时延分散容错控制

针对存在模型参数不确定性的可重构机械臂系统执行器故障,提出一种基于反演设计与时延技术相结合的容错控制方法.该方法利用反演设计的基本思想,通过神经网络补偿子系统动力学模型中的参数不确定项和关联项.利用时延控制的逼近能力来补偿执行器的故障,使得故障发生时能及时实现容错控制.该方法具有不需要在线进行故障诊断的特点,仿真结果表明了所提出控制方法的有效性.     

A Rigorous Approach to Fault-Tolerant Programming

The design of programs that are tolerant of hardware fault occurrences and processor crashes is investigated. Using a stable storage management system as a running example, a new approach is suggested for specifying, understanding, and verifying the correctness of fault-tolerant software. The approach extends previously developed axiomatic reasoning methods to the design of fault-tolerant systems by modeling faults as being operations that are performed at random time intervals on any computing system by the system's adverse environment.     

On the practicality of using intrinsic reconfiguration for fault recovery

Evolvable hardware (EHW) combines the powerful search capability of evolutionary algorithms with the flexibility of reprogrammable devices, thereby providing a natural framework for reconfiguration. This framework has generated an interest in using EHW for fault-tolerant systems because reconfiguration can effectively deal with hardware faults whenever it is impossible to provide spares. But systems cannot tolerate faults indefinitely, which means reconfiguration does have a deadline. The focus of previous EHW research relating to fault-tolerance has been primarily restricted to restoring functionality, with no real consideration of time constraints. In this paper, we are concerned with EHW performing reconfiguration under deadline constraints. In particular, we investigate reconfigurable hardware that undergoes intrinsic evolution. We show that fault recovery done by intrinsic reconfiguration has some restrictions, which designers cannot ignore.     

UML-based hardware/software co-design platform for dynamically partially reconfigurable network security systems

The dynamic partial reconfiguration technology of FPGA has made it possible to adapt system functionalities at run-time to changing environment conditions. However, this new dimension of dynamic hardware reconfigurability has rendered existing CAD tools and platforms incapable of efficiently exploring the design space. As a solution, we proposed a novel UML-based hardware/software co-design platform (UCoP) targeting at dynamically partially reconfigurable network security systems (DPRNSS). Computation-intensive network security functions, implemented as reconfigurable hardware functions, can be configured on-demand into a DPRNSS at run-time. Thus, UCoP not only supports dynamic adaptation to different environment conditions, but also increases hardware resource utilization. UCoP supports design space exploration for reconfigurable systems in three folds. Firstly, it provides reusable models of typical reconfigurable systems that can be customized according to user applications. Secondly, UCoP provides a partially reconfigurable hardware task template, using which users can focus on their hardware designs without going through the full partial reconfiguration flow. Thirdly, UCoP provides direct interactions between UML system models and real reconfigurable hardware modules, thus allowing accurate time measurements. Compared to the existing lower-bound and synthesis-based estimation methods, the accurate time measurements using UCoP at a high abstraction level can more efficiently reduce the system development efforts.     

Actuator fault-tolerant control design: Demonstration on a three-tank-system

Fault-tolerant control or reconfigurable control systems are generally based on a nominal control law associated with a fault detection and isolation module. A general review of techniques dealing with this problem is given and a new fault-tolerant control approach is presented. This method is based on the on-line estimation of an eventual fault and the addition of a new control law to the nominal control law in order to reduce the fault effect once this fault is detected and isolated. The performances of this method depend on the time delay between the occurrence of the fault and its detection and isolation. A modified approach is then proposed in order to avoid the problems generated by delays, false alarms or non-detection inherent to diagnosis techniques. These methods are applied to a pilot plant and their performances are compared and discussed.