A High Dynamic Range Programmable CMOS Front-End Filter with a Tuning Range from 1850 to 2400 MHz

This paper presents a highly programmable front-end filter and amplifier intended to replace SAW filters and low noise amplifiers (LNA) in multi-mode direct conversion radio receivers. The filter has a 42 MHz bandwidth, is tunable from 1850 to 2400 MHz, achieves a 5.8 dB NF, –25 dBm in-band 1-dB input compression point (ICP) and 0 dBm out-of-band ICP while drawing 26 mA from a 2.5 V supply.     

CMOS多路加权SAW滤波器高频模拟开关研究

报道了0.6μm CMOS 4路可编程加权高频模拟开关集成电路,其开关和加权功能分别由两个高跨导的N沟MOS晶体管实现。模拟开关连续可调的动态加权范围最大为21.3 dB,最小插入损耗约为-6 dB。在线功能测试表明,该集成电路可对中心频率在50~250 MHz范围内的声表面波(SAW)滤波器进行取样、加权、可编程加权叠加,可应用于多芯片模式组成的可编程声表面波滤波器。     

一种适用于多波段无线通信的品质因数增强型的CMOS射频滤波器

提出了一种使用品质因数增强型的有源电感的射频带通滤波器,描述了在宽射频频段上可调谐的品质因数增强型的有源电感设计技术,而且解释了与有源电感噪声和稳定性相关的问题.该滤波器采用0.18μm CMOS工艺制造,它所占用芯片的有效面积仅为150μm×200μm.测试结果表明:该射频滤波器中心频率为2.44GHz时,3dB带宽为60MHz,中心频率可在2.07～2.44GHz范围内调谐,1dB压缩点为-15dBm,而静态功耗为10.8mW;在中心频率为2.07GHz时,滤波器的品质因数可达到103.     

一种适用于多波段无线通信的品质因数增强型的CMOS射频滤波器

提出了一种使用品质因数增强型的有源电感的射频带通滤波器,描述了在宽射频频段上可调谐的品质因数增强型的有源电感设计技术,而且解释了与有源电感噪声和稳定性相关的问题.该滤波器采用0.18μm CMOS工艺制造,它所占用芯片的有效面积仅为150μm×200μm.测试结果表明:该射频滤波器中心频率为2.44GHz时,3dB带宽为60MHz,中心频率可在2.07～2.44GHz范围内调谐,1dB压缩点为-15dBm,而静态功耗为10.8mW;在中心频率为2.07GHz时,滤波器的品质因数可达到103.     

具有片上频率自动调谐功能的4MHz Gm-C滤波器

本文实现了一个应用于全集成L带DAB接收机的5阶Gm-C椭圆低通滤波器,该滤波器上集成了基于锁相环的片上频率自动调谐电路,使得该滤波器的截止频率可以准确控制在4MHz.该滤波器已经采用0.35μm CMOS工艺实现.测试结果表明,该滤波器的频率精度可以控制在1%以内,动态范围约为54dB,阻带抑制率大于40dB.该滤波器采用3.3V电源,消耗的电流约为13mA.     

一种高线性度2.4GHz CMOS LC压控振荡器

对影响压控振荡器(VCO)线性度的因素进行了研究,并提出了一种适用于2.4GHz ISM频段的高调节线性度的CMOS LC VCO结构。新的VCO结构采用两个控制端,分别控制一对p /n-well变容管和一对MOS变容管。该VCO输出两个波段,调节非线性度分别为1.45%和1.74%,总调节范围为2.33～2.72 GHz,功耗为15mW,芯片面积为534×540μm2。结果表明,新的电路结构使得VCO的调节非线性度降低到通常只用一对变容管的VCO的一半以下,同时极大地减小了调节范围内相噪声的波动,有效地提高ISM频段内多种无线通信标准的射频收发机的性能。     

A Linear CMOS OTA and Its Application to a 3.3V 20MHz High-Q gm-C Bandpass Filter

A design of a linear and fully-balanced operational transconductance amplifier (OTA) with improved high DC gain and wide bandwidth is presented.Derivative from a single common-source field effect transistor (FET) cascade and its DC I-V characteristics,the third-order coefficient g3 has been well compensated with a parallel FET operated in the triode region,which has even-odd symmetries between the boundary of the saturation and triode region.Therefore,for high linearity,a simple solution is obtained to increase input signal amplitude in saturation for the application of OTA continuous-time filters.A negative resistance load (NRL) technique is used for the compensation of parasitic output resistance and an achievement of a high DC-gain of the OTA circuits without extra internal nodes.Additionally,derivations from the ideal -90. phase of the gm-C integrator mainly due to a finite DC gain and parasitic poles will be avoided in the frequency range of interest.HSPICE simulation shows that the total harmonic distortion at 1Vp-p is less than 1% from a single 3.3V supply.As an application of the VHF CMOS OTA,a second-order OTA-C bandpass filter is fabricated using a 0.18μm CMOS process with two kinds of gate-oxide layers,which has achieved a center frequency of 20MHz,a 3dB-bandwidth of 180kHz,and a quality factor of 110.     

应用于高Q跨导-电容带通滤波器的线性跨导运放设计

设计了一种具有高的直流增益的宽带线性全差分跨导运放.一方面,并联一个工作在线性区的场效应管来补偿直流三阶系数,得到了一种应用于连续时间滤波器、增加跨导器饱和区输入信号幅度的简单方法.另一方面,结合负电阻电路提高了输出阻抗,实现高的直流增益而不需要额外的内部结点,并减小了因有限直流增益和寄生电容引起的相位偏差.将此全差分跨导运放应用于0.18μmCMOS工艺二阶带通滤波器,在3.3V电源电压、输入峰峰值1V时,HSPICE仿真结果的总谐波失真小于40dB,中心频率为20MHz,3dB带宽为0.18MHz,即Q为110.     

Design of CMOS VHF/RF Biquadratic Filters

In this paper, a class of CMOS biquadratic filter suitable to work at VHF/RF frequency range is presented. The proposed circuit has a simple structure which is analyzed and designed according to a universal G _m-C biquad filter. Simulation and experimental results show that these filters can work in GHz range and have wide tuning range.     

用于超外差接收机的低压、低功耗高动态范围CMOS线性可变增益放大器

针对超外差接收机的自动增益控制网络,设计了一种结构简单的低压、低功耗全差分可变增益放大器.它由6级子电路级联而成,提供范围为81dB的数字控制增益,每一档为3dB,增益误差小于0.5dB.该电路工作于中频300kHz下,工作电压为1.8V,功耗仅为1.35mW.采用TSMC 0.18μm 1P6M CMOS工艺制造,芯片面积约为0.24mm2,低功耗及小芯片面积使其极适用于便携式通信系统的应用.测试结果达到设计要求.     

用于超外差接收机的低压、低功耗高动态范围CMOS线性可变增益放大器

针对超外差接收机的自动增益控制网络,设计了一种结构简单的低压、低功耗全差分可变增益放大器.它由6级子电路级联而成,提供范围为81dB的数字控制增益,每一档为3dB,增益误差小于0.5dB.该电路工作于中频300kHz下,工作电压为1.8V,功耗仅为1.35mW.采用TSMC 0.18μm 1P6M CMOS工艺制造,芯片面积约为0.24mm2,低功耗及小芯片面积使其极适用于便携式通信系统的应用.测试结果达到设计要求.     

The Design of a 2-V 900-MHz CMOS Bandpass Amplifier

A 900 MHz low-power CMOS bandpassamplifier suitable for the applications of RFfront-end in wireless communication receiversis proposed and analyzed. In this design, thetemperature compensation circuit is used tostabilize the amplifier gain so that theoverall amplifier has a good temperaturestability. Moreover, the compact tunablepositive-feedback circuit is connected to theintegrated spiral inductor to generate thenegative resistance and enhance its value. The simple diode varactor circuit isadopted for center-frequency tuning. These twoimproved circuits can reduce the powerdissipation of the amplifier. An experimentalchip fabricated by 0.5 mdouble-poly-double-metal CMOS technologyoccupies a chip area of ; chip area. The measuredresults have verified the performance of thefabricated CMOS bandpass amplifier. Under a2-V supply voltage, the measured quality factoris tunable between 4.5 and 50 and the tunablefrequency range is between 845 MHz and 915 MHz. At , the measured is 20 dB whereas thenoise figure is 5.2 dB in the passband. Thegain variation is less than 4 dB in the rangeof 0–80^°C. The dc powerdissipation is 35 mW. Suitable amplifier gain,low power dissipation, and good temperaturestability make the proposed bandpass amplifierquite feasible in RF front-endapplications.     

一种用于MEMS电场传感器的CMOS可控增益前置放大电路

为了将基于MEMS技术的微型电场传感器与其信号处理电路集成在一个芯片上,设计了一种CMOS前置放大电路.该电路利用工作在线性区的长沟道MOSFET晶体管代替传统的无源器件做反馈来降低所占硅片面积,使用分流原理构建分流网络产生可编程的偏置电流来控制放大电路的增益.仿真结果表明该电路结构具有较好的线性度和很好的温度特性,长沟道晶体管的等效电阻与偏置电流相关,可以达到兆欧量级.     

A 1.2 V Rail-to-Rail Analog CMOS Rank-Order Filter with k-WTA Capability

In this paper, we design a rank-order filter with k-WTA capability for 1.2 V supply voltage. The circuit can find a rank order among a set of input voltages by setting different binary signals. Moreover, without modifying the circuit, the k-WTA function can be easily configured. The circuit has been designed using a 0.5 m DPDM CMOS technology. Seven input voltages are used to verify the performance of the circuit. The results of HSPICE post-layout simulation show that the response time of the circuit is 10 s for each rank-order operation, the input dynamic range is rail-to-rail, and the resolution is 10 mV for 1.2 V supply voltage. An experimental chip has been fabricated, in which accuracy of the comparator is measured as 40 mV for low-voltage operation. The dynamic power dissipation of the chip is 550 W.     

截止频率可调的CMOS低电压低功率高通滤波器

本文基于对传统的ＣＭＯＳ反相器的低电压工作状态的分析，提出了新颖的ＣＭＯＳ高通滤波器，其截止频率可以通过调节工作于亚阈值区的ＣＭＯＳ管的沟道导纳来实现连续可调。本文提出的电路结构简单，功耗极低，可全集成。文中设计结果经ＰＳＰＩＣＥ仿真验证是正确的。     

一种LC全集成、具有对称噪声滤波及宽调节范围的4.8GHz CMOS平衡振荡器

将对称噪声滤波技术应用到4.8GHz LC全集成VCO设计中.该VCO具有很低的相位噪声以及716MHz的调节范围,在SMIC 0.25μm单层多晶、五层金属、n阱 RF CMOS工艺上实现,在2.5V电源电压下工作电流仅为6mA,与常规VCO比较,在相同条件下,噪声性能改善了6dBc/Hz.芯片测试结果表明,在偏离4.8GHz载波1MHz的地方相位噪声为-123.66dBc/Hz,该设计在锁相环及其他消费类电子产品中有广泛应用.     

A 4.8GHz CMOS Fully Integrated LC Balanced Oscillator with Symmetrical Noise Filter Technique and Large Tuning Range

This paper presents a fully integrated 4.8GHz VCO with an invention——symmetrical noise filter technique.This VCO,with relatively low phase noise and large tuning range of 716MHz,is fabricated with the 0.25μm SMIC CMOS process.The oscillator consumes 6mA from 2.5V supply.Another conventional VCO is also designed and simulated without symmetrical noise filter on the same process,which also consumes 6mA current and is with the same tuning.Simulation result describes that the first VCO’ phase noise is 6dBc/Hz better than the latter’s at the same offset frequency from 4.8GHz.Measured phase noise at 1MHz away from the carrier in this 4.8GHz VCO with symmetrical noise filter is －123.66dBc/Hz.This design is suitable for the usage in a phase-locked loop and other consumer electronics.It is amenable for future technologies and allows easy porting to different CMOS manufacturing process.     

一种新型的Q值与L值可相互独立调谐的低噪声有源电感

提出了一种新型的品质因数(Q)与电感值(L)可相互独立调谐的低噪声有源电感。该电感主要由双回转器、调制支路、可调反馈电阻、跨导增强支路和噪声抑制单元构成。其中,双回转器是由第一回转回路和第二回转回路并联而成,获得了大电感值;调制支路不仅能减小等效并联电阻,提高Q值,还可实现对电感值的大范围调谐;可调反馈电阻不仅能增大Q值,还能实现对Q值的独立调节,也能补偿因调谐L值引起的Q值的变化;跨导增强支路和噪声抑制单元分别降低了第一回转回路和第二回转回路的噪声,从而降低有源电感的整体噪声。最终,通过上述电路模块的紧密配合及所配置的三个外部调控端电压的深度协作,实现了Q值与L值可相互独立调谐以及低噪声的优异特性。仿真结果表明,该有源电感在3.8 GHz频率下,Q峰值可从674调节到5 083,调谐率为153.2%,而L值变化率仅为0.3%;在3.65 GHz下,L值可由6.1 nH调节到15.5 nH,调谐率高达87%,而与之对应的Q值的变化率仅为3.7%;在2~6 GHz范围内,有源电感的最大和最小输入噪声分别为5.29 nV/Hz和1.75 nV/Hz。     

A New CMOS Image Sensor with a High Fill Factor and the Dynamic Digital Double Sampling Technique

介绍了基于0.35μm工艺设计的单片CMOS图像传感器芯片.该芯片采用有源像素结构,像素单元填充因数可达到43%,高于通常APS结构像素单元30%的指标.此外还设计了一种数字动态双采样技术,相对于传统的双采样技术(固定模式噪声约为0.5%),数字动态双采样技术具有更简洁的电路结构和更好抑制FPN噪声的效果.传感器芯片通过MPW计划采用Chartered 0.35μm数模混合工艺实现.实验结果表明芯片工作良好,图像固定模式噪声约为0.17%.     

一种具有高填充因数和动态数字双采样技术的CMOS图像传感器

介绍了基于0.35μm工艺设计的单片CMOS图像传感器芯片.该芯片采用有源像素结构,像素单元填充因数可达到43%,高于通常APS结构像素单元30%的指标.此外还设计了一种数字动态双采样技术,相对于传统的双采样技术(固定模式噪声约为0.5%),数字动态双采样技术具有更简洁的电路结构和更好抑制FPN噪声的效果.传感器芯片通过MPW计划采用Chartered 0.35μm数模混合工艺实现.实验结果表明芯片工作良好,图像固定模式噪声约为0.17%.