基于CTGAL电路的绝热4-2压缩器和乘法器设计

通过对并行乘法器和钟控传输门绝热逻辑(Clocked Transmission Gate Adiabatic Logic,CTGAL)电路工作原理及结构的研究,提出了基于CTGAL电路的绝热4-2压缩器的设计方案,与传统CMOS逻辑的4-2压缩器相比,此压缩器节省平均功耗约87%.在此基础上,进一步设计了4×4位绝热乘法器,HSPICE模拟结果表明了所设计的电路具有正确的逻辑功能和显著的能量恢复特性.     

采用三相电源的互补传输管绝热逻辑电路

提出了一种由三相电源驱动的新绝热逻辑电路——complementary pass- transistor adiabatic logic (CPAL ) .电路由CPL电路完成相应的逻辑运算,由互补传输门对输出负载进行绝热驱动,电路的整体功耗较小.指出选取合适的输出驱动管的器件尺寸可进一步减小CPAL电路的总能耗.设计了仅由一个电感和简单控制电路组成的三相功率时钟产生电路.为了验证提出的CPAL电路和时钟产生电路,设计了8bit全加器进行模拟试验.采用MO-SIS的0 .2 5μm CMOS工艺,在5 0～2 0 0 MHz频率范围内,CPAL全加器的功耗仅为PFAL电路和2 N - 2 N2 P电路的5 0 %和35 % .     

采用三相电源的互补传输管绝热逻辑电路

提出了一种由三相电源驱动的新绝热逻辑电路--complementary pass-transistor adiabatic logic(CPAL).电路由CPL电路完成相应的逻辑运算,由互补传输门对输出负载进行绝热驱动,电路的整体功耗较小.指出选取合适的输出驱动管的器件尺寸可进一步减小CPAL电路的总能耗.设计了仅由一个电感和简单控制电路组成的三相功率时钟产生电路.为了验证提出的CPAL电路和时钟产生电路,设计了8bit全加器进行模拟试验.采用MOSIS的0.25μm CMOS工艺,在50～200MHz频率范围内,CPAL全加器的功耗仅为PFAL电路和2N-2N2P电路的50%和35%.     

采用二相功率时钟的无悬空输出绝热CMOS电路

分析了PAL及PAL-1电路中输出悬空对电路性能的影响,强调在绝热电路设计中消除悬空输出的重要性．提出了两种新的结构互补且无悬空输出的绝热电路．PSPICE模拟证明它们能有效实现能量恢复,并使输出信号在整个有效输出期始终处于箝位状态．     

采用二相功率时钟的无悬空输出绝热CMOS电路

分析了 PAL 及 PAL- 1电路中输出悬空对电路性能的影响 ,强调在绝热电路设计中消除悬空输出的重要性 .提出了两种新的结构互补且无悬空输出的绝热电路 .PSPICE模拟证明它们能有效实现能量恢复 ,并使输出信号在整个有效输出期始终处于箝位状态     

采用二相功率时的无悬空输出绝热CMOS电路

分析了PAL及PAL－1电路中输出悬空对电路性能的影响,强调在绝热电路设计中消除悬空输出的重要性。提出了两种新的结构互补且无悬空输出的绝热电路,PSPICE模拟证明它们能有效实现能量恢复,并使输出信号在整个有效输出期始终处于箝位状态。     

基于绝热逻辑的低功耗乘法器电路设计

基于绝热开关理论的能量回收逻辑与传统的静态CMOS逻辑相比,能够大大减少电路的功率消耗。这里介绍了一种使用单相正弦电源时钟的能量回收逻辑,分别用静态CMOS逻辑和这种能量回收逻辑设计,并仿真了一个两位乘法器电路,比较了这两种电路的性能。研究表明,采用能量回收逻辑设计的乘法器显著降低了电路的功率消耗。     

绝热CMOS与传统CMOS接口电路的设计

为了将绝热CMOS电路嵌入到传统电路系统中替代耗能较大的部件，本文研究并设计绝热CMOS电路和传统CMOS电路两者之间的接口电路：传统CMOS到绝热CMOS （Traditional CMOS to Adiabatic CMOS, TC/AC）的接口电路、绝热CMOS到传统CMOS （Adiabatic CMOS to Traditional CMOS, AC/TC）的接口电路。这样传统CMOS电路可以通过TC／AC接口电路来驱动绝热CMOS电路，绝热CMOS电路可以通过AC／TC接口电路来驱动传统CMOS电路，从而可以利用具低功耗特性的绝热CMOS电路来降低整个电路系统的功耗，增强绝热CMOS电路的实用性。最后计算机模拟验证了TC／AC接口电路和AC／TC接口电路逻辑功能的正确性。     

静态绝热CMOS记忆电路和信息恢复能力

通过等效电路分析、考虑参数选取和整体时序电路的实现 ,提出具有信息恢复能力的静态绝热 CMOS记忆电路 .认为整体绝热电路结构最好融合输入、输出电路和记忆电路、时序电路为一体 ,由主触发器集合和从触发器集合相互连接构成 ,其中含有输出和反馈从触发器 .采用绝热取样输入电路实现信息记忆单元接收代码和保存信息时将信息单元与外输入隔离 .还设计出 5 4 2 1BCD码 10进制和 7进制可变计数器 (带有进位输出从触发器和反馈清 0从触发器 ) ,用计算机模拟程序检验电路的正确性     

模式可选的新型能量回收电路

基于绝热计算原理的能量回收电路是克服数字电路功耗CV2壁垒的有效途径.提出了一种MOCAL (Mode Optional CAL)电路,在CAL的基础上增加了对电路工作模式的控制,从而弥补了大部分传统绝热电路的缺陷,可以直接用来替换CMOS电路中的相应部分,降低了功耗,并节省了芯片面积.采用MOCAL结构,经过HSPICE验证,并且与CAL反相器链的功耗进行了比较.结果显示,在20 MHz频率下,MOCAL反相器链的功耗损失仅为CAL的23%,证明了设计的有效性.     

钟控准静态能量回收逻辑电路

钟控准静态能量回收逻辑 (clocked quasi- static energy recovery logic,CQSERL)只在输入信号导致输出状态发生变化的情况下才对电路节点充电 (或者回收 ) ,不需要在每个功率时钟周期循环充电和回收操作 ;CQSERL是单端输入输出逻辑 ,减小了电路实现代价 .设计了 4位 QSERL 串行进位加法器 (RCA)电路 ,和相应的 CMOS电路进行了功耗比较 .功率时钟为 10 MHz时 ,CQSERL 电路功耗是对应 CMOS电路的 35 % .流片实现了一个简单结构的正弦功率时钟产生电路 ,功率时钟的频率和相位与外接系统时钟相同     

准静态单相能量回收逻辑

提出了一种新的准静态单相能量回收逻辑,其不同于以往的能量回收逻辑,真正实现了单相功率时钟,且不需要任何额外的辅助控制时钟,不但降低了能耗,更大大简化了时钟树的设计.该逻辑还可以达到两相能量回收逻辑所具有的速度.设计了一个8位对数超前进位加法器,并分别用传统的静态CMOS逻辑、钟控CMOS绝热逻辑(典型的单相能量回收逻辑)和准静态单相能量回收逻辑实现.采用128组随机产生的输入测试向量的仿真结果表明:输入频率为10MHz时,准静态能量回收逻辑的能耗仅仅是传统静态CMOS逻辑的45%;当输入频率大于2MHz时,可以获得比时钟控CMOS绝热逻辑更低的能耗.     

准静态单相能量回收逻辑

提出了一种新的准静态单相能量回收逻辑,其不同于以往的能量回收逻辑,真正实现了单相功率时钟,且不需要任何额外的辅助控制时钟,不但降低了能耗,更大大简化了时钟树的设计.该逻辑还可以达到两相能量回收逻辑所具有的速度.设计了一个8位对数超前进位加法器,并分别用传统的静态CMOS逻辑、钟控CMOS绝热逻辑(典型的单相能量回收逻辑)和准静态单相能量回收逻辑实现.采用128组随机产生的输入测试向量的仿真结果表明:输入频率为10MHz时,准静态能量回收逻辑的能耗仅仅是传统静态CMOS逻辑的45%;当输入频率大于2MHz时,可以获得比时钟控CMOS绝热逻辑更低的能耗.     

Design of a DTCTGAL circuit and its application

By research on the switch-signal theory for multiple-valued logic circuits, the theory of three essential elements and the principle of adiabatic circuits, a design scheme for a double power clock ternary clocked transmission gate adiabatic logic (DTCTGAL) circuit is presented. The energy injection and recovery can be conducted by the bootstrapped NMOSFET, which makes the circuit maintain the characteristics of energy recovery as well as multiple-valued input and output. An XOR/XNOR circuit based on DTCTGAL is also presented using this design scheme. Finally, using the parameters of a TSMC 0.25 μm CMOS device, PSPICE simulation results indicate that the proposed circuits have correct logic and significant low power characteristics.     

True single-phase adiabatic circuitry

Dynamic logic families that rely on energy recovery to achieve low energy dissipation control the flow of data through gate cascades using multiphase clocks. Consequently, they typically use multiple clock generators and can exhibit increased energy consumption on their clock distribution networks. Moreover, they are not attractive for high-speed design due to their high complexity and clock skew management problems. In this paper, we present TSEL, the first energy-recovering (a.k.a. adiabatic) logic family that operates with a single-phase sinusoidal clocking scheme. We also present SCAL, a source-coupled variant of TSEL with improved supply voltage scalability and energy efficiency. Optimal performance under any operating conditions is achieved in SCAL using a tunable current source in each gate. TSEL and SCAL outperform previous adiabatic logic families in terms of energy efficiency and operating speed. In layout-based simulations with 0.5 μm standard CMOS process parameters, 8-bit carry-lookahead adders (CLAs) in TSEL and SCAL function correctly for operating frequencies exceeding 200 MHz. In comparison with corresponding CLAs in alternative logic styles that operate at minimum supply voltages, CLAs designed in our single-phase adiabatic logic families are more energy efficient across a broad range of operating frequencies. Specifically, for clock rates ranging from 10 to 200 MHz, our andbit SCAL CLAs are 1.5 to 2.5 times more energy efficient than corresponding adders developed in PAL and 2N2P and 2.0 to 5.0 times less dissipative than their purely combinational or pipelined CMOS counterparts     

PMOS-Only Sleep Switch Dual-Threshold Voltage Domino Logic in Sub-65-nm CMOS Technologies

A circuit technique is proposed in this paper for simultaneously reducing the subthreshold and gate oxide leakage power consumption in domino logic circuits. Only p-channel sleep transistors and a dual-threshold voltage CMOS technology are utilized to place an idle domino logic circuit into a low leakage state. Sleep transistors are added to the dynamic nodes in order to reduce the subthreshold leakage current by strongly turning off all of the high-threshold voltage transistors. Similarly, the sleep switches added to the output nodes suppress the voltages across the gate insulating layers of the transistors in the fan-out gates, thereby minimizing the gate tunneling current. The proposed circuit technique lowers the total leakage power by up to 77% and 97% as compared to the standard dual-threshold voltage domino logic circuits at the high and low die temperatures, respectively. Similarly, a 22% to 44% reduction in the total leakage power is observed as compared to a previously published sleep switch scheme in a 45-nm CMOS technology. The energy overhead of the circuit technique is low, justifying the activation of the proposed sleep scheme by providing a net savings in total energy consumption during short idle periods.     

A new approach to power estimation and reduction in CMOS digital circuits

Modelling and optimization of dynamic capacitive power consumption in digital static CMOS circuits, taking into consideration a reason of a gate switching—gate control mode, is discussed in the present paper. The term ‘gate control mode’ means that a number and type of signals applied to input terminals of the gate have an influence on total amount of energy dissipated during a single switching cycle. Moreover, changes of input signals, which keep the gate output in a steady state, can also cause power consumption. Based on this observation, complex reasons of power losses have been considered. In consequence, the authors propose a new model of dynamic power consumption in static CMOS gates. Appropriate parameters’ calculation method for the new model was developed. The gate power model has been extended to logic networks, and consequently a new measure of the circuit activity was proposed. Switching activity, which is commonly used as a traditional measure, characterizes only the number of signal changes at the circuit node, and it is not sufficient for the proposed model. As the power consumption parameters of CMOS are dependent on their control mode, the authors used probability of the node control mode as a new measure of the circuit activity. Based on the proposed model, a procedure of combinational circuit optimization for power dissipation reduction has been developed. The procedure can be included in a design flow, after technology mapping. Results of the power estimation received for some benchmark circuits are much closer to SPICE simulations than values obtained for other methods. So the model proposed in this study improves the estimation accuracy. Additionally, we can save several percent of the consumed energy.     

能量回收电容耦合逻辑及其综合方法

提出了一种新型能量回收电路ERCCL（能量回收电容耦合逻辑）,该电路的能耗低于传统CMOS电路及其他能量回收电路．ERCCL利用电容耦合进行逻辑求值,因此可以在一个门中低能耗地实现高扇入、高复杂度的逻辑．同时ERCCL是一种阈值逻辑．所以一个基于ERCCL的系统可以大大减少逻辑门数,从而降低系统能耗．针对ERCCL提出了一种阈值逻辑综合方法．用基准电路集MCNC做了相应的实验．与SIS的综合结果相比,该方法大约减少80％的逻辑门．     

能量回收电容耦合逻辑及其综合方法

提出了一种新型能量回收电路ERCCL(能量回收电容耦合逻辑),该电路的能耗低于传统CMOS电路及其他能量回收电路.ERCCL利用电容耦合进行逻辑求值,因此可以在一个门中低能耗地实现高扇入、高复杂度的逻辑.同时ERCCL是一种阈值逻辑.所以一个基于ERCCL的系统可以大大减少逻辑门数,从而降低系统能耗.针对ERCCL提出了一种阈值逻辑综合方法.用基准电路集MCNC做了相应的实验.与SIS的综合结果相比,该方法大约减少80%的逻辑门.